IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 12, DECEMBER 2004
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A Modular 32-Site Wireless Neural
Stimulation Microsystem
Maysam Ghovanloo, Member, IEEE, and Khalil Najafi, Fellow, IEEE
Abstract—This paper presents Interestim-2B, a modular 32-site
wireless microstimulating ASIC for neural prosthesis applications, to alleviate disorders such as blindness, deafness, and severe
epilepsy. Implanted just below the skull along with a high-density
intracortical microelectrode array, the chip enables leadless operation of the resulting microsystem, accepting power and data
through an inductive link from the outside world and inserting
information into the nervous system in the form of stimulating
currents. Each module contains eight current drivers, generating
100 M
stimulus currents up to 270 A with 5-b resolution,
output impedance, and a dynamic range (headroom voltage) that
extends within 150 mV of the 5 V supply rail, and 250 mV of the
ground level. As many as 64 modules can be used in parallel, to
drive multiprobe arrays of up to 2048 sites, with only a pair of
connections to a common inductive–capacitive (LC) tank circuit,
while receiving power (8.25 mW/module) and data (2.5 Mb/s)
from a 5/10-MHz frequency shift keyed carrier. Every 4.6 mm
4.6 mm chip fabricated in a 1.5- m, 2M/2P standard CMOS
process through MOSIS, houses two modules and generates up to
65 800 stimulus pulses/s.
•
Index Terms—Charge balancing, current source, frequency shift
keying, implantable electronics, inductive coupling, microstimulator, modular architecture, neural prosthesis, voltage compliance,
wireless.
•
I. INTRODUCTION
A
UDITORY function restoration in profoundly deaf individuals has been successfully achieved by implanting
wireless microstimulators capable of electrically stimulating the
cochlea or auditory brainstem [1]. In spite of extensive research,
however, visual prostheses and artificial vision, which have a
longer history than some of the commercialized implantable
devices such as deep-brain and spinal cord stimulators, have
not yet been widely utilized in the blind [2]–[9]. The reason
is the greater complexity of the visual system, which imposes
severe technological challenges on an implant in terms of the
following areas.
• Number of stimulating sites: The most advanced cochlear
implants have 22–30 stimulating sites. Yet, a patient can
converse on the phone with as low as six sites. For a
Manuscript received April 23, 2004; revised July 2, 2004. This work was supported in part by the National Institutes of Health under Contract NIH-NINDSN01-NS-9-2304, and the work was performed at the WIMS Engineering Research Center shared facilities supported by the National Science Foundation
under Award EEC-0096866.
M. Ghovanloo is with the Bionics Laboratory, Department of Electrical
and Computer Engineering, North Carolina State University, Raleigh, NC
27695–7914 USA (e-mail: mghovan@ncsu.edu).
K. Najafi is with the Center for Wireless Integrated Microsystems, University
of Michigan, Ann Arbor, MI 48109-2122 USA.
Digital Object Identifier 10.1109/JSSC.2004.837026
•
•
visual implant on the other hand, psycho-physiological
experiments with a pixelized vision have shown that a
minimum of 625 pixels are needed to restore a functional
visual sensation [4], [5]. It is also envisaged that a
minimum of 1000 sites would be needed for being able
to read text with large fonts [6].
Stimulation strategy: The auditory nerve consists of about
30 000 nerves, which should be tonotopically stimulated
to attain the right hearing perception. After 30 years of research, finding the best speech processing and stimulation
strategy is still a hot topic in biomedical signal processing
[1]. The optic nerve is made up of 1.2 million nerves and
the relationship between the optical image and the activity
in these nerves is yet to be understood [5]. Therefore,
development of an efficient image processing and visual
stimulation strategy might not happen in the near term. As
a result, today’s visual implants should provide the maximum level of flexibility to be able to support most of the
stimulation strategies that will emerge in the future.
Power consumption: Leadless operation of the implantable devices is a necessity to reduce the risk of
infection and patient discomfort as well as increase the
implant robustness. Those implants with less power
requirement ( 100 W), such as pacemakers, have an
internal long lifetime battery that can last more than
ten years. The implants with high power requirements
( 1 mW) or extreme size constraints such as auditory or
visual prostheses need to be inductively powered by two
magnetically coupled coils that constitute a transformer
and one of them is embedded in the implantable device
[5], [9].
Bandwidth: The human eye natural bandwidth is about
60 Hz [2]. Addressing and controlling more than
1000 stimulating sites based on the adopted stimulation strategy at this frequency needs several megahertz
of bandwidth across the inductive link. Wireless networks have achieved tens of megahertz of bandwidth by
increasing the carrier frequency well into the gigahertz
range. In biomedical implant applications, however, the
challenge is to achieve a wide bandwidth with a carrier
frequency that is limited to 20 MHz due to the high
tissue electromagnetic absorption at higher frequencies
[10] as well as the coupled coils self-resonance.
Implant Size: So far, visual implants have been tested
below/above the retina, around the optic nerve, and on
the visual cortex with planar, cuff, and, penetrating electrodes, respectively. Each of these methods has its own
unique set of surgical and physiological advantages and
0018-9200/04$20.00 © 2004 IEEE
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 12, DECEMBER 2004
limitations [2], [5]. Nonetheless, what is in common for
all of them is the extreme limitation in size for minimal
invasiveness. Full integration and minimization of the
number of hybrid components seem to be the only ways
to achieve a visual implant with reasonable size.
Several researchers have addressed the above problems with
limited success [2]–[9], [11]–[16]. This paper presents Interestim-2B (IS-2B), a 32-site wireless microstimulator ASIC
with a modular architecture [17]. Every IS-2B module is a
self-contained, fully integrated unit (two modules per chip)
that operates with only a pair of connections to a hybrid LC
tank. The IS-2B individually addressable modules would allow
assembling a 64-module
32-site wireless microstimulating
system while sharing the same hybrid LC tank. Therefore, a
cluster of 32 IS-2B chips in a single implant or a network
of stand-alone implants under a single external coil would be
capable of addressing up to 2048 stimulating sites, which advances the state-of-the-art in nearly all of the aforementioned
directions. Because of the similarities between different sensory or motor regions of the cerebral cortex, it is likely that a
high-density electrode array architecture, designed for IS-2B,
be well suited for several applications [2]. Hence, the ultimate goal is to develop multipurpose button-sized wireless
microstimulating three-dimensional (3-D) electrode arrays by
mounting IS-2B chips on micromachined platforms that are
connected to passive microelectrodes, or implementing the
IS-2B circuitry on the backend of active silicon micromachined probes, as shown in Fig. 1 [17], [18].
Section II describes the system overview and modular architecture of the IS-2B. Section III presents the major circuit
blocks in more detail along with simulation results. Experimentally measured results are reported in Section IV, followed by
the concluding remarks in Section V.
II. SYSTEM OVERVIEW
A. External Components
The block diagram of the IS-2B wireless neural stimulation
microsystem is shown in Fig. 2 [17]. The external components
of the system are enclosed in a dashed box on the left side of
Fig. 2(a). The rest of the system, which is fully integrated extank circuit, is small enough to be
cept for the receiver
implanted in the body. Digitized image or sound information,
acquired by a miniature camera or microphone for a visual or auditory prosthesis, respectively, is sent to a portable computer or
PDA as shown in Fig. 1. The computer processes the incoming
information in real-time and generates a series of stimulation
command-frames that can cause a set of spatiotemporal stimulus
pulses based on the adopted stimulation strategy at a two-dimensional (2-D) or 3-D array of stimulating sites that is implanted in
the targeted neural tissue. The command-frames are arranged in
bursts of nonreturn-to-zero (NRZ) serial data bit stream, which
are then modulated into a square-shaped frequency shift keyed
(FSK) signal at 5 and 10 MHz by a high-speed digital I/O card
(National Instruments DIO-6534) as shown in Fig. 3. To achieve
a high data rate close to the carrier frequency, a particular phase-
Fig. 1.
Multipurpose button-sized wireless microstimulating 3-D array [18].
coherent FSK protocol is utilized in which logic “1” is transmitted by a single cycle of the carrier at frequency and logic
“0” is transmitted by two cycles of the carrier at . The carrier frequency switches at a small fraction of a cycle and only
at negative-going (or positive-going) zero crossings. Choosing
, results in a constant data rate that can be as high as
[19]. In practice, limitation in the inductive link bandwidth,
in spite of using a wideband series-parallel LC tank combination for the transmitter coil [20], does not allow utilization of
the modulation full-speed with an acceptably low bit-error rate
(BER). In order to improve the BER, the FSK carrier spectral
bandwidth was decreased by repeating every bit twice. ThereMHz and
MHz resulted in a data
fore, choosing
rate of 2.5 Mb/s, which should be enough for a visual prosthesis
with minimum functional resolution [13].
The square-wave digital FSK signal, which has a 2.5-V dc
component, passes through dc-level adjustment circuit and a
band-pass filter (10 kHz–5.6 MHz) to turn into a bipolar sinusoidal FSK carrier (Fig. 3) before being amplified by a wideband
power amplifier (Amplifier Research, PA). Finally, the amplified FSK carrier, which contains both data and power for the
IS-2B implant, is transmitted through a wideband, low-Q inand
ductive link that is set up by generating two zeros at
across the transmitter 50 output with a series-parallel
tank combination, to reshape the inductive link passband, as
GHOVANLOO AND NAJAFI: A MODULAR 32-SITE WIRELESS NEURAL STIMULATION MICROSYSTEM
Fig. 2.
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(a) Block diagram of the IS-2B microsystem. (b) Current drivers schematic diagram [17].
B. IS-2B Architecture
Fig. 3.
High data rate phase-coherent FSK modulation protocol [19], [20].
described in [20]. A wideband inductive link is necessary for
achieving high data rates in order to eliminate residual ringing
(intersymbol interference) on the receiver side when the carrier
frequency switches from to and vice versa.
The implantable part of the IS-2B wireless stimulating mitank circuit, IS-2B modcrosystem consists of a receiver
ules (2–64), and passive probes, which interface with the neural
tissue [21]. An IS-2B module is a system-on-a-chip (SoC) consisting of all the gray boxes in Fig. 2(a) and blocks in Fig. 2(b).
There are two identical modules in each IS-2B chip, supporting
a total of 64 stimulating sites. The receiver
tank circuit
provides each module with inductively coupled power and data.
Power Supply: Implant size reduction is achieved in the
power supply block by utilizing a fully integrated full-wave
CMOS rectifier [22], [23], followed by an on-chip ripple
. The previous implants used either
rejection capacitor
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Fig. 4. Format of the IS-2B 18-b command frame.
hybrid rectifiers or an inefficient half-wave substrate diode [11],
[12], [14]. A series-type regulator stabilizes
at 5 V for
unregulated inputs 6.7 V. In order to ensure safe operation,
especially at start-up, a power-on-reset (POR) circuit activates
, and
a global reset line at start-up, continuously monitors
releases the reset line 70 s after the regulator voltage exceeds
4.8 V to ensure that the digital circuits start from a known
state (reset) after transients are passed. It also shuts the entire
3.4 V.
microstimulator down when
Receiver Block: Receiver is the second block that is connected directly across the
tank circuit. Using a new FSK
demodulator, which is designed specifically for a phase-coherent FSK modulated signal (Fig. 3), data bits are detected
by measuring the duration of each received carrier cycle. The
demodulator also derives a constant frequency clock from the
phase-coherent FSK carrier to sample the recovered data bits
and run the IS-2B digital circuitry [19], [20].
Digital Controller: Isochronous communication scheme is
adopted to provide a fast, steady, and uninterrupted data stream,
which is preferred for video applications [24]. Fig. 4 shows
the format of IS-2B 18-b command-frames, which contain a
data byte and an address byte, each accompanied by a parity
bit. In a burst of serial data bit stream, these command-frames
are transmitted back to back, while being separated by 1-b
spacers. In the digital controller block, an 18-b shift register
and a sequencer convert the serial data bit stream to parallel,
while a pattern detector resets the sequencer upon receiving a
unique frame (0FF0FFh) to maintain synchronization with the
transmitter. The address byte consists of a 6-b module address
). The module
( – ) and a 2-b register-address ( ,
address is compared to the module’s hard-wired user-programmable address, and if they match, and there is no parity
error, the data byte ( – ) is stored in one of the four internal
registers that is defined by the register-address. Otherwise, the
received command-frame is ignored with no further action. The
module’s hard-wired 6-b address, which is originally set to 3Fh,
can be changed by laser-cutting the hardwired links in order to
assign a unique address to each one of up to 64 modules that
can operate in parallel in a multichip system.
Current Drivers (CD): Each module has eight current
–
) that are enclosed in dashed boxes in
drivers (
Fig. 2(b). Each
has both nMOS current sink
and
pMOS current source
versions of a closed-loop circuit
topology that utilizes the above transistors in deep triode region
as linearized voltage-controlled resistors (VCR) by applying
, while actively maintaining their
a larger than threshold
at 80 mV [25], [26]. Each
, which is multiplexed
among four stimulating sites, is controlled by two specific
) and two shared mode bits (
,
).
status bits ( ,
Combinations of these bits can connect each stimulating site
to
, current source, GND, current sink, common analog
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 12, DECEMBER 2004
line (CAL), or keep it at high- , in four different operating
modes, as summarized in Table I. The result is a wide variety of
functions and stimulation strategies that can be used depending
on the application. An additional reference line [not shown in
Fig. 2(b)], which stays at high- in bipolar stimulation (between two sites), can be connected to
, GND, or CAL under
,
) control in Mode-0 for monopolar
feedback bits (
stimulation (between one site and the reference electrode) [21],
[27].
Register Bank: Two current amplitude registers [
and
in Fig. 2(a)] store two sets of 5-b stimulus amplitude
and 1-b offset information for a dual pair of voltage-mode
digital to analog converters: DAC-p (
,
) and DAC-n
(
,
). These DACs control the pMOS VCR current
sources and nMOS VCR current sinks in the CD blocks [25].
and
, called mode bits (
,
The last two bits of
) and feedback bits (
,
), respectively, indicate
the microstimulator mode of operation and the type of back
and
)
telemetry feedback. Two site status registers (
store the individual status bits ( ,
) for each
(see
Table I).
Timing: The timing of the stimulus pulses in IS-2B is controlled by the sequence of successive command-frames. In other
words, every change in the mode of operation, sites configuration, and stimulus amplitude is instructed to the implant by the
external system in real time. This method, which is described in
more detail in a measured example in Section IV, provides the
highest level of flexibilitily in generating any arbitrary stimulus
waveform from any of the sites [13]. In addition, since the external controller takes care of the time keeping functions, there is
no need for on-chip timers and their associated logic. This has
significantly simplified the IS-2B digital circuitry, and consequently reduced its circuit area in a 1.5- m fabrication process.
These advantages, however, come at the expense of a larger required bandwidth, which is not a limiting factor with utilization
of the high-speed digital FSK demodulator that is described in
Section III-B [19], [20].
Back Telemetry: The power transmission efficiency of the
inductive link highly depends on the relative distance between
and receiver
coils [29]. Because of
the transmitter
the variations in the relative coils distance with patient’s movements, an open-loop, constant power transmission scheme can
result in significant fluctuations in the implant received power,
which might exceed the on-chip regulator dynamic range. To externally regulate the implant received power (coarse regulation),
in addition to the on-chip regulator (fine regulation), a closed
as a feedback, is foreseen
loop system, which monitors
to stabilize the implant received power by adjusting the external
power amplifier gain. Another purpose of the back-telemetry
block is to wirelessly monitor the stimulating sites potential
through CAL. The stimulating site voltage can be an indicator of
the site and tissue impedance, while passing a 1-kHz sinusoidal
current, as well as charge balancing situation at the end of each
stimulus [27]. These measurements are necessary especially in
long-term chronic stimulations to check for the defective sites
and stimulation safety. The back-telemetry block selects one out
of four possible feedbacks,
, CAL,
, and
, based
on the feedback bits, as shown in Fig. 2(a). This block then pulse
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TABLE I
CURRENT DRIVER TRUTH TABLE
width modulates (PWM) the selected analog input signal, and
shifts the impedance across , which is reflected back to ,
due to their mutual coupling (passive back telemetry by load
shift keying) [28].
III. CIRCUIT IMPLEMENTATION
A. Integrated Full-Wave CMOS Rectifier
Diode-connected MOS transistors are used to form a fully
integrated full-wave CMOS rectifier as shown in Fig. 5(a) [21],
and
conduct in the forward direction when the
[23].
coil voltage at
or
is higher than
, while delivfrom the coil to the load.
passes through
ering current
the load, which is the rest of the chip, to the grounded P-sub,
,
, and
.
strate and returns back to the coil via
The rectifier drop-out voltage,
, should be minimized to decrease power dissipation in the rectifier block, increase the average rectified dc voltage available at the regulator
input, and lower the minimum operational receiver coil voltage.
passes through a diode-connected MOS
When
(1)
where
is the MOS threshold voltage,
is the intrinsic
transconductance, and
and are the transistor width and
can be minimized in the circuit by
length, respectively.
eliminating the body effect. To minimize the second term in
ratio should be increased as much as the rectifier size
(1),
constraints permit (4800 m 1.6 m).
Fig. 5(b) shows half of the rectifier symmetrical cross section.
In order to protect the rectifier against latch-up and substrate
leakage, the separated N-well voltage should be dynamically
controlled. Two auxiliary pMOS transistors are added to each
or the
rectifying pMOS to connect the separated N-well to
coil terminals ( and ), whichever is at a higher potential.
shares its source and
The source-side auxiliary pMOS
gate terminals with the diode-connected
and turns on
is ON, connecting the separated N-well to ,
whenever
at this time. The drain-side
which is higher than
shares its source terminal with
auxiliary pMOS
Fig. 5. (a) Full-wave CMOS rectifier schematic. (b) Half of the rectifier
symmetrical cross section [21], [23].
and turns on whenever the coil voltage is less than
by at
, connecting the separated N-well to
. Since
least
no current passes through the auxiliary MOSFETs when they
turn on, their drain-source voltage is close to zero. Therefore,
they prevent the parasitic vertical PNP transistors from turning
on and leave little chance for latch-up or any leakage current
to the substrate. Another advantage of this circuit, which is
also used in charge pumps [30], is eliminating the body effect
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 12, DECEMBER 2004
on the rectifying pMOS transistors, thus, reducing the rectifier
drop-out voltage according to (1). On the nMOS transistors
side, common-collector vertical PNP transistors and parasitic
and
facilitate current return
diodes in parallel to
back to the coil when its voltage goes below the grounded
. To decrease the risk of
substrate by a diode-drop
latch-up even further, the pMOS complexes and the nMOS
pair are widely separated in the layout and protected by N
and P guard-rings, respectively [31].
B. High Data Rate Digital FSK Demodulator
Fig. 6(a) shows the receiver block schematic diagram, which
is a high-speed digital FSK demodulator, and Fig. 6(b) shows
simulated waveforms at different nodes of the receiver block
[19], [20]. A cross-coupled differential pair that is directly contank squares up the incoming sinusoidal
nected across the
FSK carrier signal
. An -b
ripple counter runs
, which is generated by a five-stage
by a time-base clock
is high and resets when
is
ring oscillator, only when
MHz, is chosen based
low. The oscillator frequency,
on
(2)
MHz
MHz, such that the counter
which yields
most significant bit (MSB) goes high during long carrier halfand stays low during short carrier half-cycles at
cycles at
. Therefore, MSB discriminates between short (logic “0”) and
long (logic “1”) carrier cycles by generating short pulses associated only with the long cycles. A digital circuit then derives the
demodulated serial data bit stream (Data_Out) and a constant
frequency clock (Clock_Out) from a combination of MSB and
.
It should be noted that this scheme is highly robust, and as
is in the desired range, indicated by (2), the phase
long as
noise and process-dependent frequency variations of the on-chip
ring oscillator or the external transmitter do not affect the data
and clock recovery performance [20]. In the specific simulaand
are chosen equal to
tion of Fig. 6(b), for example,
8 and 4 MHz, respectively. Nevertheless, the demodulator still
works because the carrier frequencies still satisfy (2). A latency
exists between the transmitted and received data,
of
which does not cause a significant problem in this biomedical
application.
C. Large Voltage Compliance, High Output Impedance
Current Driver
In current microstimulation applications, the load is highly
capacitive, due to the electrode–electrolyte impedance at the
interface of the metallic stimulating sites and tissue fluids,
and variable from one site to another, or during the lifetime of
one site. Therefore, the stimulator output voltage can change
significantly, which should not affect the desired stimulus
current level. Cascode or wide swing cascode current mirrors are the conventional current sources that are used in
many microstimulator designs including [11]–[16] to generate
site-voltage-independent stimulus currents, while providing
high output impedance. High output impedance in these cir-
Fig. 6. (a) Phase-coherent FSK demodulator
(b) Demodulator simulated waveforms [19], [20].
schematic
diagram.
cuits comes at the expense of a reduction in voltage compliance
(headroom), and an increase in power dissipation in the current
source due to the unused voltage, both of which are undesirable in a wireless implantable microstimulator, where the
supply voltage and permissible temperature rise due to power
dissipation are limited. In IS-2B, pMOS and nMOS versions
of a voltage-to-current conversion circuit, called VCR current
source and shown in Fig. 2(b), are used in CDs to generate
the stimulus pulses. The VCR current sources/sinks, which
are controlled by voltage-mode DACs, provide larger voltage
compliance, show higher output impedance, and occupy less
circuit area compared to their conventional counterparts [25],
[26]. The following discussion focuses on the nMOS current
sinks, however, it also applies to their dual pMOS current
source circuits.
In Fig. 2(b), a pMOS-input folded-cascode operational amat
mV, while DAC-n
plifier (Amp-p) maintains
gate voltage
according to
. All the
controls the
biasing and reference voltages and currents are generated from
a band-gap reference generator, such that many process-dependent parameter variations would cancel out [26]. As long as
,
operates in the triode
region, and the output stimulus current will be defined by
(3)
GHOVANLOO AND NAJAFI: A MODULAR 32-SITE WIRELESS NEURAL STIMULATION MICROSYSTEM
2463
Fig. 8. IS-2B die microphotograph and floor-plan [17].
evident from one of the peaks in this curve. Increasing the
number of parallel transistors reduces the transconductance
ripple at the expense of larger circuit area. Fig. 7(b) shows a
simulated comparison between the output current versus driven
output voltage of the VCR and conventional current sources.
All of the current sources were designed to occupy roughly the
mm and sink 100
when the
same area on a chip
stimulating site voltage is 2.5 V. It is obvious from Fig. 7(b)
curves that the VCR current source has the closest output
characteristics to an ideal current source [26].
IV. MEASUREMENT RESULTS
Fig. 7. (a) Circuit simulation of the VCR output current and transconductance
versus DAC-n control voltage. (b) Comparison between the output
characteristics of the VCR and other conventional current sources [25],
[26].
which is linear for small
values close to
. For larger
,
decreases due to the carrier mobility degradation at
high vertical field and the actual stimulus current is less than
what is predicted by (3). On the other hand, the nMOS drain
when it is biased
current goes above the linear trace versus
in the
in saturation. This suggests that if the drain current of
triode region is added to the drain current of another transistor,
, biased in the saturation region by receiving a fraction of
on its gate
, even though the individual transistor
currents are nonlinear, their sum can be tailored to be linear. This
goes out of saturation at
procedure can be repeated when
by adding another parallel nMOS until the entire
higher
from
to
is linearized.
range of
Fig. 7(a) shows the simulated contribution of each indi) to
, which
vidual parallel nMOS transistor ( –
. It also
is the sum of all four drain currents, versus
curve
shows the fairly constant slope of the
A/V), which is a measure of the VCR
(
current sink linearity. The effect of each parallel transistor is
The IS-2B chip was fabricated in the AMI 1.5- m two-metal
two-poly n-well standard CMOS process through the MOSIS
foundry by fitting two identical IS-2B modules in a 4.6 mm
4.6 mm die. Fig. 8 shows a die microphotograph and
floor-plan of the IS-2B. The chip was operated as described
in Section II-A, and shown in Fig. 2(a). The command-frames
were generated automatically from user-defined stimulation
parameters that were entered into a graphical user interface,
called digital pattern generator (DPG-6), running in LabView-7
environment. Table II summarizes the experimentally measured
IS-2B specifications [17].
Fig. 9 shows the receiver block measured waveforms. The
and
received 5/10 MHz FSK carrier, which is measured at
as well as their subtraction across the
tank, can be seen on
the three lower traces. Depending on the transmitter and receiver
coil designs and their orientation, the power amplifier gain is
manually adjusted such that at a nominal coupling distance of
is induced across the
tank. The upper
5 mm, 24–28
two traces from top show the recovered clock and demodulated
serial data bit stream at 2.5 MHz and 2.5 Mb/s, respectively. To
the authors’ knowledge, this is the fastest data rate reported so
far in inductively powered applications [9]–[14]
Fig. 10(a) shows the linearity of the measured stimulus
versus 5-b stimulus amplitude command (DAC’s
current
digital input) for both VCR current source and current sink
270 A full-scale current range [also see
circuits in the
Fig. 7(a)]. Fig. 10(a) also shows a good matching between
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 12, DECEMBER 2004
TABLE II
INTERESTIM-2B SPECIFICATIONS
Fig. 9. Receiver block measured waveforms. Top two traces: recovered clock
and demodulated data (5 V/div). Bottom three traces: received FSK carrier
across the L C tank (20 V/div) [19].
the sourcing and sinking currents for the entire range, which
is important in generating charge balanced stimulus pulses.
Fig. 10(b), which is measured with an HP4155A semiconductor
parameter analyzer, shows the sinking and sourcing stimulus
currents at different digital amplitude levels, while sweeping
[also see Fig. 7(b)]. The
the site voltage from GND to
VCR current sink (source) can achieve a voltage compliance of
97% (95%) of the 5-V supply voltage, while maintaining high
output impedance in the 100 M range to keep the desired
stimulation currents constant within 1%, irrespective of the site
and tissue impedances [25].
A sample measured stimulation burst is shown in Fig. 11. The
two upper traces show the integrated full-wave CMOS rectifier
350 s for the reguand series regulator outputs. It takes
lator to startup and sink current. Meanwhile, the rectifier output
, which is inrapidly increases up to 15 V, while charging
creased to 10 nF with an off-chip surface-mount capacitor to
improve ripple rejection. As soon as the regulator starts sinking
current, the rectified dc voltage reduces to 8 V and stays at
at 5 V. One advanthis level, while the regulator stabilizes
tage of the FSK modulation for this application over the more
popular ASK scheme is the absence of the low-frequency ripples on the rectified carrier signal due to the carrier amplitude
modulation. The POR activates the global reset line (third trace)
at the startup and keeps the entire implant in the reset-mode until
4.8 V to safely start the digital circuitry from
70 s after
a known state. The receiver block immediately starts recovering
Fig. 10. (a) Measured current driver I
versus 5-b digital current-amplitude
command. (b) Measured stimulus currents at different digital amplitude levels,
while sweeping a stimulation site voltage from GND to V
[25], [26].
the serial data bit stream at 2.5 Mb/s (fourth trace), which consists of back to back command-frames in the format shown in
Fig. 4. The stimulation burst, shown on the three lower traces,
starts as soon as the digital controller block synchronizes with
the transmitter by detecting the unique frame 0FF 0FFh which is
sent between every two biphasic stimulation pulses in this specific example.
GHOVANLOO AND NAJAFI: A MODULAR 32-SITE WIRELESS NEURAL STIMULATION MICROSYSTEM
2465
pulses/s at 270 A full-scale current. Eight current drivers
per module provide large voltage compliance up to 97% of the
5-V supply, and high output impedance in the 100-M range,
which are two key parameters in wireless microstimulators.
4.6 mm IS-2B chip, fabricated in the AMI
Every 4.6 mm
1.5- m standard CMOS process, houses two modules and has a
total of 13 000 transistors. A prototype implant is developed for
acute wireless neural microstimulation, using the IS-2B chip.
Further in vitro measurements in saline and in vivo experiments
in an animal model (rat) are under way [21], [27].
ACKNOWLEDGMENT
The authors would like to thank Prof. K. D. Wise and Dr. W. J.
Heetderks for their guidance.
Fig. 11. Experimentally measured stimulation burst waveforms. From top:
CMOS rectifier output, regulator output, POR output, demodulated data bit
stream, Site0 single-ended voltage, differential voltage across a 10-k
resistor
connected between Site0 and Site4, Site0 single-ended voltage (5 V/div) [17].
A 10-k load, resembling sites and tissue impedances, is connected between Site0 and Site4, and the site voltages are measured both differentially and single ended. In this experiment,
no external capacitor was added to the resistive load to keep the
current and voltage waveforms proportional. Fig. 11 inset shows
a magnified view of the four lower traces. In this example, prior
and
output
initialization commands have switched
multiplexers to Site0 and Site4, respectively, set the stimulus
,
current amplitudes to full-scale for both phases (
), and selected the operation in Mode-3 (Table I).
In every bipolar-biphasic pulse between Site0 and Site4, the first
stimulation command connects Site4 (Site0) to a source (sink).
As a result, 270 A flows from Site4 to Site0 in the first stimulus
phase for the duration of the next command-frame (7.6 s). The
second command puts both sites in the high- state to create an
inter-phase delay. The third command swaps the sites status and
therefore, 270 A flows back from Site0 to Site4 in the second
stimulus phase. Finally, the fourth command deactivates both
sites by returning them to the high- state. The timing resolution of the IS-2B system is equal to the duration of every 18-b
command-frame plus the spacer bit, which is 7.6 s at 2.5 Mb/s.
This is an order of magnitude finer than the actual neural signals
bandwidth ( 10 kHz). Considering that at least two commands
are required per stimulation phase, IS-2B is capable of generating up to 65 800 pulses/s. The timing accuracy of the IS-2B
system (50 ns) depends on the external timing controller, which
is the DIO-6534 high-speed digital I/O card (National Instruments, TX) with a 20-MHz internal time-base.
V. CONCLUSION
IS-2B, a 32-site wireless neural microstimulation system on
a chip, is developed with a modular stand-alone architecture,
which is easily extendable to 64 modules (2048 sites) with
only two connections between every module and a common
receiver LC tank. IS-2B modules receive inductive power
(8.25 mW/module) and high-speed data (2.5 Mb/s) from a
5/10 MHz FSK carrier, while generating up to 65 800 stimulus
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Maysam Ghovanloo (S’00–M’04) was born in
1973. He received the B.S. degree in electrical engineering from the University of Tehran, Tehran, Iran,
in 1994, and the M.S. (Hons.) degree in biomedical
engineering from the Amirkabir University of Technology, Tehran, in 1997. He also received the M.S.
and Ph.D. degrees in electrical engineering from the
University of Michigan, Ann Arbor, in 2003 and
2004, respectively. His undergraduate research was
focused on developing an 8-kW power supply for
Nd:YAG lasers. At the Etrat Institute of Technology,
he worked on computer interfaces for industrial automotive robotic applications. His M.S. thesis was on development of a multisite physiologic recording
system for investigation of neural assemblies, and his Ph.D. research was on
developing a wireless microsystem for neural stimulating microprobes.
From 1994 to 1998, he worked part-time at the IDEA Inc., Tehran, where
he participated in the development of the first modular patient care monitoring
system in Iran. In December 1998, he founded Sabz-Negar Rayaneh Co. Ltd. to
manufacture physiology and pharmacology research laboratory instruments. In
the summer of 2002, he was with Advanced Bionics Inc., Sylmar, CA, working
on the design of spinal-cord stimulators. He joined the faculty of North Carolina
State University in August 2004, where he is currently an Assistant Professor in
the Department of Electrical and Computer Engineering.
Dr. Ghovanloo has received awards in the operational category of the 40th and
41st DAC/ISSCC student design contest in 2003 and 2004, respectively. He is a
member of Tau Beta Pi, the IEEE Solid-State Circuits Society, and biomedical
engineering societies.
Khalil Najafi (S’84–M’86–SM’97–F’00) was born
in 1958. He received the B.S., M.S., and the Ph.D.
degrees in 1980, 1981, and 1986 respectively, all in
electrical engineering from the Department of Electrical Engineering and Computer Science, University
of Michigan, Ann Arbor.
From 1986 to 1988, he was employed as a
Research Fellow, from 1988 to 1990 as an Assistant
Research Scientist, from 1990 to 1993 as an Assistant
Professor, from 1993 to 1998 as an Associate
Professor, and since September 1998, he has been
Professor and Director of the Solid-State Electronics Laboratory, Department
of Electrical Engineering and Computer Science, University of Michigan.
His research interests include micromachining technologies, micromachined
sensors, actuators, MEMS, analog integrated circuits, implantable biomedical
microsystems, micropackaging, and low-power wireless sensing/actuating
systems.
Dr. Najafi was awarded a National Science Foundation Young Investigator
Award from 1992 to 1997, and was the recipient of the Beatrice Winner Award
for Editorial Excellence at the 1986 International Solid-State Circuits Conference, the Paul Rappaport Award for co-authoring the best paper published in
the IEEE TRANSACTIONS ON ELECTRON DEVICES, and the Best Paper Award at
ISSCC 1999. In 2003, he received the EECS Outstanding Achievement Award.
He received the Faculty Recognition Award in 2001, and the University of
Michigan’s Henry Russel Award for outstanding achievement and scholarship
in 1994, and was selected Professor of the Year in 1993. In 1998, he was named
the Arthur F. Thurnau Professor for outstanding contributions to teaching
and research, and received the College of Engineering’s Research Excellence
Award. He has been active in the field of solid-state sensors and actuators for
more than twenty years, and has been involved in several conferences and workshops dealing with solid-state sensors and actuators, including the International
Conference on Solid-State Sensors and Actuators, the Hilton-Head Solid-State
Sensors and Actuators Workshop, and the IEEE/ASME Micro-Electromechanical Systems (MEMS) Conference. He is the Editor for Solid-State Sensors
for IEEE TRANSACTIONS ON ELECTRON DEVICES, an Associate Editor for
the Journal of Micromechanics and Microengineering, Institute of Physics
Publishing, and an editor for the Journal of Sensors and Materials. He also
served as the Associate Editor for IEEE JOURNAL OF SOLID-STATE CIRCUITS
from 2000 to 2004, and the Associate Editor for IEEE TRANSACTIONS ON
BIOMEDICAL ENGINEERING from 1999 to 2000.