AMD Confidential – Advance Information
Socket AM3 Processor
Functional Data Sheet
Publication # 40778
Revision: 1.13
Issue Date: January 2009
Advanced Micro Devices
AMD Confidential – Advance Information
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AMD Confidential – Advance Information
PID: 40778 Rev. 1.13 – January 2009
Socket AM3 Processor Functional Data Sheet
Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1
Pins
1.1
1.2
1.3
1.4
1.5
1.6
1.7
..............................................................7
Connection Diagram (Left Half) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Connection Diagram (Right Half) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Alphabetical Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Color-Coded Connection Diagram (Left Half) . . . . . . . . . . . . . . . . . . . . . . . 18
Color-Coded Connection Diagram (Right Half) . . . . . . . . . . . . . . . . . . . . . . 19
2
Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.1 Mechanical Loading for Lidded Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2 Package Insertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3 Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Contents
3
AMD Confidential – Advance Information
PID: 40778 Rev. 1.13 – January 2009
Socket AM3 Processor Functional Data Sheet
List of Figures
Figure 1. Connection Diagram (Left Half) .........................................................................................7
Figure 2. Connection Diagram (Right Half) ......................................................................................8
Figure 3. Color-Coded Connection Diagram (Left Half) .................................................................18
Figure 4. Color-Coded Connection Diagram (Right Half) ...............................................................19
Figure 5. Organic Micro Pin Grid Array Package(UOF): Top, Side, and Bottom Views
(Lidded) .............................................................................................................................21
4
List of Figures
AMD Confidential – Advance Information
PID: 40778 Rev. 1.13 – January 2009
Socket AM3 Processor Functional Data Sheet
List of Tables
Table 1.
Pin Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2.
HyperTransport™ Technology Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3.
DDR2 SDRAM Memory Interface Pin Descriptions
(Supports DDR2 and DDR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4.
Clock Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 5.
Thermal Observation/Control Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 6.
Power Supply/Voltage Regulator Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . 11
Table 7.
JTAG Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 8.
Debug Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 9.
Miscellaneous Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 10. Mechanical Loading for Lidded Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11. Recommended Number of Insertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
List of Tables
5
AMD Confidential – Advance Information
PID: 40778 Rev. 1.13 – January 2009
Socket AM3 Processor Functional Data Sheet
Revision History
Date
Revision
Description
January 2009
1.13
Third NDA release.
• M_VDDIO_PWRGD changed to not supported. (See Table 3 on page 10.)
June 2008
1.11
Second NDA release.
• Added MA/B_EVENT_L pins.
• Added NP/VSS and NP/RSVD pins.
August 2007
1.07
Initial NDA release.
Revision History
6
AMD Confidential – Advance Information
PID:40778 Rev 1.13 – January 2009
1
Socket AM3 Processor Functional Data Sheet
Pins
1.1 Connection Diagram (Left Half)
A
2
VOID
3
VSS
4
5
6
7
8
VDDNB
DBREQ_L
VDDNB
VSS
CLKIN_H
9
VSS
10
11
12
TEST25_H
VSS
VDDR
B
VOID
NP/ RSVD
VDD
VSS
VDDNB
DBRDY
VDDNB
CLKIN_L
VSS
TEST25_L
VSS
VDDR
C
SVC/ VID[3]
VDD
VSS
VDD
TEST14
VDDNB
RESET_L
VDDNB
PWROK
VDDA
TEST29_H
VDDR
D
VID[4]
VID[5]
VDD
TEST8
VDD
TEST17
VDDNB
LDTSTOP_L
VDDNB
VDDA
TEST29_L
VDDR
PVIEN/ VID[
E
VID[0]
F
PSI_L
RSVD
G
VDD_FB_L
VDD_FB_H
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
Figure 1.
1
VOID
VLDT_B
1]
VLDT_B
SVD/ VID[2]
M_VDDIO_P
WRGD
L
VOID
L0_CADIN_ L0_CADIN_L L0_CADIN_
H[1]
L0_CADIN_L
[1]
[0]
H[0]
VSS
VSS
L0_CADIN_ L0_CADIN_L L0_CADIN_
H[3]
L0_CADIN_L
[3]
[2]
H[2]
VDD
VDD
L0_CADIN_ L0_CLKIN_L L0_CLKIN_H
H[4]
L0_CADIN_L
[4]
[0]
[0]
VSS
VSS
L0_CADIN_ L0_CADIN_L L0_CADIN_
H[6]
L0_CADIN_L
[6]
[5]
VDD
H[5]
VDD
L0_CTLIN_H L0_CADIN_L L0_CADIN_
[0]
L0_CTLIN_L
[0]
[7]
H[7]
VSS
VSS
L0_CADOUT L0_CTLOUT L0_CTLOUT
_L[7]
L0_CADOUT
_H[7]
_H[0]
_L[0]
VDD
VDD
L0_CADOUT L0_CADOUT L0_CADOUT
_L[5]
L0_CADOUT
_H[5]
_H[6]
_L[6]
VSS
VSS
L0_CLKOUT L0_CADOUT L0_CADOUT
_L[0]
L0_CLKOUT
_H[0]
_H[4]
VDD
_L[4]
VDD
L0_CADOUT L0_CADOUT L0_CADOUT
_L[2]
L0_CADOUT
_H[2]
_H[3]
VSS
_L[3]
VSS
L0_CADOUT L0_CADOUT L0_CADOUT
_L[0]
L0_CADOUT
_H[0]
TEST7
VDD
TEST16
VDDNB
TEST18
VDDNB
VSS
VSS
VDD
TEST9
VDD
TEST15
VDDNB
TEST19
VDDNB
M_VREF
VDD
TEST10
VDD
VSS
VDDNB
VSS
VDDNB
_H[1]
_L[1]
VDD
VDD
H
E
VOID
VLDT_B
VSS
VSS
VLDT_B
L0_CADIN_
H[8]
L0_CADIN_ L0_CADIN_L L0_CADIN_L
H[9]
[9]
VDD
VDD
[8]
L0_CADIN_
H[10]
L0_CADIN_ L0_CADIN_L L0_CADIN_L
H[11]
[11]
VSS
VSS
[10]
L0_CLKIN_H
[1]
L0_CADIN_ L0_CADIN_L L0_CLKIN_L
H[12]
[12]
VDD
VDD
[1]
L0_CADIN_
H[13]
L0_CADIN_ L0_CADIN_L L0_CADIN_L
H[14]
[14]
VSS
VSS
[13]
L0_CADIN_
H[15]
L0_CTLIN_H L0_CTLIN_L L0_CADIN_L
[1]
[1]
VDD
VDD
[15]
L0_CTLOUT
_L[1]
L0_CADOUT L0_CADOUT L0_CTLOUT
_L[15]
VSS
_H[15]
VSS
_H[1]
L0_CADOUT
_L[14]
L0_CADOUT L0_CADOUT L0_CADOUT
_L[13]
_H[13]
VDD
VDD
_H[14]
L0_CADOUT
_L[12]
L0_CLKOUT L0_CLKOUT L0_CADOUT
_L[1]
_H[1]
VSS
VSS
_H[12]
L0_CADOUT
_L[11]
L0_CADOUT L0_CADOUT L0_CADOUT
_L[10]
_H[10]
VDD
VDD
_H[11]
L0_CADOUT
_L[9]
L0_CADOUT L0_CADOUT L0_CADOUT
_L[8]
_H[8]
_H[9]
AJ
VLDT_A
VLDT_A
VLDT_A
VLDT_A
TEST6
TEST2
AK
VOID
VSS
RSVD
SA[0]
TEST26
SID
AL
VOID
VOID
ALERT_L
VSS
SIC
1
2
CPU_PRES
ENT_L
3
4
5
6
14
15
16
]
MB_DM[0]
]
VSS
]
MB_DATA[7
]
]
VSS
MB_DQS_L[ MB_DQS_H[ MB_DATA[3 MB_DATA[1
0]
MB_DATA[0
]
0]
VSS
]
MB_DATA[1
2]
3]
VSS
VDDR_SENS MB_DATA[5 MA_DATA[1 MA_DATA[6 MA_DATA[2
VDD
VDDNB_FB_ VDDNB_FB_ CORE_TYP
13
MB_DATA[1 MB_DATA[6 MB_DATA[2 MB_DATA[8
E
]
MB_DATA[4
]
]
VSS
]
MA_DQS_H[
0]
]
VSS
MA_DATA[5 MA_DATA[0 MA_DQS_L[ MA_DATA[7
]
MA_DATA[4
VDD
VSS
TEST28_L
VSS
VDD
VSS
VSS
VDD
VSS
TEST28_H
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VSS
VDD
VSS
VDD
VSS
VDD
VDD
VSS
VDD
VSS
VDD
VSS
]
0]
]
A
B
C
D
E
F
G
VSS
MA_DM[0]
VSS
H
VDD
VSS
VDD
J
VDD
VSS
VDD
VSS
K
VSS
VDD
VSS
VDD
L
VDD
VSS
VDD
VSS
M
]
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
N
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
P
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
R
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
T
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
U
HTREF0
HTREF1
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
V
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
W
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
Y
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
AA
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
AB
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
AC
VSS
AD
VDD
VSS
VDD
VSS
VDD
VSS
NP/ VSS
VOID
VOID
VDD
VSS
VDD
VDD
VSS
VDD
VSS
VDD
VSS
VDD
THERMDA
THERMDC
VSS
VSS
VDDR
TEST3
TEST23
TEST12
TCK
M_ZN
VDDR
TEST13
THERMTRI
P_L
PROCHOT_
L
7
TEST20
TEST22
TRST_L
TEST24
TEST27
TDO
TEST21
TMS
TDI
8
9
10
M_ZP
VDDIO_FB_
H
VDDIO_FB_
L
11
VDDR
VDDR
VDDR
12
MA_DATA[5
9]
VSS
MA_DQS_H[
7]
MA_DATA[5 MA_DATA[6 MA_DQS_L[ MA_DATA[5
8]
MB_DATA[5
9]
3]
7]
6]
VSS
MA_DM[7]
VSS
MB_DATA[5 MA_DATA[6 MA_DATA[5 MA_DATA[6
8]
MB_DATA[6
3]
MB_DQS_L[
7]
MB_DQS_H[
7]
2]
VSS
MB_DM[7]
VSS
7]
MB_DATA[5
1]
1]
VSS
MB_DATA[6 MB_DATA[5
0]
MB_DATA[5
6]
0]
VSS
MB_DATA[6 MB_DATA[5 MB_DATA[6 MB_DATA[5
2]
7]
1]
5]
13
14
15
16
AE
AF
AG
AH
AJ
AK
AL
Connection Diagram (Left Half)
Pins
7
AMD Confidential – Advance Information
PID:40778 Rev 1.13 – January 2009
Socket AM3 Processor Functional Data Sheet
1.2 Connection Diagram (Right Half)
17
A
B
C
D
E
F
G
19
20
21
22
]
1]
MB_DM[1]
VSS
MB_DQS_L[1
]
MB_DQS_H[
1]
MA_DATA[8
]
MA_DATA[1
3]
RSVD
VSS
MA_DM[1]
VSS
]
MB_RESET_
L
MB_CLK_H[
0]
MB_CLK_L[0
]
4]
VSS
RSVD
VSS
0]
MB_DATA[1
5]
6]
VSS
23
MB_DM[2]
MB_DATA[1
7]
MA_DQS_L[1
]
L
VSS
1]
MB_DATA[2
0]
1]
VSS
]
MA_DATA[2
4]
0]
MA_DATA[1
0]
5]
VSS
1]
MA_DATA[1
6]
MA_DATA[1 MA_DATA[9 MA_CLK_H[ MA_CLK_H[ MA_CLK_L[0 MA_DATA[1 MA_DATA[1
2]
MA_DATA[3
]
0]
2]
VSS
3]
MB_DATA[1
8]
]
1]
7]
2]
VSS
MA_DM[2]
VSS
RSVD
2]
MA_DQS_L[2
]
2]
MA_DATA[2
3]
RSVD
NP/ VSS
VOID
VOID
VDD
VSS
RSVD
VDD
VSS
VDD
VSS
VDD
VSS
VDD
MA_DM[8]
K
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
]
26
27
28
29
9]
VSS
8]
MB_DATA[2
9]
4]
5]
VSS
MA_DM[3]
MA_CHECK[
8]
VSS
8]
MA_DATA[2
9]
5]
VSS
]
MA_DQS_H[
3]
30
31
VOID
VOID
A
VSS
VOID
B
MB_DM[3]
VSS
MB_DQS_L[3
]
MB_DQS_H[
3]
MA_DATA[2 MA_DATA[1 MA_DATA[2 MA_DATA[3 MA_DATA[3 MB_DATA[3 MB_DATA[3
VSS
]
VSS
1]
MA_CLK_L[1
25
MB_DATA[1 MB_DATA[2 MB_DQS_L[2 MB_DQS_H[ MA_DQS_H[ MA_DATA[1 MA_DATA[2 MA_DATA[2 MA_DQS_L[3
MA_DQS_H[ MA_RESET_ MA_DATA[1 MA_DATA[1 MA_DATA[2
1]
24
MB_DATA[2 MB_DATA[2 MB_DATA[1 MB_DATA[2 MB_DATA[2 MB_DATA[2
J
H
MA_CHECK[
7]
9]
VSS
4]
MA_DATA[2
6]
0]
VSS
1]
MB_DATA[2
7]
0]
VSS
1]
MB_DATA[2
6]
MA_DATA[2 MA_CHECK[ MA_CHECK[ MB_CHECK[ MB_CHECK[ MB_CHECK[
7]
VSS
4]
MA_CHECK[
0]
5]
VSS
MA_CHECK[ MA_DQS_L[8 MA_DQS_H[
6]
VSS
]
MA_CHECK[
2]
MB_CHECK[ MB_CHECK[
]
VSS
8]
MB_CHECK[
6]
H
J
K
VDD
VSS
VDD
VSS
VDD
VSS
VSS
VDD
VSS
VDD
VSS
VDD
VDDIO
N
VSS
VDD
VSS
VDD
VSS
VDD
VSS
MA_ADD[14]
P
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VDDIO
MA_ADD[11]
VDDIO
MA_ADD[7]
VDDIO
MB_ADD[11]
VDDIO
MB_ADD[9]
P
R
VSS
VDD
VSS
VDD
VSS
VDD
VSS
MA_ADD[8]
MA_ADD[6]
MA_ADD[5]
MA_ADD[4]
MB_ADD[7]
MB_ADD[8]
MB_ADD[5]
MB_ADD[6]
R
T
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VDDIO
MA_ADD[3]
VDDIO
MA_ADD[1]
VDDIO
MB_ADD[3]
VDDIO
MB_ADD[4]
T
U
VSS
VDD
VSS
VDD
VSS
VDD
VSS
MB_ADD[1]
MB_ADD[2]
V
VDD
VSS
VDD
VSS
VDD
VSS
VDD
W
VSS
VDD
VSS
VDD
VSS
VDD
VSS
MA_ADD[0]
Y
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VDDIO
AA
VSS
VDD
VSS
VDD
VSS
VDD
VSS
]
]
AB
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VDDIO
MA_CAS_L
AC
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDDIO
VOID
VOID
VSS
VSS
VDD
VSS
RSVD
RSVD
RSVD
AE
AF
AG
AH
AJ
AK
AL
MA_DATA[6
0]
MA_DATA[5
3]
MA_DATA[5 MA_DATA[5 MA_CLK_L[6 MA_CLK_H[ MA_DATA[4 MA_DATA[4 MA_DATA[4
1]
MA_DATA[5
0]
4]
]
6]
VSS
MA_DM[6]
VSS
8]
MA_DATA[4
9]
3]
VSS
6]
MA_DATA[4
7]
2]
]
MA_CKE[1]
MA_ADD[15]
7]
1]
MB_DQS_L[8 MB_DQS_H[
G
VSS
MA_CLK_L[2
RSVD
VDDIO
MB_CHECK[
VSS
0]
MB_CHECK[
F
VDD
MA_CLK_H[
RSVD
1]
MB_DM[8]
5]
E
L
3]
MA_CKE[0]
8]
VSS
4]
MA_CHECK[
C
D
M
AD
Figure 2.
18
MB_DATA[9 MB_CLK_H[ MB_CLK_L[1 MB_DATA[1 MB_DATA[1 MB_DATA[1
MA_BANK[2
]
MA_ADD[2]
VDDIO
3]
MB_CKE[0]
RSVD
RSVD
L
VDDIO
MB_CKE[1]
M
MA_ADD[12] MA_ADD[9] MB_ADD[15] MB_ADD[14] MB_ADD[12]
MA_CLK_L[5 MA_CLK_H[
]
VDDIO
5]
MA_CLK_H[
4]
VDDIO
MB_EVENT
_L
5]
6]
VSS
MB_DQS_L[6
]
MB_DQS_H[
6]
RSVD
VSS
]
MB_DATA[4
9]
MB_CLK_H[
7]
MB_CLK_L[7
]
]
VSS
RSVD
VSS
7]
MB_DATA[4
2]
2]
VSS
MB_DATA[4 MB_DATA[4
3]
MB_DATA[5
3]
7]
VSS
2]
MB_DATA[4
1]
MB_DM[5]
MB_DQS_H[
5]
5]
VSS
MB_DATA[4
0]
VSS
]
MB_CLK_L[5 MB_CLK_H[
]
VDDIO
]
3]
MA_ADD[10]
VDDIO
MA0_CS_L[1
]
MA_DATA[4
0]
MA_RAS_L
VDDIO
]
MA_BANK[1
]
]
4]
VDDIO
VDDIO
5]
MB_CLK_H[
2]
MA_BANK[0 MB_BANK[0
]
]
MA_WE_L
VDDIO
MA_DATA[3
6]
VSS
MA1_CS_L[1
]
VDDIO
MA1_ODT[1] MA0_ODT[1]
MA_DATA[3
2]
VSS
]
MB_ADD[10] MB_ADD[0]
MB_RAS_L
MA_ADD[13] MA1_ODT[0] MA0_ODT[0] MB_CAS_L
VDDIO
_L
MB0_ODT[0]
VDDIO
MB_WE_L
VDDIO
MB1_CS_L[1 MB0_CS_L[1
]
MA_DATA[3
7]
]
MA_DATA[4
1]
MA_DM[5]
MB_DATA[4
4]
4]
VSS
4]
MA_DATA[3
4]
]
MB_CLK_L[3 MB_CLK_H[
]
VDDIO
MA_DATA[5 MA_DQS_H[ MA_DQS_L[6 MA_CLK_L[7 MA_CLK_H[ MA_DATA[5 MA_DATA[4 MA_DQS_H[ MA_DQS_L[5 MA_DATA[4 MA_DQS_H[ MA_DQS_L[4 MA_DATA[3 MB_DATA[3
MB_DM[6]
MB_BANK[2
MA_CLK_L[3 MA_CLK_H[ MA_CLK_L[4 MB_CLK_L[4 MB_CLK_H[ MA_EVENT MB_CLK_L[2
MA0_CS_L[0 MA1_CS_L[0
VSS
2]
VDDIO
]
3]
6]
VSS
MA_DM[4]
VSS
3]
MB_BANK[1
]
MB1_CS_L[0
]
MB0_CS_L[0
]
VSS
5]
MB_DATA[3
8]
9]
8]
VSS
MB_DM[4]
MB_DATA[5 MB_CLK_L[6 MB_CLK_H[ MB_DATA[4 MB_DATA[5 MB_DATA[4 MB_DQS_L[5 MB_DATA[4 MB_DATA[3 MB_DATA[3 MB_DATA[3 MB_DQS_H[ MB_DQS_L[4
4]
]
6]
8]
2]
6]
]
5]
5]
4]
9]
4]
]
17
18
19
20
21
22
23
24
25
26
27
28
29
U
V
W
Y
AA
AB
AC
MB1_ODT[0] A D
MB_ADD[13] A E
MB0_ODT[1] A F
MB1_ODT[1] A G
MB_DATA[3
7]
MA_DATA[4 MA_DATA[3 MA_DATA[3 MA_DATA[3 MB_DATA[3 MB_DATA[3
5]
N
3]
2]
AH
AJ
VSS
VOID
AK
VOID
VOID
AL
30
31
Connection Diagram (Right Half)
Pins
8
AMD Confidential – Advance Information
PID:40778 Rev 1.13 – January 2009
Socket AM3 Processor Functional Data Sheet
1.3 Pin Types
Table 1. Pin Types
Pin Types
I-HT-D
Input, HyperTransport™ Technology, Differential
O-HT-D
Output, HyperTransport Technology, Differential
B-IO-S
Bidirectional, VDDIO, Single-Ended
B-IO-OD Bidirectional, VDDIO, Open Drain
B-IO-D
Bidirectional, VDDIO, Differential
I-IO-S
Input, VDDIO, Single-Ended
I-IO-D
Input, VDDIO, Differential
O-IO-D
Output, VDDIO, Differential
O-IO-S
Output, VDDIO, Single-Ended
O-IO-OD Output, VDDIO, Open Drain
A
Analog
S
Supply Voltage
VREF
Voltage Reference
1.4 Pin Descriptions
Table 2. HyperTransport™ Technology Pin Descriptions
Signal Name
Type
Description
L0_CLKIN_H/L[1:0]
I-HT-D
Link 0 Clock Input
L0_CTLIN_H/L[1:0]
I-HT-D
Link 0 Control Input
L0_CADIN_H/L[15:0]
I-HT-D
Link 0 Command/Address/Data Input
L0_CLKOUT_H/L[1:0]
O-HT-D Link 0 Clock Outputs
L0_CTLOUT_H/L[1:0]
O-HT-D Link 0 Control Output
L0_CADOUT_H/L[15:0]
O-HT-D Link 0 Command/Address/Data Outputs
HTREF1
A
Compensation Resistor to VLDT
HTREF0
A
Compensation Resistor to VSS
Pins
9
AMD Confidential – Advance Information
PID:40778 Rev 1.13 – January 2009
Socket AM3 Processor Functional Data Sheet
Table 3. DDR2 SDRAM Memory Interface Pin Descriptions (Supports DDR2 and DDR3)1
Signal Name
Type
Description
MA_CLK_H/L[7:0],
MB_CLK_H/L[7:0]
O-IO-D
DRAM Differential Clock
MA0_CS_L[1:0],
MA1_CS_L[1:0],
MB0_CS_L[1:0],
MB1_CS_L[1:0]
O-IO-S
DRAM Chip Selects
MA0_ODT[1:0],
MA1_ODT[1:0],
MB0_ODT[1:0],
MB1_ODT[1:0]
O-IO-S
DRAM Enable Pin for On Die Termination
MA_CKE[1:0], MB_CKE[1:0]
O-IO-S
DRAM Clock Enable
MA_DQS_H/L[8:0],
MB_DQS_H/L[8:0]
B-IO-D
DRAM Differential Data Strobe
MA_DATA[63:0],
MB_DATA[63:0]
B-IO-S
DRAM Interface Data Bus
MA_DM[8:0], MB_DM[8:0]
O-IO-S
DRAM Data Mask Bits
MA_CHECK[7:0],
MB_CHECK[7:0]
B-IO-S
DRAM Interface ECC Check Bits
MA_RAS_L, MB_RAS_L
O-IO-S
DRAM Row Address Strobe
MA_CAS_L, MB_CAS_L
O-IO-S
DRAM Column Address Strobe
MA_WE_L, MB_WE_L
O-IO-S
DRAM Write Enable
MA_ADD[15:0],
MB_ADD[15:0]
O-IO-S
DRAM Column/Row Address
MA_BANK[2:0],
MB_BANK[2:0]
O-IO-S
DRAM Bank Address
MA_RESET_L,
MB_RESET_L
O-IO-S
DRAM Reset Pin for Suspend-to-RAM Power Management Mode
MA_EVENT_L,
MB_EVENT_L
I-IO-S
DRAM Thermal Event Status
M_VREF
VREF
DRAM Interface Voltage Reference
M_ZP
A
Compensation Resistor to VSS
M_ZN
A
Compensation Resistor to VDDIO
M_VDDIO_PWRGD
I-IO-S
Not Supported
Note:
1. Support for DDR2 or DDR3 depends on platform implementation.
Table 4. Clock Pin Descriptions
Signal Name
Type
Description
CLKIN_H/L
I-IO-D
200-MHz PLL Reference Clock
Pins
10
AMD Confidential – Advance Information
PID:40778 Rev 1.13 – January 2009
Socket AM3 Processor Functional Data Sheet
Table 5. Thermal Observation/Control Pin Descriptions
Signal Name
PROCHOT_L
Type
Description
Asserted as an input to force the processor into the HTC-active state or
B-IO-OD becomes asserted as an output to indicate when the processor has entered the
HTC-active state.
THERMDA
A
Anode (+) of the thermal diode
THERMDC
A
Cathode (–) of the thermal diode
THERMTRIP_L
SIC
SID
O-IO-OD Thermal Sensor Trip output
I-IO-S
Sideband-Temperature Sensor Interface Clock
B-IO-OD Sideband-Temperature Sensor Interface Data
ALERT_L
O-IO-S
Programmable pin that can indicate different events, including a SidebandTemperature Sensor Interface interrupt.
SA[0]
I-IO-S
Sideband interface address
Table 6. Power Supply/Voltage Regulator Interface Pin Descriptions
Signal Name
PSI_L
Type
Notes Description
O-IO-S
Power Status Indicator for the VDD Power Supply regulator. This
signal may be used by the regulator to improve efficiency when the
processor is in low power states.
VDD_FB_H/L
A
Differential feedback for VDD power supply
VDDNB_FB_H/L
A
Differential feedback for VDDNB power supply
VDDIO_FB_H/L
A
Differential feedback for VDDIO power supply
VDDA
S
Filtered PLL supply voltage
VDD
S
Core power supply
VDDNB
S
Northbridge power supply
VDDIO
S
DDR SDRAM I/O ring power supply
VLDT_A, VLDT_B
S
HyperTransport™ I/O ring power supply
VDDR
S
VDDR power supply
VDDR_SENSE
A
VDDR voltage monitor pin
VSS
S
Ground
PVIEN/VID[1]
B-IO-OD 1
Prior to PWROK assertion, PVIEN/VID[1] signals to the processor
whether the platform supports PVI or SVI operation. After PWROK
assertion, on a platform that implements the parallel VID interface, this
pin is bit 1 of the VID interface. This pin is not used after PWROK
assertion on platforms that implement the serial VID interface.
SVD/VID[2]
B-IO-OD 1
In platforms supporting SVI, this signal is the serial VID interface data.
In platforms supporting PVI, this signal is bit 2 of the parallel voltage
ID to the regulator.
SVC/VID[3]
O-IO-S
1
In platforms supporting SVI, this signal is the serial VID interface
clock. In platforms supporting PVI, this signal is bit 3 of the parallel
voltage ID to the regulator.
VID[5:4], VID[0]
O-IO-S
1
Voltage ID pins to the regulator
Note:
1. The function of this pin is platform implementation dependant. For information on how to connect this pin, please
refer to the appropriate motherboard design guide.
Pins
11
AMD Confidential – Advance Information
PID:40778 Rev 1.13 – January 2009
Socket AM3 Processor Functional Data Sheet
Table 7. JTAG Pin Descriptions
Signal Name
Type
Description
TCK
I-IO-S
JTAG Clock
TMS
I-IO-S
JTAG Mode Select
TRST_L
I-IO-S
JTAG Reset
TDI
I-IO-S
JTAG Data Input
TDO
O-IO-S
JTAG Data Output
Table 8. Debug Pin Descriptions
Signal Name
Type
Description
DBREQ_L
I-IO-S
Debug Request
DBRDY
O-IO-S
Debug Ready
Table 9. Miscellaneous Pin Descriptions
Signal Name
Type
Description
CPU_PRESENT_L
O-IO-S
Indicates a processor is present for a socket. Shorted to VSS on the package.
RESET_L
I-IO-S
Processor Reset
PWROK
I-IO-S
Indicates that voltages and input CLKIN have reached specified operation.
LDTSTOP_L
I-IO-S
HyperTransport™ Technology Stop Control Input. Used for power
management and for changing HyperTransport link width and frequency.
O-IO-S
Indicates that the processor is capable of split Northbridge and core voltage
plane operation. If open, the processor requires a unified core and Northbridge
voltage plane. If shorted to VSS, split core and Northbridge voltage plan
operation is supported.
CORE_TYPE
VOID
Missing pins on package and socket used for mechanical keying.
RSVD
Reserved pins that should remain unconnected.
NP/VSS
Pin is not populated on the package but socket hole connects to ground.
NP/RSVD
Pin is not populated on the package but socket contains a hole that should remain
unconnected.
TEST*
Refer to Socket AM3 Motherboard Design Guide, order #40837
Pins
12
AMD Confidential – Advance Information
PID:40778 Rev 1.13 – January 2009
Socket AM3 Processor Functional Data Sheet
1.5 Alphabetical Pin List
Name
ALERT _L
CLKIN_H
CLKIN_L
CORE_T YPE
CPU_PRESENT _L
DBRDY
DBREQ_L
HT REF0
HT REF1
L0_CADIN_H[0]
L0_CADIN_H[1]
L0_CADIN_H[10]
L0_CADIN_H[11]
L0_CADIN_H[12]
L0_CADIN_H[13]
L0_CADIN_H[14]
L0_CADIN_H[15]
L0_CADIN_H[2]
L0_CADIN_H[3]
L0_CADIN_H[4]
L0_CADIN_H[5]
L0_CADIN_H[6]
L0_CADIN_H[7]
L0_CADIN_H[8]
L0_CADIN_H[9]
L0_CADIN_L[0]
L0_CADIN_L[1]
L0_CADIN_L[10]
L0_CADIN_L[11]
L0_CADIN_L[12]
L0_CADIN_L[13]
L0_CADIN_L[14]
L0_CADIN_L[15]
L0_CADIN_L[2]
L0_CADIN_L[3]
L0_CADIN_L[4]
L0_CADIN_L[5]
L0_CADIN_L[6]
L0_CADIN_L[7]
L0_CADIN_L[8]
L0_CADIN_L[9]
L0_CADOUT _H[0]
L0_CADOUT _H[1]
L0_CADOUT _H[10]
L0_CADOUT _H[11]
L0_CADOUT _H[12]
L0_CADOUT _H[13]
L0_CADOUT _H[14]
L0_CADOUT _H[15]
L0_CADOUT _H[2]
Pin
AL4
A8
B8
G5
AL3
B6
A5
V7
V8
J3
J1
L6
M4
P4
R6
T4
U6
L3
L1
N1
R3
R1
U3
J6
K4
J2
K1
M6
M5
P5
T6
T5
V6
L2
M1
P1
R2
T1
U2
K6
K5
AH1
AG2
AF5
AF6
AD6
AB5
AB6
Y5
AF1
Name
L0_CADOUT _H[3]
L0_CADOUT _H[4]
L0_CADOUT _H[5]
L0_CADOUT _H[6]
L0_CADOUT _H[7]
L0_CADOUT _H[8]
L0_CADOUT _H[9]
L0_CADOUT _L[0]
L0_CADOUT _L[1]
L0_CADOUT _L[10]
L0_CADOUT _L[11]
L0_CADOUT _L[12]
L0_CADOUT _L[13]
L0_CADOUT _L[14]
L0_CADOUT _L[15]
L0_CADOUT _L[2]
L0_CADOUT _L[3]
L0_CADOUT _L[4]
L0_CADOUT _L[5]
L0_CADOUT _L[6]
L0_CADOUT _L[7]
L0_CADOUT _L[8]
L0_CADOUT _L[9]
L0_CLKIN_H[0]
L0_CLKIN_H[1]
L0_CLKIN_L[0]
L0_CLKIN_L[1]
L0_CLKOUT _H[0]
L0_CLKOUT _H[1]
L0_CLKOUT _L[0]
L0_CLKOUT _L[1]
L0_CT LIN_H[0]
L0_CT LIN_H[1]
L0_CT LIN_L[0]
L0_CT LIN_L[1]
L0_CT LOUT _H[0]
L0_CT LOUT _H[1]
L0_CT LOUT _L[0]
L0_CT LOUT _L[1]
LDT ST OP_L
M_VDDIO_PWRGD
M_VREF
M_ZN
M_ZP
MA_ADD[0]
MA_ADD[1]
MA_ADD[10]
MA_ADD[11]
MA_ADD[12]
MA_ADD[13]
Pin
AE2
AC2
AB1
AA2
Y1
AH5
AH6
AG1
AG3
AF4
AE6
AC6
AB4
AA6
Y4
AE1
AE3
AC3
AA1
AA3
W1
AH4
AG6
N3
N6
N2
P6
AD1
AD5
AC1
AD4
U1
V4
V1
V5
W2
Y6
W3
W6
D8
F3
F12
AH11
AJ11
W24
T 27
Y25
P25
N26
AC26
Name
MA_ADD[14]
MA_ADD[15]
MA_ADD[2]
MA_ADD[3]
MA_ADD[4]
MA_ADD[5]
MA_ADD[6]
MA_ADD[7]
MA_ADD[8]
MA_ADD[9]
MA_BANK[0]
MA_BANK[1]
MA_BANK[2]
MA_CAS_L
MA_CHECK[0]
MA_CHECK[1]
MA_CHECK[2]
MA_CHECK[3]
MA_CHECK[4]
MA_CHECK[5]
MA_CHECK[6]
MA_CHECK[7]
MA_CKE[0]
MA_CKE[1]
MA_CLK_H[0]
MA_CLK_H[1]
MA_CLK_H[2]
MA_CLK_H[3]
MA_CLK_H[4]
MA_CLK_H[5]
MA_CLK_H[6]
MA_CLK_H[7]
MA_CLK_L[0]
MA_CLK_L[1]
MA_CLK_L[2]
MA_CLK_L[3]
MA_CLK_L[4]
MA_CLK_L[5]
MA_CLK_L[6]
MA_CLK_L[7]
MA_DAT A[0]
MA_DAT A[1]
MA_DAT A[10]
MA_DAT A[11]
MA_DAT A[12]
MA_DAT A[13]
MA_DAT A[14]
MA_DAT A[15]
MA_DAT A[16]
MA_DAT A[17]
Pins
Pin
N24
M27
U25
T 25
R27
R26
R25
P27
R24
N27
AA27
Y27
N25
AB25
H27
H29
K27
L24
G27
G28
J26
K25
M25
L27
G20
G19
U24
W26
V27
U27
AE20
AG21
G21
H19
V24
W25
W27
U26
AE19
AG20
G14
E14
F21
G22
G17
F17
E21
E22
F23
G23
Name
MA_DAT A[18]
MA_DAT A[19]
MA_DAT A[2]
MA_DAT A[20]
MA_DAT A[21]
MA_DAT A[22]
MA_DAT A[23]
MA_DAT A[24]
MA_DAT A[25]
MA_DAT A[26]
MA_DAT A[27]
MA_DAT A[28]
MA_DAT A[29]
MA_DAT A[3]
MA_DAT A[30]
MA_DAT A[31]
MA_DAT A[32]
MA_DAT A[33]
MA_DAT A[34]
MA_DAT A[35]
MA_DAT A[36]
MA_DAT A[37]
MA_DAT A[38]
MA_DAT A[39]
MA_DAT A[4]
MA_DAT A[40]
MA_DAT A[41]
MA_DAT A[42]
MA_DAT A[43]
MA_DAT A[44]
MA_DAT A[45]
MA_DAT A[46]
MA_DAT A[47]
MA_DAT A[48]
MA_DAT A[49]
MA_DAT A[5]
MA_DAT A[50]
MA_DAT A[51]
MA_DAT A[52]
MA_DAT A[53]
MA_DAT A[54]
MA_DAT A[55]
MA_DAT A[56]
MA_DAT A[57]
MA_DAT A[58]
MA_DAT A[59]
MA_DAT A[6]
MA_DAT A[60]
MA_DAT A[61]
MA_DAT A[62]
Pin
C26
E26
E16
D23
E23
E25
F25
E27
C28
F27
G26
C27
D27
H17
E28
E29
AF27
AG29
AH27
AJ27
AE26
AF29
AJ29
AJ28
H13
AF25
AH25
AG23
AE22
AG26
AJ26
AE23
AF23
AE21
AF21
G13
AF17
AE17
AG22
AD21
AE18
AG17
AE16
AG15
AE13
AD13
E15
AD17
AG16
AG14
13
AMD Confidential – Advance Information
PID:40778 Rev 1.13 – January 2009
Name
MA_DAT A[63]
MA_DAT A[7]
MA_DAT A[8]
MA_DAT A[9]
MA_DM[0]
MA_DM[1]
MA_DM[2]
MA_DM[3]
MA_DM[4]
MA_DM[5]
MA_DM[6]
MA_DM[7]
MA_DM[8]
MA_DQS_H[0]
MA_DQS_H[1]
MA_DQS_H[2]
MA_DQS_H[3]
MA_DQS_H[4]
MA_DQS_H[5]
MA_DQS_H[6]
MA_DQS_H[7]
MA_DQS_H[8]
MA_DQS_L[0]
MA_DQS_L[1]
MA_DQS_L[2]
MA_DQS_L[3]
MA_DQS_L[4]
MA_DQS_L[5]
MA_DQS_L[6]
MA_DQS_L[7]
MA_DQS_L[8]
MA_EVENT _L
MA_RAS_L
MA_RESET _L
MA_WE_L
MA0_CS_L[0]
MA0_CS_L[1]
MA0_ODT [0]
MA0_ODT [1]
MA1_CS_L[0]
MA1_CS_L[1]
MA1_ODT [0]
MA1_ODT [1]
MB_ADD[0]
MB_ADD[1]
MB_ADD[10]
MB_ADD[11]
MB_ADD[12]
MB_ADD[13]
MB_ADD[14]
Pin
AE14
G16
E17
G18
H15
E18
E24
B29
AH29
AJ25
AF19
AF15
J25
F15
E19
C25
D29
AG27
AG24
AG18
AD15
J28
G15
F19
D25
C29
AG28
AG25
AG19
AE15
J27
W30
AA26
E20
AB27
AA24
AC25
AC28
AE28
AA25
AD27
AC27
AE27
AA30
U28
AA29
P29
N30
AE31
N29
Name
MB_ADD[15]
MB_ADD[2]
MB_ADD[3]
MB_ADD[4]
MB_ADD[5]
MB_ADD[6]
MB_ADD[7]
MB_ADD[8]
MB_ADD[9]
MB_BANK[0]
MB_BANK[1]
MB_BANK[2]
MB_CAS_L
MB_CHECK[0]
MB_CHECK[1]
MB_CHECK[2]
MB_CHECK[3]
MB_CHECK[4]
MB_CHECK[5]
MB_CHECK[6]
MB_CHECK[7]
MB_CKE[0]
MB_CKE[1]
MB_CLK_H[0]
MB_CLK_H[1]
MB_CLK_H[2]
MB_CLK_H[3]
MB_CLK_H[4]
MB_CLK_H[5]
MB_CLK_H[6]
MB_CLK_H[7]
MB_CLK_L[0]
MB_CLK_L[1]
MB_CLK_L[2]
MB_CLK_L[3]
MB_CLK_L[4]
MB_CLK_L[5]
MB_CLK_L[6]
MB_CLK_L[7]
MB_DAT A[0]
MB_DAT A[1]
MB_DAT A[10]
MB_DAT A[11]
MB_DAT A[12]
MB_DAT A[13]
MB_DAT A[14]
MB_DAT A[15]
MB_DAT A[16]
MB_DAT A[17]
MB_DAT A[18]
Socket AM3 Processor Functional Data Sheet
Pin
N28
U29
T 29
T 31
R30
R31
R28
R29
P31
AA28
AA31
N31
AC29
G31
H31
L28
L29
G29
G30
K31
K29
M29
M31
C19
A18
V31
Y31
W29
U31
AL19
AJ19
D19
A19
W31
Y30
W28
U30
AL18
AK19
D13
A13
A21
C21
D15
C16
A20
B21
A22
B23
B25
Name
MB_DAT A[19]
MB_DAT A[2]
MB_DAT A[20]
MB_DAT A[21]
MB_DAT A[22]
MB_DAT A[23]
MB_DAT A[24]
MB_DAT A[25]
MB_DAT A[26]
MB_DAT A[27]
MB_DAT A[28]
MB_DAT A[29]
MB_DAT A[3]
MB_DAT A[30]
MB_DAT A[31]
MB_DAT A[32]
MB_DAT A[33]
MB_DAT A[34]
MB_DAT A[35]
MB_DAT A[36]
MB_DAT A[37]
MB_DAT A[38]
MB_DAT A[39]
MB_DAT A[4]
MB_DAT A[40]
MB_DAT A[41]
MB_DAT A[42]
MB_DAT A[43]
MB_DAT A[44]
MB_DAT A[45]
MB_DAT A[46]
MB_DAT A[47]
MB_DAT A[48]
MB_DAT A[49]
MB_DAT A[5]
MB_DAT A[50]
MB_DAT A[51]
MB_DAT A[52]
MB_DAT A[53]
MB_DAT A[54]
MB_DAT A[55]
MB_DAT A[56]
MB_DAT A[57]
MB_DAT A[58]
MB_DAT A[59]
MB_DAT A[6]
MB_DAT A[60]
MB_DAT A[61]
MB_DAT A[62]
MB_DAT A[63]
Pins
Pin
A26
A15
D21
C22
A24
A25
A28
A29
F31
F29
A27
B27
C15
E30
E31
AJ31
AJ30
AL26
AL25
AG30
AH31
AK27
AL27
F13
AJ24
AH23
AH21
AJ21
AK25
AL24
AL22
AJ22
AL20
AH19
E13
AJ16
AH15
AL21
AK21
AL17
AL16
AK15
AL14
AG13
AF13
A14
AJ15
AL15
AL13
AH13
Name
MB_DAT A[7]
MB_DAT A[8]
MB_DAT A[9]
MB_DM[0]
MB_DM[1]
MB_DM[2]
MB_DM[3]
MB_DM[4]
MB_DM[5]
MB_DM[6]
MB_DM[7]
MB_DM[8]
MB_DQS_H[0]
MB_DQS_H[1]
MB_DQS_H[2]
MB_DQS_H[3]
MB_DQS_H[4]
MB_DQS_H[5]
MB_DQS_H[6]
MB_DQS_H[7]
MB_DQS_H[8]
MB_DQS_L[0]
MB_DQS_L[1]
MB_DQS_L[2]
MB_DQS_L[3]
MB_DQS_L[4]
MB_DQS_L[5]
MB_DQS_L[6]
MB_DQS_L[7]
MB_DQS_L[8]
MB_EVENT _L
MB_RAS_L
MB_RESET _L
MB_WE_L
MB0_CS_L[0]
MB0_CS_L[1]
MB0_ODT [0]
MB0_ODT [1]
MB1_CS_L[0]
MB1_CS_L[1]
MB1_ODT [0]
MB1_ODT [1]
NP/RSVD
NP/VSS
NP/VSS
PROCHOT _L
PSI_L
PVIEN/VID[1]
PWROK
RESET _L
Pin
B15
A16
A17
B13
B17
A23
C30
AK29
AJ23
AH17
AJ14
J29
C14
D17
C24
D31
AL28
AK23
AK17
AK13
J31
C13
C17
C23
C31
AL29
AL23
AJ17
AJ13
J30
V29
AB29
B19
AC30
AC31
AE30
AD29
AF31
AB31
AE29
AD31
AG31
B2
AE7
H20
AL7
F1
E2
C9
C7
14
AMD Confidential – Advance Information
PID:40778 Rev 1.13 – January 2009
Name
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
SA[0]
SIC
SID
SVC/VID[3]
SVD/VID[2]
T CK
T DI
T DO
T EST 10
T EST 12
T EST 13
T EST 14
T EST 15
T EST 16
T EST 17
T EST 18
T EST 19
T EST 2
T EST 20
T EST 21
T EST 22
T EST 23
T EST 24
T EST 25_H
T EST 25_L
T EST 26
T EST 27
T EST 28_H
T EST 28_L
T EST 29_H
T EST 29_L
T EST 3
T EST 6
T EST 7
Pin
AD25
AE24
AE25
AJ18
AJ20
AK3
C18
C20
F2
G24
G25
H25
L25
L26
L30
L31
AK4
AL6
AK6
C1
E3
AH10
AL10
AK10
G7
AH9
AJ7
C5
F8
E7
D6
E9
F10
AJ6
AJ8
AL8
AJ9
AH8
AK8
A10
B10
AK5
AK9
J10
H9
C11
D11
AH7
AJ5
E5
Name
T EST 8
T EST 9
T HERMDA
T HERMDC
T HERMT RIP_L
T MS
T RST _L
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
Socket AM3 Processor Functional Data Sheet
Pin
D4
F6
AG8
AG9
AK7
AL9
AJ10
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA8
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB7
AB9
AC10
AC12
AC14
AC16
AC18
AC20
AC22
AC4
AC5
AC8
AD11
AD2
AD23
AD3
AD7
AD9
AE10
AE12
AF11
AF7
AF9
AG4
AG5
AG7
AH2
AH3
Name
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
Pins
Pin
B3
C2
C4
D3
D5
E4
E6
F5
F7
G6
G8
H11
H23
H7
J12
J14
J16
J18
J20
J22
J24
J8
K11
K13
K15
K17
K19
K21
K23
K7
K9
L10
L12
L14
L16
L18
L20
L22
L4
L5
L8
M11
M13
M15
M17
M19
M2
M21
M23
M3
Name
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
Pin
M7
M9
N10
N12
N14
N16
N18
N20
N22
N8
P11
P13
P15
P17
P19
P21
P23
P7
P9
R10
R12
R14
R16
R18
R20
R22
R4
R5
R8
T 11
T 13
T 15
T 17
T 19
T2
T 21
T 23
T3
T7
T9
U10
U12
U14
U16
U18
U20
U22
U8
V11
V13
15
AMD Confidential – Advance Information
PID:40778 Rev 1.13 – January 2009
Name
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD_FB_H
VDD_FB_L
VDDA
VDDA
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
Pin
V15
V17
V19
V21
V23
V9
W10
W12
W14
W16
W18
W20
W22
W4
W5
W8
Y11
Y13
Y15
Y17
Y19
Y2
Y21
Y23
Y3
Y7
Y9
G2
G1
C10
D10
AB24
AB26
AB28
AB30
AC24
AD26
AD28
AD30
AF30
M24
M26
M28
M30
P24
P26
P28
P30
T 24
T 26
Name
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO_FB_H
VDDIO_FB_L
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB_FB_H
VDDNB_FB_L
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR_SENSE
VID[0]
VID[4]
VID[5]
VLDT _A
VLDT _A
VLDT _A
VLDT _A
VLDT _B
VLDT _B
VLDT _B
VLDT _B
VOID
Socket AM3 Processor Functional Data Sheet
Pin
T 28
T 30
V25
V26
V28
V30
Y24
Y26
Y28
Y29
AK11
AL11
A4
A6
B5
B7
C6
C8
D7
D9
E10
E8
F11
F9
G10
G12
G4
G3
A12
AG12
AH12
AJ12
AK12
AL12
B12
C12
D12
E12
E1
D1
D2
AJ1
AJ2
AJ3
AJ4
H1
H2
H5
H6
A1
Name
VOID
VOID
VOID
VOID
VOID
VOID
VOID
VOID
VOID
VOID
VOID
VOID
VOID
VOID
VOID
VOID
VOID
VOID
VOID
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Pins
Pin
A2
A30
A31
AD18
AD19
AE8
AE9
AK1
AK31
AL1
AL2
AL30
AL31
B1
B31
H21
H22
H3
H4
A11
A3
A7
A9
AA11
AA13
AA15
AA17
AA19
AA21
AA23
AA4
AA5
AA7
AA9
AB10
AB12
AB14
AB16
AB18
AB2
AB20
AB22
AB3
AB8
AC11
AC13
AC15
AC17
AC19
AC21
Name
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Pin
AC23
AC7
AC9
AD10
AD12
AD14
AD16
AD20
AD22
AD24
AD8
AE11
AE4
AE5
AF10
AF12
AF14
AF16
AF18
AF2
AF20
AF22
AF24
AF26
AF28
AF3
AF8
AG10
AG11
AH14
AH16
AH18
AH20
AH22
AH24
AH26
AH28
AH30
AK14
AK16
AK18
AK2
AK20
AK22
AK24
AK26
AK28
AK30
AL5
B11
16
AMD Confidential – Advance Information
PID:40778 Rev 1.13 – January 2009
Name
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Pin
B14
B16
B18
B20
B22
B24
B26
B28
B30
B4
B9
C3
D14
D16
D18
D20
D22
D24
D26
D28
D30
E11
F14
F16
F18
F20
F22
F24
F26
F28
F30
F4
G11
G9
H10
H12
H14
H16
H18
H24
H26
Name
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Socket AM3 Processor Functional Data Sheet
Pin
H28
H30
H8
J11
J13
J15
J17
J19
J21
J23
J4
J5
J7
J9
K10
K12
K14
K16
K18
K2
K20
K22
K24
K26
K28
K3
K30
K8
L11
L13
L15
L17
L19
L21
L23
L7
L9
M10
M12
M14
M16
Name
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Pins
Pin
M18
M20
M22
M8
N11
N13
N15
N17
N19
N21
N23
N4
N5
N7
N9
P10
P12
P14
P16
P18
P2
P20
P22
P3
P8
R11
R13
R15
R17
R19
R21
R23
R7
R9
T 10
T 12
T 14
T 16
T 18
T 20
T 22
Name
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Pin
T8
U11
U13
U15
U17
U19
U21
U23
U4
U5
U7
U9
V10
V12
V14
V16
V18
V2
V20
V22
V3
W11
W13
W15
W17
W19
W21
W23
W7
W9
Y10
Y12
Y14
Y16
Y18
Y20
Y22
Y8
17
AMD Confidential – Advance Information
PID:40778 Rev 1.13 – January 2009
Socket AM3 Processor Functional Data Sheet
1.6 Color-Coded Connection Diagram (Left Half)
1
2
4
5
6
A
VOID
VOID
VSS
VDDNB
DBREQ_L
VDDNB
VSS
CLKIN_H
VSS
TEST 25_H
VSS
VDDR
B
VOID
NP/ RSVD
VDD
VSS
VDDNB
DBRDY
VDDNB
CLKIN_L
VSS
TEST25_L
VSS
VDDR
7
8
9
10
11
12
C
SVC/ VID[3]
VDD
VSS
VDD
T EST 14
VDDNB
RESET _L
VDDNB
PWROK
VDDA
T EST 29_H
VDDR
D
VID[4]
VID[5]
VDD
T EST 8
VDD
TEST17
VDDNB
LDTST OP_L
VDDNB
VDDA
T EST 29_L
VDDR
E
VID[0]
SVD/ VID[2]
VDD
TEST7
VDD
T EST 16
VDDNB
T EST18
VDDNB
VSS
PVIEN/ VID[
1]
F
PSI_L
RSVD
G
VDD_FB_L
VDD_FB_H
H
VLDT_B
VLDT _B
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
M_VDDIO_P
WRGD
H[1]
L0_CADIN_L
[1]
H[3]
L
H
E
VOID
VLDT _B
VSS
VSS
[0]
H[0]
VSS
VSS
[3]
[2]
H[2]
VDD
VDD
L0_CADIN_ L0_CLKIN_L L0_CLKIN_H
H[4]
L0_CADIN_L
[4]
[0]
VSS
[0]
VSS
L0_CADIN_ L0_CADIN_L L0_CADIN_
H[6]
L0_CADIN_L
[6]
[5]
H[5]
VDD
VDD
L0_CT LIN_H L0_CADIN_L L0_CADIN_
[0]
L0_CT LIN_L
[0]
[7]
H[7]
VSS
VSS
L0_CADOUT L0_CTLOUT L0_CT LOUT
_L[7]
L0_CADOUT
_H[7]
_H[0]
_L[0]
VDD
VDD
L0_CADOUT L0_CADOUT L0_CADOUT
_L[5]
L0_CADOUT
_H[5]
_H[6]
_L[6]
VSS
VSS
L0_CLKOUT L0_CADOUT L0_CADOUT
_L[0]
L0_CLKOUT
_H[0]
_H[4]
VDD
_L[4]
VDD
L0_CADOUT L0_CADOUT L0_CADOUT
_L[2]
L0_CADOUT
_H[2]
_H[3]
_L[3]
VSS
VSS
L0_CADOUT L0_CADOUT L0_CADOUT
_L[0]
L0_CADOUT
_H[0]
VLDT_A
_H[1]
_L[1]
VDD
VDD
VLDT _A
VLDT _A
VOID
VSS
AL
VOID
VOID
1
2
VDD
VOID
L0_CADIN_ L0_CADIN_L L0_CADIN_
L0_CADIN_L
VSS
VDDNB_FB_ VDDNB_FB_ CORE_T YP
L0_CADIN_ L0_CADIN_L L0_CADIN_
AK
Figure 3.
3
RSVD
CPU_PRES
ENT _L
3
H[9]
VDD
[9]
VDD
VDD
T EST 15
VDDNB
T EST 19
VDDNB
M_VREF
T EST 10
VDD
VSS
VDDNB
VSS
VDDNB
VLDT_B
VDD
VSS
T EST 28_L
VSS
VDD
VSS
VSS
VDD
VSS
TEST 28_H
VSS
VDD
VDD
VSS
VDD
VSS
VDD
VSS
H[8]
[8]
L0_CADIN_
H[10]
L0_CADIN_ L0_CADIN_L L0_CADIN_L
H[11]
[11]
VSS
VSS
[10]
L0_CLKIN_H
[1]
L0_CADIN_ L0_CADIN_L L0_CLKIN_L
H[12]
[12]
VDD
VDD
[1]
L0_CADIN_
H[13]
L0_CADIN_ L0_CADIN_L L0_CADIN_L
H[14]
[14]
VSS
VSS
[13]
L0_CADIN_
H[15]
L0_CT LIN_H L0_CTLIN_L L0_CADIN_L
[1]
VDD
[1]
VDD
[15]
L0_CT LOUT
_L[1]
L0_CADOUT L0_CADOUT L0_CT LOUT
_L[15]
_H[15]
VSS
VSS
_H[1]
L0_CADOUT
_L[14]
L0_CADOUT L0_CADOUT L0_CADOUT
_L[13]
_H[13]
VDD
VDD
_H[14]
L0_CADOUT
_L[12]
L0_CLKOUT L0_CLKOUT L0_CADOUT
_L[1]
_H[1]
VSS
VSS
_H[12]
L0_CADOUT
_L[11]
L0_CADOUT L0_CADOUT L0_CADOUT
_L[10]
VDD
_H[10]
VDD
_H[11]
L0_CADOUT
_L[9]
L0_CADOUT L0_CADOUT L0_CADOUT
_L[8]
_H[8]
_H[9]
VLDT_A
TEST6
T EST 2
SA[0]
T EST 26
SID
ALERT _L
VSS
SIC
4
5
E
VDD
L0_CADIN_ L0_CADIN_L L0_CADIN_L
6
14
15
16
]
]
MB_DM[0]
VSS
]
MB_DATA[7
]
]
VSS
MB_DQS_L[ MB_DQS_H[ MB_DATA[3 MB_DAT A[1
0]
MB_DAT A[0
]
0]
VSS
]
MB_DATA[1
2]
3]
VSS
VDDR_SENS MB_DAT A[5 MA_DAT A[1 MA_DATA[6 MA_DAT A[2
T EST 9
L0_CADIN_
13
MB_DAT A[1 MB_DAT A[6 MB_DATA[2 MB_DAT A[8
]
MB_DAT A[4
]
]
VSS
]
MA_DQS_H[
0]
]
VSS
MA_DAT A[5 MA_DAT A[0 MA_DQS_L[ MA_DAT A[7
]
A
B
C
D
E
F
G
]
0]
]
VSS
MA_DM[0]
VSS
H
VSS
VDD
VSS
VDD
J
VDD
VSS
VDD
VSS
K
MA_DAT A[4
]
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
L
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
M
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
N
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
P
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
R
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
T
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
U
HTREF0
HT REF1
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
V
W
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
Y
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
AA
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
AB
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
AC
VDD
VSS
VDD
VSS
VDD
VSS
NP/ VSS
VOID
VOID
VDD
VSS
VDD
VDD
VSS
VDD
VSS
VDD
VSS
VDD
THERMDA
T HERMDC
VSS
VSS
VDDR
T EST 3
T EST 23
T EST12
T CK
M_ZN
VDDR
T EST 13
T EST 20
T EST22
T RST _L
M_ZP
VDDR
T HERMT RI
P_L
PROCHOT _
L
7
T EST 24
T EST27
T DO
T EST 21
TMS
T DI
8
9
10
VDDIO_FB_
H
VDDIO_FB_
L
11
VDDR
VDDR
12
MA_DAT A[5
9]
VSS
MA_DQS_H[
7]
VSS
MA_DAT A[5 MA_DAT A[6 MA_DQS_L[ MA_DAT A[5
8]
MB_DAT A[5
9]
3]
7]
6]
VSS
MA_DM[7]
VSS
MB_DAT A[5 MA_DAT A[6 MA_DATA[5 MA_DAT A[6
8]
MB_DAT A[6
3]
MB_DQS_L[
7]
MB_DQS_H[
7]
2]
VSS
MB_DM[7]
VSS
7]
MB_DATA[5
1]
1]
VSS
MB_DATA[6 MB_DAT A[5
0]
MB_DATA[5
6]
0]
VSS
MB_DAT A[6 MB_DAT A[5 MB_DATA[6 MB_DAT A[5
2]
7]
1]
5]
13
14
15
16
AD
AE
AF
AG
AH
AJ
AK
AL
Color-Coded Connection Diagram (Left Half)
Pins
18
AMD Confidential – Advance Information
PID:40778 Rev 1.13 – January 2009
Socket AM3 Processor Functional Data Sheet
1.7 Color-Coded Connection Diagram (Right Half)
17
A
B
C
D
E
F
G
H
19
20
21
22
]
1]
MB_DM[1]
VSS
MB_DQS_L[
1]
MB_DQS_H[
1]
MA_DATA[8
]
MA_DATA[1
3]
RSVD
VSS
MA_DM[1]
VSS
1]
MB_RESET
_L
MB_CLK_H[
0]
MB_CLK_L[
0]
4]
VSS
RSVD
VSS
0]
MB_DATA[1
5]
6]
VSS
23
MB_DM[2]
MB_DATA[1
7]
1]
1]
_L
VSS
1]
MB_DATA[2
0]
1]
VSS
2]
MA_DATA[2
0]
4]
MA_DATA[1
0]
5]
VSS
1]
MA_DATA[1
6]
MA_DATA[1 MA_DAT A[9 MA_CLK_H[ MA_CLK_H[ MA_CLK_L[ MA_DAT A[1 MA_DATA[1
2]
MA_DATA[3
]
]
VSS
1]
MA_CLK_L[
1]
25
26
2]
VSS
2]
VSS
MA_DM[2]
VSS
3]
MB_DATA[1
8]
2]
MA_DQS_L[
2]
2]
MA_DATA[2
3]
RSVD
0]
0]
1]
7]
NP/ VSS
VOID
VOID
VDD
VSS
RSVD
MA_DM[8]
VDD
VSS
VDD
VSS
VDD
VSS
VDD
K
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
L
VSS
VDD
VSS
VDD
VSS
VDD
VSS
M
VDD
VSS
VDD
VSS
VDD
VSS
VDD
N
VSS
VDD
VSS
VDD
VSS
VDD
VSS
P
VDD
VSS
VDD
VSS
VDD
VSS
VDD
R
VSS
VDD
VSS
VDD
VSS
VDD
VSS
T
VDD
VSS
VDD
VSS
VDD
VSS
VDD
U
VSS
VDD
VSS
VDD
VSS
VDD
VSS
V
VDD
VSS
VDD
VSS
VDD
VSS
VDD
9]
VSS
MA_CHECK
[3]
VDDIO
8]
VSS
MA_CHECK
[7]
9]
VSS
7]
VSS
[6]
VSS
RSVD
RSVD
MA_CKE[0]
VDDIO
MA_ADD[14 MA_BANK[2 MA_ADD[12
]
VDDIO
MA_CLK_H[
2]
MA_CLK_L[
2]
MA_ADD[3]
MA_ADD[2]
VDDIO
VDDIO
5]
VDDIO
VSS
VDD
VSS
MA_ADD[0]
VSS
VDD
VDDIO
AA
VSS
VDD
VSS
VDD
VSS
VDD
VSS
]
]
AB
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VDDIO
MA_CAS_L
AC
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDDIO
]
]
VOID
VOID
VSS
VSS
VDD
VSS
RSVD
VDDIO
RSVD
RSVD
AG
AH
AJ
AK
AL
6]
6]
MA_DM[6]
VSS
8]
MA_DATA[4
9]
3]
VSS
6]
MA_DATA[4
7]
3]
3]
6]
0]
VSS
1]
MB_DAT A[2
7]
0]
VSS
1]
MB_DAT A[2
6]
[4]
MA_CHECK
[0]
[5]
VSS
8]
MA_CHECK
[2]
MA_CKE[1]
MA_ADD[15
]
MA_ADD[9]
8]
VSS
[4]
MA_CHECK
[1]
MB_DM[8]
MB_CHECK
[7]
MB_CHECK MB_CHECK
[2]
[3]
VDDIO
MB_CKE[0]
[5]
VSS
[0]
MB_CHECK
[1]
MB_DQS_L[ MB_DQS_H[
8]
VSS
8]
MB_CHECK
[6]
3]
MA_ADD[10
]
MA0_CS_L[0 MA1_CS_L[0
VSS
MA_ADD[7]
MA_ADD[1]
5]
MA_CLK_H[
4]
VDDIO
VDDIO
]
5]
6]
VSS
MB_DQS_L[
6]
MB_DQS_H[
6]
RSVD
VSS
6]
MB_DATA[4
9]
MB_CLK_H[
7]
MB_CLK_L[
7]
7]
VSS
RSVD
VSS
7]
MB_DATA[4
2]
2]
VSS
MB_DATA[4 MB_DAT A[4
3]
MB_DATA[5
3]
7]
VSS
2]
MB_DATA[4
1]
MB_DM[5]
MB_DQS_H[
5]
F
G
H
J
K
RSVD
L
MB_CKE[1]
M
MB_ADD[11
]
MB_ADD[3]
MB_ADD[1] MB_ADD[2]
VDDIO
MB_EVENT
_L
VDDIO
MB_ADD[4]
MB_CLK_L[ MB_CLK_H[
5]
VDDIO
5]
MB_CLK_H[
2]
3]
VDDIO
MA_RAS_L
VDDIO
4]
MA_BANK[1
]
4]
4]
VDDIO
VDDIO
MA_BANK[0 MB_BANK[0 MB_ADD[10
0]
3]
MB_ADD[0]
]
]
]
MA_WE_L
VDDIO
MB_RAS_L
VDDIO
MB_CAS_L
MB_WE_L
MA0_CS_L[1 MA_ADD[13 MA1_ODT [0 MA0_ODT[0
MA_DATA[4
_L
]
MA1_CS_L[1
]
]
VDDIO
MB0_ODT [0
]
2]
MB_CLK_L[ MB_CLK_H[
VDDIO
3]
MB_BANK[1
]
MB1_CS_L[0
]
MB0_CS_L[0
]
MB1_ODT [0
]
MA_DAT A[3 MA1_ODT [1 MA0_ODT[1 MB1_CS_L[1 MB0_CS_L[1 MB_ADD[13
6]
VSS
]
MA_DATA[3
2]
]
VSS
]
MA_DAT A[3
7]
]
VDDIO
]
MB0_ODT [1
]
MA_DATA[5 MA_DQS_H[ MA_DQS_L[ MA_CLK_L[ MA_CLK_H[ MA_DAT A[5 MA_DATA[4 MA_DQS_H[ MA_DQS_L[ MA_DAT A[4 MA_DQS_H[ MA_DQS_L[ MA_DAT A[3 MB_DAT A[3 MB1_ODT [1
MB_DM[6]
D
E
RSVD
MB_ADD[15 MB_ADD[14 MB_ADD[12 MB_BANK[2
]
C
VDDIO
MA_CLK_L[ MA_CLK_H[ MA_CLK_L[ MB_CLK_L[ MB_CLK_H[ MA_EVENT MB_CLK_L[
VDD
4]
4]
MA_DATA[2
MA_CLK_L[ MA_CLK_H[
VSS
VSS
VSS
MB_DQS_L[
MB_DQS_H[
N
P
VDD
1]
3]
MB_DM[3]
R
VSS
MA_DATA[5 MA_DAT A[5 MA_CLK_L[ MA_CLK_H[ MA_DATA[4 MA_DAT A[4 MA_DATA[4
VSS
3]
MA_DQS_H[
B
MB_ADD[9]
VDDIO
VDD
3]
9]
5]
VOID
VDDIO
]
VSS
MA_DATA[5
8]
MA_DATA[2
A
VSS
MA_ADD[8] MA_ADD[6] MA_ADD[5] MA_ADD[4] MB_ADD[7] MB_ADD[8] MB_ADD[5] MB_ADD[6]
VDD
0]
5]
MA_DM[3]
31
VOID
]
MA_ADD[11
]
VSS
MA_DATA[5
9]
4]
VSS
30
VOID
]
VDDIO
]
VDD
AF
8]
MB_DATA[2
MA_CHECK MA_DQS_L[ MA_DQS_H[
Y
AE
29
MA_DAT A[2 MA_CHECK MA_CHECK MB_CHECK MB_CHECK MB_CHECK
W
0]
28
MA_DATA[2 MA_DAT A[1 MA_DATA[2 MA_DAT A[3 MA_DAT A[3 MB_DAT A[3 MB_DAT A[3
RSVD
VSS
MA_DATA[6
27
MB_DATA[1 MB_DAT A[2 MB_DQS_L[ MB_DQS_H[ MA_DQS_H[ MA_DAT A[1 MA_DATA[2 MA_DAT A[2 MA_DQS_L[
MA_DQS_H[ MA_RESET MA_DATA[1 MA_DAT A[1 MA_DATA[2
MA_DQS_L[
24
MB_DAT A[2 MB_DATA[2 MB_DAT A[1 MB_DATA[2 MB_DAT A[2 MB_DAT A[2
J
AD
Figure 4.
18
MB_DATA[9 MB_CLK_H[ MB_CLK_L[ MB_DAT A[1 MB_DATA[1 MB_DAT A[1
5]
VSS
MB_DAT A[4
0]
VSS
5]
MA_DATA[4
1]
MA_DM[5]
MB_DATA[4
4]
4]
VSS
4]
MA_DATA[3
4]
4]
3]
6]
VSS
MA_DM[4]
VSS
]
MB_DAT A[3
7]
MA_DAT A[4 MA_DATA[3 MA_DAT A[3 MA_DAT A[3 MB_DAT A[3 MB_DAT A[3
5]
VSS
5]
MB_DATA[3
8]
9]
8]
VSS
MB_DM[4]
MB_DATA[5 MB_CLK_L[ MB_CLK_H[ MB_DAT A[4 MB_DATA[5 MB_DAT A[4 MB_DQS_L[ MB_DAT A[4 MB_DATA[3 MB_DAT A[3 MB_DATA[3 MB_DQS_H[ MB_DQS_L[
4]
6]
6]
8]
2]
6]
5]
5]
5]
4]
9]
4]
4]
17
18
19
20
21
22
23
24
25
26
27
28
29
3]
2]
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
VSS
VOID
AK
VOID
VOID
AL
30
31
Color-Coded Connection Diagram (Right Half)
Pins
19
AMD Confidential – Advance Information
PID:40778 Rev 1.13 – January 2009
2
Socket AM3 Processor Functional Data Sheet
Package Specifications
2.1 Mechanical Loading for Lidded Parts
Table 10 provides the mechanical loading specification for lidded parts. These specifications should
not be exceeded during heat sink installation, system testing, or system shipment.
Table 10. Mechanical Loading for Lidded Parts
Type
Static
Dynamic
Maximum
Force
Units
lbf
lbf
100
200
Notes
1, 2
1, 3
Notes:
1.
2.
3.
Load specified for coplanar, uniform contact to lid surface.
The static specification specifies the allowable range to be applied by the heat sink to the processor package.
The dynamic specification assumes a dynamic load that includes the static load and is applied at 50 G for 11 ms.
2.2 Package Insertions
Table 11 provides the recommended number of times that the processor package can be inserted and
removed from a socket.
Table 11. Recommended Number of Insertions
Package
Number of Insertions
AM3
15
Package Specifications
20
AMD Confidential – Advance Information
PID:40778 Rev 1.13 – January 2009
Socket AM3 Processor Functional Data Sheet
2.3 Package Diagram
82)
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Figure 5. Organic Micro Pin Grid Array Package(UOF): Top, Side, and Bottom Views
(Lidded)
Package Specifications
21