A Mixed-Signal ASIC Power-Factor-Correction(PFC) Controller for High
Frequency Switching Rectifiers
Regan Zane and Dragan MaksimoviC
Colorado Power Electronics Center (CoPEC)
Department of Electrical and Computer Engineering
University of Colorado, Boulder, CO 80309-0425
zane@colorado.edu, maksimov@colorado.edu
Abstract - A mixed-signal I C controller is described for singlephase PFC applications. The single-chip controller block diagram is described, and the fundamental analog and digital operating blocks are developed in detail. Implementation options
for each block are given, with experimental results from a 1 . 2 , ~
CMOS test chip included. The controller blocks are derived for
boost and buckhoost type converters, but control of other power
stages could be derived in the same manner. The final controller
is proposed as a single-chip PFC solution, with no external design
or components necessary for high-performance, stable operation
over a wide range of operating conditions.
2) Low-cost: System costs can be split into two categories: componentlproduction costs and design costs. To minimize componentlproduction costs, controller power-stage interfacing should
be simple with few components needed. To reduce design costs,
very little design should be necessary to implement the controller using the most common power stages for particular applications.
3) High-pegomance: Performance requirements for front-end
AC-to-DC converters are driven primarily by regulations that
specify limits on input current harmonics [SI. Also, it is often desirable that the system operate over universal-input voltage range and a wide range of load conditions. In general, the
controller should force the power-stage to achieve low current
harmonic distortion and near-unity PFC, while maintaining as
wide-bandwidth control of the output voltage as possible within
input harmonic constraints. Regulations such as IEC 1000-3-2
can often be met using simple controller/power stage configurations without precise input current shaping. On the other hand,
the regulations proposed for avionics applications have much
tighter limits on the line-current harmonic contents. These limits
can be met only using high-performance low-harmonic rectifiers
I Introduction
Many new control techniques for AC-to-DC power converters have
been developed in response to tightened regulation of the input current
harmonic content [ 11-[4]. These controllers generally add complexity
and cost to power systems with the performance benefit of powerfactor-correction (PFC) and low current harmonic distortion. While
such methods have been successful at meeting the demands of many
systems over the past ten years, especially using analog ICs that combine multiple control components on a single chip (such as [13]), the
recent proliferation of electronic systems throughout the home and office places new constraints on front-end AC-to-DC converters. Specifically, applications such as light-weight, mobile equipment, “smart”
appliances, and fluorescent lighting demand controllers that result in
smaller, lighter, cheaper and higher-performance power systems.
In leading up to the solution described in this paper, we will first
examine each of these power system requirements and their implications on the controller:
1) Small foorprint & light weight: In order to reduce the size and
weight of power-stage components, the converter must be operated at high switching frequencies, likely from hundreds of
k H z to M H z . Also, the controller shouldn’t require additional
power-stage components for proper operation. To reduce the
size of the controller, multi-function chips should be used and
total component count should be minimized.
This material is based upon work supported by the National Science Foundation under Grant No. ECS-9703449 and by the University of Colorado 1998
Summer Session Research Grant.
0-7803-5421-4/99/$10.00 0 1999 IEEE
[W.
Combining the above requirements, an ideal solution would be a
low-cost, single-chip controller capable of switching frequencies from
hundreds of k H z to M H z that requires no external design and very
few external components for stable operation over a wide range of
operating conditions for most common power stages. The analog ICs
available today offer many of these characteristics, but are not capable
of the adaptive functions necessary for stable, closed-loop operation
over wide operating conditions without additional system design. Due
to the versatility and adaptability of digital signal processors (DSPs),
many DSP controllers have been proposed and implemented for lowfrequency, high-power applications [9]-[ 121, especially in the area of
motor drives [14]. However, due to the high-frequency and low-cost
requirements of the PFC controller, DSP solutions appear infeasible
for the foreseeable future, even with the rapid growth in digital technologies.
This paper presents a mixed-signal IC controller that combines the
benefits of analog and digital techniques, with the potential of meeting
117
power converter
L4-l
driver
I
clock
t
b
4
------ k----------------’
Mixed-Signal IC Controller
Figure 2: Step-upldown controller waveforms
Switch Freq. Select
Figure 1: Mixed-Signal IC Controller Block Diagram
all of the ideal PFC control characteristics detailed in the preceding
argument. The general design and operation of the controller is described in Section 11. Implementation options for each primary block
are then developed in Section 111, with experimental results from a
1 . 2 CMOS
~
test chip included where applicable.
I1 IC Controller Description
The ideal PFC control objectives are to maintain the low-frequency
portion of the input current i, proportional to the input (full-waverectified ac line) voltage vg,and to keep the output dc voltage V, at a
specified reference level,
A general block diagram of the proposed controller is shown in
Fig. 1, where the control input to the power stage is the switch gate
drive signal, c ( t ) . The power stage operates with a fixed switching
frequency fs and variable duty ratio D, and can be analyzed using
standard techniques [ 5 ] . The controller is based on the non-linear carrier (NLC) control method to achieve the performance requirements
of (1) while maintaining simplicity and IC implementation potential
[6]. At the beginning of a switching period, a fixed-frequency clock
pulse sets the switch drive high. A signal proportional to the integral
of the power stage switch current, i 4 ( t ) ,is then compared to a judiciously selected non-linear waveform, i c ( t ) ,resetting the switch drive
when i,(t) = ic(t), and thus controlling the power switch duty cycle.
General operating waveforms for a step-upIdown controller are shown
in Fig. 2.
In developing the mixed-signal IC, each functional block of the
controller in Fig. 1 was examined separately to determine if its specified function coupled with its interactions with other blocks would
be best performed using analog or digital circuit techniques. Starting
with the power switch current integration block, analog implementation offers the benefits of simple interfacing with the power-stage and
infinite time resolution in the output i, ( t )for continuous duty-ratio.
On the other hand, digital implementation results in precise control
of the integration factor and automatic switching frequency scalability, but very complex high-speed A/D conversion of hgh-frequency
switch current, possible sensitivity to switching noise and stability
problems with discrete-time output and resulting duty-ratio. Thus,
analog techniques were chosen, with the need for adaptive circuitry to
vary the integration factor with switching frequency.
The NLC waveform generator block must regenerate an amplitude modulated waveshape, dependant only on the power-stage type,
within each switching cycle. This has been performed off-chip using
discrete passive components in the analog domain [7]. To maintain
precise waveshape generation over a wide range of switching frequencies on an IC, a digital NLC generator was used with an output DIA
converter for continuous comparison and infinite duty-cycle resolution. Interfacing with the outer-voltage feedback loop can be acheved
using either digital preset modulation in the generator or analog modulation in the DIA converter, depending on the feedback filter type
used.
Finally, in order to maintain stable closed-loop operation while optimizing the transient response characteristics, the outer-voltage feedback filter must adaptively adjust its compensation for changes in
load. Due to the very low frequencies involved (twice line-frequency),
analog techniques would require off-chip components and would not
facilitate adaptive behavior. A digital feedback filter clocked at a low
frequency offers a good solution. For example, an adaptive, digital
feedback filter implemented using standard microcontrollers has already been discussed in [lo].
The full controller as outlined in Fig. 1 was simulated with ex-
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280ms
i(1ine)
290ms
Time
300ms
Figure 4: Experimental integration block waveforms for (1) integrator reset, (4) integration buffer output, with fs = 100kHz, D = 0.2,
I,, = 50mA.
Figure 3: Simulated AC line current waveform
tracted experimental waveforms from Section 111 using an averagedswitch model [8] of a step up/down power stage, with the resulting
ac-line input current
shown in Fig. 3, achieving a total harmonic
distortion (THD) of less than 5%.
I11 IC Controller Implementation
Two full-custom ASICs have been designed in 1.2p CMOS for
testing of the mixed-signal controller depicted in Fig. 1. The chips
were fabricated using MOSIS services [18]. The first chip isolated
each primary block for individual testing and evaluation, while the
second chip combined all blocks for full closed-loop operation with
the power-stage. Experimental results from the first test chip are included in this section where applicable, whereas the second chip is
still in fabrication and closed-loop experimental results are not yet
available. The final c h p can be operated with a single 5V power supply and a single high-frequency clock input.
Sub-Sections A, B, and C develop implementation options for the
three primary blocks of Fig. 1, namely the analog integration, NLC
generator, and digital feedback filter blocks. The second test chip also
included a current-comparator, switch-drive logic, and clock generation logic for control of switch-drive reset, integrator reset, and NLC
generator clocking and reset.
A. Analog Integrator
The analog integrator was designed using three stages. First, the input power-switch current was scaled down by a factor of 5000 using
closely matched current-mirrors. The design assumed a peak powerstage current of up to 5A, with a 1 : 100 current transformer for
50mA peak chip input current, scaled down to 10pA peak for the
integration stage. The second stage used an on-chip capacitor and reset switch for current integration, designed for operation at a switching frequency of fa = 100kHz. Due to the on-chip capacitor, the
integration constant was not exactly known, but only needed to be
maintained within a range of values dependant on the NLC generator
output. Future designs will employ adaptive control of the integration
constant or current scaling factor to allow for operation over a wide
range of switching frequencies. The final stage performed voltage-tocurrent conversion for interfacing with the current output of the NLC
generator. This was implemented using a voltage-buffer and on-chip
18KR resistor combination to maintain the current through the resistor proportional to the integration output voltage. Each of these stages
were tested separately from the first test chip and found to operate as
designed. Results from the integration stage are shown in Fig. 4.
B. NLC Waveform Generator
This section develops simple difference equations for ASIC hardware implementation of the NLC waveform generator of Fig. 1 for
two power-stage types. Additional generators could be developed in
a similar manner and included on the same chip with simple selection logic allowing a single chip to be used for all common power
stages. The ideal waveforms for step-up (boost) and step-up/down
(buck-boost, Flyback, Sepic, Cuk) switching converters are given by
163:
step-up:v,(t)
=
v,-(I--)
t
t
T,
T,
Vm-TS
t
= vc(t),
step - up/down : vc(t) =
vc(t+T,)
where v,(t) is the ideal NLC waveform (ic(t)in Fig. l), V, is the
slowly varying feedback signal, and l/Ts is the power stage switching
frequency.
Starting with step-up (boost) type converters [5] and sampling (2)
with a period T,, the resulting ideal NLC waveform is given by:
119
v,(nT,) = V,
-)TS
nT,
nT,
(1 ,
TS
(3)
3-bit Shift Register
U
Reset
K
Figure 6: Step-up/down NLC Generator Filter Implementation
I
-3
to focus only on the non-linear portion of the signal results in the samuled waveform:
Figure 5: Step-up NLC Generator Filter Implementation
(7)
using the same notation as in the step-up generator. Again using
the 2-Transform, the recursive form for hardware implementation is
found to be:
where n is the sample number. With the goal of a simple recursive
difference equation for filter implementation, the 2-Transform of (3)
is found to be:
)
z - ' ( l - b) - ~ - ~ ( 1b)+
1 - 32-1 3%-2 - 2 - 3
+
(4)
where l / b is an integer representing the number of samples per powerstage switching period. The Inverse 2-Transform is then used to find
the desired recursive difference equation:
Equation ( 5 ) can then be implemented directly in hardware, as shown
in Fig. 5, by pre-loading the first three points during reset, then operating the filter for the remaining portion of the switching period.
For step-upidown (buck-boost, Flyback, Sepic, Cuk) type converters [5], a discrete-time implementation is not as easily derived from
the ideal NLC waveshape (1) due to an infinite response at the start of
each switching cycle. However, a good approximation can be derived
using the same exponential generator analyzed in [7], for which the
sampled approximate NLC waveform becomes:
(6)
where a = 0.22 is a constant found to minimize the total harmonic
distortion (THD) of the input current over a universal input voltage
range, and Dmin is the minimum duty ratio expected for the operating load range. Normalizing and shifting the waveform by D,i,T,
This filter is shown in Fig. 6, where the reset signal loads the voltagefeedback signal vm[k]into the delay element input for Dm,,Ts, with
normal filter operation for the remainder of the switching period. Note
that the voltage-feedback filter operates at a much lower frequency
than the NLC generator, as signified by separate subscripts for the
two signals, vm[k]and vc[n]. Notice that for both NLC waveform
generators, the frequency factor b is given by the ratio of the controller sampling and power-stage switching frequencies, fc and fa respectively. Thus, if the two frequencies are scaled together internally,
the waveform generator operates independent of power stage switching frequency, as required by the application. An analog NLC waveform output ic(t) is achieved through a current-steering D/A converter
for high-speed, high-accuracy operation with minimal passive components [17]. Details of the circuit design were described in [19].
For the first test chip, a bit resolution of 6 bits and a sampling clock
frequency of fc = 40 * fs were chosen for good resolution at high
duty ratios and low total harmonic distortion (THD) of the AC line
current i l i n e . The resulting K from (8) is:
K = 0.890625dec = 0.111001btn .
(9)
The maximum bias current (peak vm [k])for the least-significantbit (LSB) was l p A , resulting in a peak (reset) current for ic(t) of
63pA. Low-pass filtering of the output was performed by sizing
of the output current mirrors. Experimental results are shown in
Figs. 7-8 for two switching frequencies, fs = 25kHz, and fs =
250kHz, which demonstrate valid operation independent of switching frequency. Higher frequency operation could not be accurately
recorded due to bandwidth and noise limitations of the testing structure, whereas in the final implementation of Fig. 1 all NLC waveform
generator signals will be internal to the chip with predicted switching
frequency fs operation up to M H z .
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7 ACqS
4
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Chl Freq
249.94kHZ
Low signal
amD Iit ude
amplttude
1
3
%:
I.. I.. . . I
..
Ch4
SOOmV%
.<ni\..
. . l i . , . v ~ 3 0 N o "1998
M 1 O OMS
30 N O V 1998
16:2S: 18
15 56 00
Figure 7: Experimental waveforms for (1) Dmin,(3) digital clock,
and (4) D/A converter output zc(t)(26pA/div],with fs = 25kHz,
fc
Figure 8: Experimental waveforms for (1) D,,,,
(3) digital clock,
and (4) D/A converter output i c ( t )[26pA/div],with fs = 250kHz,
= 1MHz.
fc
= 10MHz.
C. Digital Feedback Filter
A block diagram of the voltage-regulating feedback loop for the IC
controller is shown in Fig. 9, where F ( s ) is the low-frequencypowerstage control-to-output transfer function, G is a constant scale factor,
and A , ( z ) is the digital feedback filter transfer function. The power
stage transfer function is given by [7]:
where the converter pole frequency w p and transconductance gm are
defined as:
Figure 9: Voltage regulating feedback loop
and R, is the equivalent power-switch current sense resistance.
Many well-known methods are available for design of the digital
filter A , ( z ) in Fig. 9. Since the loop has already been analyzed, implemented, and tested in the analog domain, a logical approach would
be to use a discrete equivalent filter from the known A , ( s ) . Thus, the
compensation approach used here is modeled after that in [7], where
A,(s) was chosen as:
W O
A,(s) = -7
(1
+ -)s
W Z
E1 ,
[15]. The resulting discrete-time transfer function is given by:
where A1 and bl are given by:
A1
wz(tan
(13)
where wzis the compensator zero frequency, and integral compensation assures zero steady-state error in the output voltage. To achieve a
desired loop-gain cross-over frequency, the compensator zero is used
to cancel the converter pole, w z = wp, with a resulting cross-over
frequency given by:
=
bl
(+)+ 1) 2;
tan
('fi")- 1
tan
(y)
+ 1'
=
(16)
and T'j is the digital filter clock period. From the Inverse Z-transform,
the desired discrete-time difference equation is given by:
+
gm R
.
(14)
3
The desired digital feedback filter was determined via the bilinear
transformation (BLT) with pre-warping around the zero frequency, y Z
fcross
1
=
vm[k]= Alve[k] Alblve[]E- 11
-fo
+ vm[k - 11,
(17)
where a possible block diagram suitable for hardware implementation is shown in Fig. 10. In order to maintain optimum feedback
121
[7] R. Zane, D. MaksimoviC, “Non-linear-Carrier Control for HighPower-Factor Rectifiers Based on Up-Down Switching Converters,” IEEE Transactions on Power Electronics, Vol. 13, NO. 2,
March 1998, pp. 213-221.
[SI N. Jayaram, D. MaksimoviC, “Power Factor Correctors Based
on Coupled-Inductor Sepic and Cuk Converters with NonlinearCarrier Control,” IEEE APEC ’98, pp. 468-476.
Figure lo: Digital Feedback Filter Implementation
[9] M. Chang, J. Lin, Y. Tzou, “DSP-based Fully Digital Control
of a ACDC Converter with a Nonlinear Digital Current Mode
Control,” IEEE PESC 96, pp. 1702-1708.
for variable load and universal input conditions, the filter coefficients,
[lo] A. Mitwalli, S. Leeb, G. Verghese, V. Thottuvelil, “An AdapA1 and Albl, of Fig. 10 must adaptively adjust to maintain suitable
tive Digital Controller for a Unity Power Factor Converter,”
IEEE Transactions on Power Electronics, Vol. 11, NO. 2, 1996,
phase margin for closed-loop stability and a cross-over frequency sufpp. 374.
ficiently below the line-frequency output voltage ripple for low dis[ l l ] M. Tognolini, A. Rufer, “A DSP based Control for a Symmettortion. Additionally, care must be taken in choosing and generating
rical Three-phase Two-Switch PFC-Power Supply for Variable
Output Voltage,” IEEE PESC 96, pp. 1588-1594.
the digital filter clock frequency, ff, due to the line-frequency rip121
H.
Pinheiro, G. Jobs, K. Khorasani, ,“Neural Network-Based
ple, 2 f l , and switching frequency ripple, fa, on the sampled output
Controller for Voltage PWM Rectifier,” IEEE PESC 96,
pp. 1582-1587.
voltage. One option is to extract the line-frequency ripple and sample
131 Unitrode Product Guide, “High Power Factor Preregulator,
the output with a clock synchronized to twice the line-frequency. An
UC3854A/B,” Unitrode Integrated Circuits, Merrimack, NH,
on-chip anti-aliasing filter can then be used to filter out the switching
http://www.unitrode.com, 1998.
frequency noise.
141 Analog Devices Product Guide, “Single-Chip DSP Motor Drive
Controller with PFC, ADMC331,” http://www.analog.com,
1999.
V Conclusions
11.51 G. Franklin, J. Powell, M. Workman, Digital Control of DyA mixed-signal IC controller for single-phase PFC switching connamic Systems. Massachusetts: Addison-Wesley, 1992.
verters has been presented. The single-chip, high-performance con[16] R. Bachik, A, B r o c k s c k d t , c, )+person, K, Yuen, ‘‘fiactical Aspects of Line-Line and Line-Ground Single Phase PFC,”
troller combines analog and dlgital building blocks to achive operaIEEE APEC 99, pp. 342-348.
tion at high switching frequencies and no external components or de171 S. Soclof, Design and Applications of Analog Integrated Cirsign required for high-performance, stable operation. Internal blocks
cuits, New Jersey: Prentice-Hall, 1991.
were described with implementation examples given for boost and
181 http:/hww.mosis.com
buckhoost type power stages, and experimental results from a 1 . 2 ~ 191 R. Zane, D. MaksimovicC, “Frequency scalable non-linear
waveform generator for mixed-signal power-factor-correction
CMOS test chip were included. The proposed controller can be used
IC controller,” IEEE Custom Integrated Circuits Conference,
to implement high-performance, low-harmonic rectifier systems. It is
San Diego, May 16-19, 1999.
suitable for operation over universal input voltage range, wide switching frequency range, and variable load conditions.
Mixed-signal (analog and digital) ASICs, such as the PFC controller described in this paper, are proposed as an approach that would
enable advanced, high-performance control functions in future power
electronic systems.
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