1.
MuItimodule Parallel
Series-Loaded Resonant
Converters
S. J. CHIANG
C. M. LIAW, Member, IEEE
National Tsing Hua University
J. H. OUYANG
C. C. CHIANG
Industry Technology Research Institute
%wan
The design and implementation of a multimodule parallel
series-loaded resonant (SLR)converter system is presented.
The SLR converter to be paralleled is operated in the n = 2
discontinuous mode (DCM). Its de analysis and dynamic modeling
are made. In parallel operation, an average control technique
is proposed to compewate the mismatch in current control
characteristics of each parallel converter. Good dynamic and
static current sharing characteristics are obtained. In addition,
to obtain good output voltage regulatiq control performance, a
design procedure is presented to find the parameters of feedback
voltage controller according to the prescribed specifications.
Manuscript received December 11, 1992; revised July 23, 1993.
IEEE Log No. T-AESBl/l/M98.5.
Authors’ addresses: S . J. Chiang and C. M. h a w , Department of
Electrical Engineering, National Tsing Hua IJniversity, Hsinchu,
%wan, 30043,R.O.C.; J. H. Ouyang and C. C. Chiang, Electronics
Research and Service Organization, Industry Technology Research
Institute; Hsinchu, Biwan, R.O.C.
1995
I IEEE
0018-9251/95/$4.00 @
INTRODUCTION
Multimodule operation of converters has the
following advantages. 1) The converters can be
designed in modular fashion, and thus the system
power capacity can be easily enlarged by increasing the
number of parallel converters. 2) The system reliability
is greatly increased. 3) With appropriate configuration
arrangement and operation management, the overall
power conversion efficiency and the life of converter
can be increased. For a high performance multimodule
parallel converter system, in addition to good current
sharing property, good output voltage regulating
performance is indispensable. During the past years,
although the researches about the multimodule parallel
operation for switching type converters have been
made by some authors [l-31, the dynamic modeling,
controller design and implementation for parallel
resonant type converters are still seldom performed.
A series-loaded resonant (SLR) converter operated
in n = 2 DCM (discontinuous mode) can be used
in many applications, since it has the following
features [4]:1) Zero current switching and zero
voltage switching at turn off make it possess higher
efficiency and higher switching frequency than the
switching converters; 2) since the switches turn
off naturally, it is possible to use thyristors in low
switching frequency and high power applications.
In addition to these, the converter in this operation
mode behaves like a frequency controlled current
source; this makes it suitable for parallel operation.
However, since the switching frequency is variable and
the switching current is sinusoidal, the peak-current
control technique [5, 61, which is commonly used
for current-mode control of switching converters, is
not applicable any more. Here, the inherent current
sharing property of SLR converters operated in
n = 2 DCM is studied. The results indicate that in
the n = 2 DCM, the mismatch in current control
characteristics among parallel converters is caused
only by the difference of the capacitances of resonant
capacitors. Since the differences are generally within a
finite bound, the SLR converters have acceptable equal
current sharing capability.
For being a high performance parallel system, the
accurate current sharing property is very important.
To achieve this goal, an average current control
method is proposed. The output current o f each slave
module is compared with that of a master module; the
regulated current error signal is then used to modify
the control signal of the respective slave module. By
properly designing the current controllers in inner
loop, each slave converter current can closely track
that of the master converter both in the transient and
static periods. Based on the proposed current control
technique, the outer loop voltage controller can be
designed using an equivalent single-module model.
Both of the current controller and voltage controller
IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS VOL. 31, NO. 1 JANUARY 1995
257
are designed using the proposed systematic procedures
according to the prescribed specifications. The
simulated and measured results show that good current
sharing and output voltage regulating characteristics
are obtained by the proposed converter system.
11.
ANALYSIS OF SLR CONVERTER
Depending on the load condition and the ratio
between the switching frequency and the resonant
frequency, the SLR converter can operate in various
operation modes [4,71. Among these, n = 2 DCM is
the simplest mode to be analyzed. As stated in the
previous section, converters operated in this mode
are suitable for multimodule operation, thus only the
analyses of this mode are made here.
A.
-
vo
+
(4
DC Analysis
vg
The half-bridge SLR converter is shown in
Fig. l(a). For simplifying the analysis, no output
transformer is added and all devices are assumed
to be ideal. According to the direction of resonant
current i and the status of switch, the operation
in this n = 2 DCM is divided into four submodes.
The equivalent circuits and the related waveforms
corresponding to each submode are shown in Fig. l(b)
[4]. The resonant current i is rectified and filtered to
supply the output load current i o as shown in Fig. l(b).
Since the waveforms of the first half switching cycle are
symmetric to the later half cycle, only the analyses for
the last half cycle operation are made here. According
to the equivalent circuits and the typical waveforms
shown in Fig. l(b), the resonant voltage and current
of each submode under steady-state can be solved and
listed as follows.
1) 0 5 WOt < 7r
v(t) = (V, - Vo)(l- coswot) - 2Vocoswot
(1)
T 3 T "
"m"
iLl
( 5I
(4
where VOdenotes the steady-state output voltage and
+
v(t) = (-Vg Vo)coswot + (V,
+ Vo)
Fig. 1. SL!K converter. (a) Power circuit. (b) Equivalent circuits
and related vvaveforms in n = 2 DCM. (c) Operating characteristics
of SLR in n = 2 DCM.
where Ts dienotes the switching period. It is seen from
Fig. l(a) that i~ is rectified from the resonant current i,
i.e.,
iL = lil.
(8)
(4)
It consists of a dc component and a high frequency
componenit. The dc component of iL is just the average
load current lo, which is found as
IL = lo:= TsY2
2.58
v(t) = v(27r/wo) = 2V0
(6)
i(t) = 0
(7)
(1"'"'
(9)
IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS VOL. 31, NO. 1 JANUARY 1995
From (9) and (3) one can obtain:
vin=2vg
A
Equation (10) shows that in n = 2 DCM, the SLR
converter can be regarded as frequency control current
source. For verifying the operating range within which
(10) is reasonable, some simulations are made using
EMTP (electromagnetic transients program). The
circuit parameters listed in Section IV are used here
for these simulations. The relationships between F,
and VO(= IoR) for various values of load resistances
are plotted in Fig. l(c), in which, F, is the lowest
frequency (about 100 Hz)generated by voltage control
oscillator (VCO) and Fs (= 100 kHz) is the highest
frequency below which the SLR converter can operate
in n = 2 DCM. The results shown in Fig. l(c) indicate
that below the rated output voltage (VO= 10 V) and
within the range of load resistance 20/9n (rated
load) < R < 2 k a , the characteristics of frequency
control current source of (10) is true. However, for
larger value of output voltage, particularly for larger
value of load resistance, the output voltage becomes
saturated. This is mainly due to the fact that the output
voltage of SLR converter cannot exceed the input
voltage V, (= 24 V).
B.
Dynamic Modeling
The dynamic modeling of a resonant converter
is difficult, since the commonly used state-space
averaging method cannot be applied. To overcome
this difficulty, the concept of extended state-space
averaging method proposed in [8, 91 can be used here.
The basic concept of this method is that the averaged
high frequency dynamic behavior of the resonant
circuit is combined with the low frequency part of
the output circuit. For convenience of derivation, the
small signal equivalent circuit of Fig. l(a) is drawn
in Fig. 2(a). Where i~ and io denote the perturbated
average resonant current and load current, respectively.
i~ is found from (9) by replacing the steady-state
,
P, and F, + f,
values of IL, V,, and F, by IL f ~ V,
and neglecting the $Pg term as
+
VO
VgR
+i0)Zp
where
=
c
A
V
1
+
4+ - +J $7 , cG
"0
(b)
Fig. 2. Small signal model of SLR converter in n = 2 DCM.
(a) Output circuit. (b) Pansfer function block diagram.
and R, is the equivalent series resistance (ESR) of
the output capacitor. In practical realization, a VCO
is used to generate the switching control signal with
frequency fs. If the gain of VCO is K , then
f, = KP,
(14)
where 0, is the control voltage generated from the
regulated voltage error signal through a controller.
From (11) to (14), we can derive the following transfer
functions.
Control-to-output
G = SKCrVg.
Audio-susceptibility
Ou tpu t-impedance
The variation of output voltage 00 can be found from
the output circuit shown in Fig. 2(a) as
z p
(4
+
ir, = 8C,Vgfs + -0,.
Do = (iL
and
rectifier
circuits
R ( 1 + sCR,)
1 + sC(R + R,)
(12)
zo=
7
A 10 9,=op=o
=z p .
(17)
One can observe from (15)-(17) that in n = 2 DCM
the dynamic behavior of SLR converter is determined
only by its output circuit. The transfer function block
diagram corresponding to (15)-(17) is shown in
Fig. 2(b).
CHIANG ET AL.: MU1iTIMODUL.E PARALLEL SliRIES-LOADE<DRESONANT CONVERTERS
259
;:r+cT1tT$!a
Obviously, if all output capacitors are identical,
the equivalent ESR and capacitance become R: =
R,/(N 1) and C' = ( N + 1)C.
Since form Fig. l(c) and (lo), the SLR converter
behaves like a frepency controlled source, the
cross responses (fsi to i~,, i # j ) [lo] are very small.
Hence the cross transfer functions are not included
in the dynamic model of parallel multimodule SLR
converters. The current sharing property and the
design of voltage feedback controller are described as
follows.
Curren,tSharing Characteristics: Suppose
converter 1 in Figs. 3(a) and 3@) is regarded as master
converter, the current ratio of ith slave module to the
master module can be found from Fig. 3@) as
SLR Converters
&. ..... ..
2
I
"c
,
:
:
!
.
+
G
.
:
............... ...........
Ntl
h
+"0
i = 2,3, ..., N
+1
(19)
+
I
(b)
Fig. 3. Parallel converter system. (a) Circuit configuration.
(b) Closed-loop transfer function block diagram for direct parallel
connection without current control.
where G; 5 G1 AGi is assumed and AG; denotes
the mismatch between GI and Gj. The ratio of current
sharing mismatch between ith slave module and the
master module to the total current can further be
found to be
Ill. MULTIMODULE OPERATION OF SLR
CONVERTERS
A.
Module Paralleled Without Inner-Loop Current
Control
The circuit configuration of the parallel converter
system, which consists of ( N 1) modules (providing
the ( N 1) redundancy), is drawn in Fig. 3(a) where
the control voltage (current command) V, generated
from a voltage controller is common for all modules.
Since the effect of input voltage variation D, is much
smaller than that of output current io, it is neglected
in the controller design introduced here. Accordingly,
a transfer function block diagram can be drawn in
Fig. 3(b) from Figs. 2@) and 3(a) where CV is a
voltage feedback controller and
+
+
Zb = z p l / / z , 2 / / " ' / / Z p , N + I
= (R.1
XR:+-
+
&-)/ I ( R d + &)
Tf only two modules arc paralleled ( N = 1) and
AG2 is within f10% of GI due to the variations of
capacitance of resonant capacitor C,, then from (20)
the maximum value of R T is
~ 5.26%. Practically, this
is in acceptable range. The maximum value of R T ~ ,
i = 2, ...,AT 1will be decreased as the number of
paralleled converters is increased.
Design of Voltage Feedback Controller:
The controller CV shown in Fig. 3@) is the
proportional-plus-integral (PI) controller, which has
the following structure:
+
Generally, the parameters of CV arc found based
on trial-and-error approach. In the following, a
systematic and quantitative procedure is to design the
PI controller according to the prescribed specifications.
The closed-loop transfer function of PO to io is derived
from Fig. 3(b) as
1
SC'
where the impedance of Zk is assumed to be
approximated by an equivalent series RC brhnch.
260
IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS VOL. 31, NO. 1 MNLJAKY 199.5
where
U =
1
C'(R
+ R:) '
c=-
1
C'R;.'
d=-
RR:
R+R:'
O +
4
N+l
b=dG',
(23)
G'iCG;
i=l
Fig. 4. Closed-loop transfer function block diagram of parallel
converter system with current contrcil.
(27)
For evaluating the regulating performance, the output
voltage response due to unit-step load current change
is found from (22) as
vg(t) = hle-pIr
+ hze-flz'.
(28)
For ease of derivation, suppose that p1 and p2 are all
positive real and p2 > p l . Using (B),
one can find the
time at which the maximum dip of vg(t) occurred and
the maximum dip to be
and
+ h2
(2)
(A)
(30)
112 - 111
from (23), (29), and (30) as
This is the voltage dip due to ESR of output capacitor
and cannot be eliminated by using control technique.
It can only be reduced by adopting the capacitor with
lower ESR.
2) If v d m = V'.d is required, one must take the
saturation of control effort into account, since in this
case the control is more demanding.
3) The constraint of p1 and 112 being a11 real is
rather strict, and slower regulating response speed
is resulted. This limitation can be relaxed by making
a more general formulation in which p1 and p2 arc
complex conjugates.
B.
Module Paralleled With Inner-Loop C u r r e n t
Control
respectively.
In order to specify the response speed, define t,, to
be the time at which the response of vo(t) restores to
5% of v d , , then the following equation is yielded
For achieving more accurate dynamic current
sharing characteristics, an average current control
technique is proposed. In Fig. 4, Cli, i = 2,3,. .,N 1
are the current controllers for ith slave module.
The average current for each module is obtained
v d m = 20(hle-"1're + h2e-pzfr.).
(31) by rectifying the resonant current and filtering by
the low pass filter E The error of average currents
According to the above analysis, the design procedure
of ith slave module and master module is regulated
for the controller Cv is summarized as follows.
through current controller Cli, the resulted signal Dm,
Step I Define the specifications of v d , and t,,.
is augmented to the control signal 9,(D,1 = 9 , ) to yield
Sfep 2 Solve p1 and 112 from (30) and (31).
the control signal Pci, which is then sent to adjust the
Sfep 3 The parameters Kp and K I of the voltage
output current of ith slave module. The effect of input
controller Cv are found using (24) and (25).
voltage variation 9, is also neglected here.
Comments.
Design of Inner-Loop Current Controller: Since the
1 ) In the design process described above, the
response speed of the inner current loop is much faster
minimum value of Vdmcan be obtained by letting
than the outer voltage loop, the outer loop is neglected
tdm = 0, i.e., the maximum dip is forced to occur at
t = 0. In this case, the maximum dip v d , can be found in the design stage of current controller C r , . The
CHIANG ET AL.: MULTIMODULE PARALLEL SERIES-LOADED RESONANT CONVERTERS
+
261
design of Cf; can be treated as the tracking problem;
its major purpose is to let the current of ith module
closely follow that of master module. The structures of
the filter F and the controller CI; are chosen to be
F(s)=
+
a
(33)
1 CfRfS
From Fig. 4 and using (33) and (34) one can derive the
ratio of these two currents as
Similar to the design procedure introduced prek iously,
by specifying the desired response time, p1,p2 can be
solved from (43) and (44),and then Kpi and K,i can
be found from (38) and (39).
Design of Voltage Controller: Once all controllers
C I ; ,i = 2,3,...,N + 1 are all successfully designed,
we can treat i ~ =i i ~ 1 ,i = 2,3,.. ., N 1 in the design
of outer-loop voltage controller CV. Thus G' in (23)
becomes G' = ( N + 1)Gl and the design procedure
developed in Section IIIA can also be used here to
find the parameters of CV (the effect of 0, is not
considered).
+
C.
Design of Input Voltage Feedforward Controller
(35)
where the transient part T1i is defined as
T A
- S2CfFf
aAGi(Kp;s + Kr;)
+ [l + a(Gi + AG;)Kp;]s + a(Gi + AG;)Kri
'
(36)
For investigating the tracking problem, i ~ is1 treated
as a command. The steady-state value of the unit-step
response found from (35) is equal to unity. So there is
no steady-state current sharing error. As to the analysis
of the dynamic response characteristics, TI;of (36) can
be used. The partial fraction form of T1i is
hi
h2
TI&) = -+ s+p1 s + p 2
(37)
where
pi
hl
+ p2 = -[11
Cf R f
+ a(G1+ AG;)Kpi]
(38)
Although the effect of input voltage variation on
the output voltage is much smaller than that of load
current and it is neglected in the design of feedback
controllers, the feedforward controller G f shown
by dotted line in Fig. 4 can be augmented to reduce
its effect. Since G1x G z E . . . M G N + ~if ,all the
inner-loop current controllers are properly designed,
the controller G f can be found [12] to be
Gf = M/GI.
(45)
Generally, complete elimination of the effect of input
voltage variation under various operating conditions
is impossible, since (16) and (45) indicate that G f is a
function of load resistance. It is suggested here that the
nominal load resistance is used to design the controller
Gf.
IV.
DESIGN OF PROPOSED PARALLEL CONVERTER
SYSTEM
The experimental parallel SLR converter system is
assumed to consist of two modules. The specifications
of each module are
1
+ h2 = -
Cf R f aKpiAGi
vg = 2!4 v,
The unit-step response of
7'1i
h ( 1 - e-pIf)
y(t)= L
P1
A.
is
h2
+ -(1-
e-p2').
P2
If p1 and p 2 are all real and positive and p2
condition for no overshoot of (42) is [ll]
hl = d f i h 2 .
(42)
> p1, the
VI = 10 v,
Iomax
= 45 A. (46)
Power Circuit
If the resonant frequency fo is chosen to be
200 kHz, to ensure each SLR will work in n = 2 DCM,
the maximum switching frequency F,,,, is set as a half
of fo, i.e., E,,,, = 100 kHz. The resonant network can
be determined using (10) and (3) as:
(43)
Furthermore, the response time t,, is defined to be
the time at which y(t) reaches 90% of its steady-state
value, then from (42) one can write
From (2), the peak value of resonant current is
262
IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS VOL. 31, NO. 1 JANUARY 1995
0 9L
A
2__Lpi-.
1
2
3
4
5
7
6
U
om1
0 . 0 0 ~ 0.003
0.004
lxl0-31
Time (sec)
0.005
0.006
o.007
o uun
u.008
0 IOG7
0008
0 009
Time ( S e c )
Fig. 5. Simulated current tracking responses.
It is known that a lower value of ESR (R,) leads
to smaller steady-state output voltage ripple as well as
smaller voltage dip due to step load current change.
However, the capacitor with a low value of ESR is
generally large in size. This leads to slower output
voltage regulating response, since according to the
analysis made in Section 11, the dynamic of SLR
converter in n = 2 DCM are mainly determined by
the output circuit. If the maximum value of ripple
corresponding to the peak current of (48) is set no
larger than 0.5 V (5% of nominal output voltage),
the ESR must be not greater than 0.5/10 A =
50 mil. Accordingly, a capacitor having the following
parameters is chosen:
C = 3300 pF,
R, = SO m a .
(49)
0
0 001
0 002
0003
0004
0005
0006
Tmie(Sec)
(b)
Fig. 6. Simulated closed-loop responses. (a) Current tracking
characteristics. (b) Output voltage regulating characteristics.
Following the design procedure described in Section
IIIA, the parameters of the voltage controller Cv are
obtained as
Kp = 67.915,
K I = 53722.
(55)
The simulated responses due to step load current
B. Controllers
change (lo = 1 A to 7 A) plotted in Figs. 6(a) and
6(b) show that good current traclung performance
The parameters of VCO and the filter for the slave is obtained and the voltage regulating response also
and master converters are
satisfies the prescribed specifications listed in (54).
When the converter is operated at 90% rated load
K = 5037.02 and
a = 0.25,
( l o = 8 A), the simulated output voltage and current
(50)
responses without adding the feedforward controller
Cf Rf = 1.8 x lo-'.
due to 10% input voltage variation (frequency =
120 Hz) are shown in Fig. 7.The results show that the
Assume that the mismatch between the current
variations in the output voltage and current sharing
tracking response is
characteristics are small. If further improvement is
AG = fO.lGl
(51) needed, the feedforward controller of (45)is designed
to be
and the desired response time of the current tracking
response is
Gf = M / G l = 0.302
( R = 1.25 (2).
(56)
t,, = lms.
(52) The simulated results shown in Fig. 8 indicate that
Following the design procedure introduced in Section
IIIB, the parameters of the current controller C12 of
(34) can be found as
Kp2 = 3.728,
K12 = 4.3593x
lo4.
The simulated responses of i , y / i ~shown
l
in Fig. 5
indicate that the given tracking characteristics are
exactly satisfied.
Having designed the current controller, the
specifications of unit-step response for designing
the voltage controller Cv are prescribed as follows
(R= 10/7R):
t,, = 4ms,
V& = 0.022 V (1 A).
significant improvements in the input voltage rejection
characteristics have been achieved.
(53) V. SOME EXPERIMENTAL RESULTS
Having confirmed the effectiveness of the proposed
controller, the circuit implementation of the designed
current and voltage controllers are performed. The
measured and simulated frequency responses of
control-to-output transfer function of single module
under nominal case ( R = 10/4R) are compared in
Fig. 9.The validity of the small-signal model developed
in Section IIB can be confirmed from the results.
(54) Supposed that the two paralleled converters are
CHIANG ET AL.: MULTIMODULE PARALLEL SERIES-LOADED RESONANT CONVERTERS
263
2gr---
,
-
--
.
19L
o
o 005
001
ooir
0.025
002
003
0035
1
d
0.04
0045
Time (Sec.)
0.zr
,
,
-40t
l
__ Simulated
...
result
Measured r e s u l t
(1.5
0
10
__
I
0005
001
0015
1
15
2
25
3
35
4
1
002
0025
0035
003
004
Frequency IOexp (Hz)
0045
Time ( S e c )
Fig. 9. Simulated and measured frequency responses
control-to-output transfer function.
3f
the
"0
V
-0.510
.
'
0 005
0.015
0.01
I
- j -
0.02
0.025
I
--d
0.03
0.035
0.04
0 045
Time (Sec.)
Fig. 7. Simulated waveforms of output voltage and converter
currents due to varying input voltage without feedforward
controller.
29-
,
tP
I
19 I
0
0.005
0.015
0.01
0.02
0.025
0.03
0.035
0.04
0.045
0.035
0.04
0.045
Time (Sec.)
I
0
I
0.005
Fig. 10. Measured dynamic responses ot the converter :urrents
and the output voltage due to step load current change (1 lo 7 A)
0.01
0.015
0.02
0.025
0 03
are also observed. Under steady-state condition with
la = 4 A, if one module is suddenly terminated and
then restored to its operation, the dynamic responses
of converter output currents io1 and im and output
voltage are plotted in Figs. ll(a) and ll@).Good
performances obtained by the proposed controller
are further verified by the results. The responses of
output voltage due to input voltage variation without
and with feedforward compensator G f arc shown in
Figs. 12(a) and 12@), respectively. The effectiveness
of augmenting the feedforward compensator is quite
obvious from the results shown in Fig. 12.
Time ( S e c . )
VI.
CONCLUSIONS
-1
The analysis, design and implementation of '1
parallel SLIX converter system have been introduced
in the previous sections. To let the SLR converter be
suitable for parallel operation, it is forced to operate
-051-_.
I
in n = 2 DCM. The dc analysis, resonant circuit
0
0005
001
0015
002
0025
003
0035 0 0 4 0 0 4 5
design, and dynamic modeling are made. According
Time (Sec )
to which, the inherent current sharing property is
Simulated
waveforms
of
output
voltage
and
converter
Fig. 8.
investigated
and the average current control technique
currents due to varying input voltage with feedforward controller.
is proposed to yield good dynamic and static current
sharing characteristics. The voltage feedback controller
normally operated, the dynamic responses of converter is designed using a proposed systematic procedure
such that the prescribed specifications are satisfied.
l
i ~ and
2
output voltage due to step
currents f ~ and
The simulated and experimental results show that
load current change (io = 1 A to 7 A) are shown in
good current sharing and output voltage regulating
Fig. 10. The yielded voltage response is very close
performances are achieved by the parallel convcxter
to the simulated result shown in Fig. 6(b). Good
system controlled by the proposed controller.
dynamic and static current sharing characteristics
A
264
IEEE TRANSACTIONS ON AEROSPACE ANI) ELECTRONIC SYSTEMS VOL. 31. NO. 1 JANUtiRY 1995
REFERENCES
[l]
[2]
[3]
lo 1
[4]
lo2
[SI
V
n
VO
[6]
(b)
Fig. 11. Measured dynamic responses of converter output currents
and output voltage due to change of system configuration.
(a) Module 2 is suddenly terminated its operation. (b) Module 2
is suddenly restored.
V
[7l
[8]
2 4V
[9]
V
2v
[lo]
V
[ll]
2 4V
[12]
V
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(b)
Fig. 12. Measured output voltage waveform due to varying input
voliage. (a) Without feedforward controller. (b) With feedforward
controller.
CHIANG El' AL.: MU1,TTIMODULE PARAILEL SERIES-LOADED RESONANT CONVERTERS
265
C. M. Liaw (S’tW-M89) was born in Taiwan, Republic of China, on June 19,
1951. He received the B.S. degree in electronic engineering from the Evening
Department of Tmmkang College of A.rts and Sciences, Bipei, Biwan, in 1979,
and the M.S. and Ph.D. degrees in electrical engineering from National Tsing E
University, Hsinchu, Taiwan, in 1981 and 1988, respectively.
He is presently a Professor at National Tsing Hua University. His area.; of
research interest are control of motor drives, adaptive control systems, control
power systems, and power electronics.
S. J. Chiang was born in niwan, Republic of China, on Feb. 7, 1965. He received
the B.S.E.E. degree from the National Tsing Hua University, Hsinchu, Taiwan, in
1987.
He is currently working toward the Ph.D. degree at the National Tsing Hua
University. His research interests are ]power electronics and control systems.
Jr-Hong Ouyang was born in Changhua, Taiwan, Republic of China, on Oct. 5,
1964. He received the B.S. degree in electrical engineering from %tung Institute of
Technology, Taipei, Taiwan, in 1987, and the M.S. degree in electrical engineering
from National Tsing Hua University, Hsinchu, Taiwan, in 1989.
Since 1989, he has worked as an electrical engineer at Electronics Research
and Service Organization, Industrial Tkchnology Research Institute, Hsinchu,
Taiwan, R.O.C. His current research interests are power electronics and control
systems.
Chih-Chiang Chiang was born in Bichung, Taiwan, R.O.C., on Sept. 18, 1965.
He received the B.S. degree in automatic control engineering from Feng Chia
University, Bichung, Biwan, in 1988, and the M.S. degree in nuclear engineering
from National Tsing Hua University, Hsinchu, Biwan, in 1990.
Since 1990, he has worked as a design engineer at Electronics Research and
Service Organization, Industrial lkchnology Research Institute, Hsinchu, Taiwan,
R.O.C. His current research interests are power electronics and control systems.
266
IEEE TRANSACTIONS ON AEROSPACE AND ELECTR.ONIC SYSTEMS VOL. 31. NO. 1 JANLARY 1995