Tips and Tricks to Get More Out of Your SPICE Models
Scott Pearson, Alain Laprade
Abstract — Circuit simulation tools are useful supplements
to breadboarding for gaining fast and detailed design insight.
A collection of simulation tips and tricks used by our
applications support group is presented.
Fairchild
Semiconductor offers interactive on-line design simulation
tools and device models for off-line simulations.
I. INTRODUCTION
The various simulation tips presented demonstrate
methods to accomplish simulations not possible
using only native models included with the
ORCAD® simulator. Examples are a resistor with
dynamic temperature feedback, voltage controlled
reactive models (capacitors and inductors) and
analog behavioral models for complex waveforms.
Also included in this paper is a discussion of the
thermal model and its importance to the designer.
Use of the thermal model will give an indication of
the junction temperature ensuring device
specification are not exceeded.
Detailed instructions on how to use the models
provided by Fairchild Semiconductor will be
provided. Models and instructions given here are
applicable for ORCAD® simulation products, but
assistance with other simulation tools is available.
Another option offered to designers is on-line
simulation tools such as FETBench®, which will be
introduced here.
Finally, circuit simulation convergence can be a
frustrating issue. Tips are described which can
minimize such issues.
Fixes which improve
convergence can also result in reduced simulation
times.
dynamically during the simulation. A temperature
sweep will perform independent static simulations
at various temperatures.
TABLE I
RESISTOR TEMPERATURE COEFFICIENT SPICE LISTING
Rvtemp 18 19 RvtempMOD 1
MODEL RvtempMOD RES (TC1=-2.5e-3 TC2=1e-6)
The ability to describe the value of a resistor and
its temperature coefficients as an analog behavioral
model (ABM) referenced to a voltage node (making
use of electrical thermal analogy) is necessary to
express dependence on operating temperature.
Voltage node references within PSPICE resistor
models are not permitted. Dynamic temperature
dependence of resistive elements (expressed as
separate lumped elements) cannot be implemented
without a resistor ABM.
This limitation is overcome with a voltagecontrolled current source ABM expression (Fig. 1).
By using the nodes of the current source for voltage
control, resistor behaviour may be expressed as a
current source as in (1). Resistance R(Td) is
replaced with a behavioral mode analytical
expression that is a function of the electrical
analogy voltage node Td as shown in the next
section. The form for the ABM netlist expression is
described in Table II.
I=
V
R(Td )
+
+
I
II. A PSPICE RESISTOR MODEL HAVING
DYNAMIC TEMPERATURE CAPABILITY
Use of dynamic temperature information within a
closed loop system simulation can run into
algorithm limitations with some simulation software
such as PSPICE. The SPICE resistor model may be
set to have temperature dependence as in the listing
from Table I. PSPICE will only run simulations at a
single temperature defined in the simulation setup
menu, and this temperature setting cannot be varied
(1)
-
I=V/R(Td)
-
Fig. 1 Implementing a voltage dependent ABM resistor model.
TABLE II
Voltage Dependent ABM resistor model netlist.
G_Resistor
Node1
Node2
Value={V(node1,Node2)/
+function(V(Td))}
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Fairchild Power Seminar 2007
III. THERMAL MODELING
Semiconductor devices often operate at high
junction temperatures. Understanding their thermal
limitations is important to achieve good device
reliability and system performance targets. Circuit
designers are responsible for performing junction
temperature calculations to verify that their devices
operate within manufacturer specifications.
Measurement of semiconductor thermal response
involves a calibrated power pulse. Power dissipated
within a device causes a junction temperature rise
because of the thermal impedance from the die and
package. (2) describes thermal impedance as the
result of a change in junction temperature divided
by power dissipation.
ZθJC ( t ) =
∆TJ ( t ) TJ ( t ) − TJ (0)
=
PD
PD
(2)
A basic semiconductor thermal model and its
electrical analogue is shown in Fig.2. Heat is
generated at the device junction and flows through
the silicon to the case, and finally to the heat sink.
Tjunction
ZθJC
Tcase
ZθCS
Tsink
ZθSA
a circuit form representation of the junction
temperature as expressed in (3).
TJ = Tambient + G _ Pdiss • ( Z θJC + Z θCS + Z θSA )
(3)
where
TJ = junction temperature
G_Pdiss = instantaneous power loss
ZθJC = thermal impedance junction-to-case
ZθCS = thermal impedance case-to-heat sink
ZθSA = thermal impedance heat sink-to-ambient.
The unit conversion for the electrical analogy of
the thermal system is listed in Table III. ZθJC is
provided in manufacturer data sheets using the
single pulse normalized thermal impedance curve as
in Fig. 3. ZθJC may be represented using an
equivalent electrical analogy model as in Fig. 4.
TABLE III
ELECTRICAL/THERMAL ANALOGY
Electrical
⇔
Thermal
o
Ohm (resistance)
C/Watt (thermal resistance)
Farad (capacitance) Joules/oC (thermal capacitance)
Amp (current)
Watt (power)
o
Volt (voltage)
C (temperature)
Tambient
Fig. 3 Normalized maximum transient thermal impedance.
Die
Power
Dissipation
Insulator &
interface
Heat sink
G_Pdiss
Transistor
Fig. 2 Semiconductor thermal impedance model.
Junction temperature information is determined
by the inclusion of the device’s thermal network
ZθJC and current source G_PDISS. The thermal
network parameters are supplied in Fairchild
Semiconductor data sheets.
G_PDISS is the
semiconductor’s instantaneous operating loss, and
expresses the result in the form of a current. This is
Fig. 4 Semiconductor thermal impedance model.
When model parameters are unavailable, they
may be derived from the datasheet RθJC and from
the single pulse normalized thermal transient
impedance curve data points. The electrical analog
model may be expressed as in (4). The R-C
parameters may be obtained by using curve fitting
software such as TableCurve 2D® [15].
Z( t ) = R 1 ⋅ (1 − e
A-64
−t
R1 ⋅C1
) + Κ + R 6 ⋅ (1 − e
−t
R 6 ⋅C 6
)
(4)
Fairchild Power Seminar 2007
Knowing operating waveforms and system level
thermal impedance information, thermal response to
complex waveforms may be analyzed. An example
circuit and simulation result for a MOSFET
operated under continuous conduction is shown in
Fig. 5, where a 60A/40ms current pulse is applied to
an FDB8445 MOSFET [12] having a case
temperature of 120oC. The simulation is in closed
loop form. The temperature dependent RDS(on) and
junction temperature responses are shown in Fig. 6.
Resistance (mOhms)
Fig.
5
Electrical
analogy
of
system
losses.
25
20
15
10
5
V(Vds)/ I(V4) (mOhms)
0
0
5
10
15
20
25
30
35
40
45
50
240
60
220
50
200
40
180
30
160
o
70
IV. SIMPLE VOLTAGE CONTROLLED REACTIVE
MODELS
In this section, simple non-linear inductor and
capacitor SPICE model implementations are
described. These models are most suited when
device non-linear performance characteristics are
known, but their non-linear physical characteristics
are difficult to derive.
PSPICE includes in its ANL_MISC.LIB library a
5-terminal non-linear inductor model ZX (Fig. 7)
and a non-linear capacitor model YX. The ZX and
YX node definitions are listed in Tables IV and V.
Functional blocks from these library models were
recreated in Figs 8 and 10 using available PSPICE
symbols to facilitate the numerical derivation of the
library functions. Node numbers 1 through 5 are
marked to facilitate functional reference with the
existing PSPICE ZX and YX library files. Node 5
would normally be connected to a load.
With a device specific behavioral voltage source
model, the ZX and YX models can be made to
operate non-linearly with the use of voltage
dependent input nodes 1 and 2 which multiply the
voltage from node 3.
Temperature ( C)
Current (A)
Time (ms)
Instantaneous power dissipation information is
evaluated with ABM current source G8 by
multiplying the drain-source voltage with current
I(V4) flowing through the MOSFET resistance.
(Zero-volt source V4 is included to measure
current.) Case temperature is set with voltage source
Vcase. A more detailed system level thermal
impedance network could be implemented in place
of Vcase.
Instantaneous junction temperature
information Tjunction is the result from the closed
loop simulation.
20
140
10
I(I4) (A)
120
V(Tjunction) (C)
0
100
0
5
10
15
20
25
30
35
40
45
50
Time (ms)
Fig. 6 Simulation results.
The FDB8445 MOSFET thermal impedance
model is provided by an RC ladder network (R1-R6,
C1-C6). The MOSFET RDS(on) is modeled with a
voltage dependent current source ABM model G6.
Fig. 7 PSPICE ANL_MISC.LIB ZX Symbol
A. Non-Linear Inductance Model.
Power supply filter inductors and solenoid coil
inductance are examples of devices having nonlinear properties.
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Fairchild Power Seminar 2007
The equivalent schematic representation of the
non-linear inductance model ZX is shown in Fig. 8.
Model response to a sudden change of inductance
value is shown in Fig. 9. The simulation consists of
an AC voltage source connected in parallel to a nonlinear 1µH inductor having a series resistance of
0.01Ω. Rin is used to aid with convergence.
V4 = Vcontrol ⋅ V3
V4 = ( Vcontrol ⋅ Lref ) ⋅
(6)
d i Lref
dt
i Lref = i Rinductor
V4 = ( Vcontrol ⋅ Lref ) ⋅
(7)
(8)
d i Rinductor
dt
(9)
The simulated inductor voltage drop VL
corresponds to the total voltage drop between nodes
4a and 5 (to include winding resistance Rinductor).
VL = ( Vcontrol ⋅ Lref ) ⋅
d iRinductor
+ Rinductor ⋅ i Rinductor
dt
(10)
where
VL = voltage across the non-linear inductor
iRinductor = non-linear inductor current
0 < Vcontrol < 1.
B. Non-Linear Capacitor Model
Capacitor models that can be expressed using a
non-linear model include certain ceramic capacitor
types and MOSFET capacitance which have nonlinear voltage dependent properties.
The equivalent schematic representation of the
non-linear capacitor model YX is shown in Fig. 10.
Model response to a sudden change of capacitance
value is shown in Fig. 11. The simulation consists
of an AC voltage source connected in parallel to a
non-linear 1µF capacitor. Rin is used to aid with
convergence.
Fig. 8 Voltage-controlled inductance model.
TABLE IV
ZX MODEL NODE DEFINITION
1: control input voltage (+)
2: control input voltage (-)
3: reference inductor/resistor (connect other lead to ground)
4: output (floating impedance)
5: output (floating impedance)
Inductance ( µH)
1.25
1.00
0.75
L = 1µ H
Vcontrol = 1.0V
Vcontrol = 0.25V
0.50
L = 0.25µH
0.25
0.00
140
145
150
155
Voltage or Current
Time (µs)
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
140
145
150
Time (µs)
160
165
V(4a)/d(I(Rinductor)) (uH)
155
I(Rinductor) (A)
160
165
V(4a) (V)
Fig. 9 Voltage-controlled inductor model response.
Fig. 10 Voltage-controlled capacitor model YX.
When an inductor is energized, current cannot
change instantaneously. By Faraday’s law:
V3 = Lref ⋅
d i Lref
dt
(5)
By substitution (Fig. 8),
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Fairchild Power Seminar 2007
TABLE V
YX MODEL NODE DEFINITION
1: control input voltage (+)
2: control input voltage (-)
3: reference capacitor (connect other lead to ground)
4: output (floating impedance)
5: output (floating impedance)
achieve steady state information may also require
significant run-time.
Through the use of
characterization data selected under relevant
operating conditions, device behavioral models may
be prepared.
These models may then be used as building blocks
for complex topologies.
Capacitance (nF)
1200
1000
Vcontrol = 1.0V
800
600
Vcontrol = 0.25V
400
C = 0.25µH
C = 1µF
200
0
0
5
10
15
Time (µs)
20
25
(1/V(4))*S(I(Fcopy))
Voltage or Current
0.6
0.4
A. Complex Waveform Circuit
Application of modern high speed IGBTs in
SMPS circuits can provide cost and conduction loss
advantages.
In PFC circuits (Fig. 12), each
switching operation occurs at a different current and
duty cycle. IGBT losses (Fig. 13) are a non-linear
function of the collector current, collector voltage
and junction temperature. The loss plane represents
IGBT turn-off losses at a single clamp voltage (400
VDC).
0.2
IL1
VacABS
0.0
Vout
390Vdc
Boost Inductor
-0.2
D1
-0.4
Boost Diode
D2
VacInput
-0.6
0
5
10
15
Time (µs)
20
I(V2)
90 Vrms
50Hz
25
C1
IGBT
V(4)
D3
PFC Control
Circuit
D4
Fig. 11 Voltage-controlled capacitor model response.
Current Sense Resistor
Capacitor voltage may be expressed as
1
⋅ i Cref ⋅ d t
Cref
= iFCOPY
VCref =
i CREF
1
⋅ iFCOPY ⋅ d t
Cref
= Vcontrol ⋅ V4
VCref =
VCref
V4 =
∫
∫
1
⋅ iFCOPY ⋅ d t
Vcontrol ⋅ Cref
∫
Fig. 12 Boost PFC circuit block diagram.
(11)
Eoff (µ joules)
(12)
(13)
(14)
where
V4 = non-linear capacitor voltage
iFCOPY = non-linear capacitor current
0 < Vcontrol < 1
V. USING BEHAVIORAL MODELING FOR
COMPLEX WAVEFORM CIRCUITS
Evaluating device performance with nonrepetitive waveform topologies can be a daunting
task. In situations in which IGBT and diode losses
require accurate modeling, meaningful results may
be a difficult to obtain. Device models, if existent,
may have limited accuracy. Simulations required to
Tj (oC)
Icollector (amps)
Fig. 13 Three-dimensional Eoff plot.
A behavioral modeling technique for determining
losses and junction temperature of an IGBT
operating in a switched mode power circuit is
described. Full PFC circuit implementation in
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Fairchild Power Seminar 2007
closed loop form using behavioral modeling for
switching information, loss calculations and control
are described in detail in [2, 4]. The transistor
transient thermal impedance model is used within
this feedback loop.
B. Behavioral Model Equations
Techniques expressing empirical IGBT test data
into loss equations are described in [1]. The onstate voltage (VCE(sat)), turn-off loss (Eoff) and turnon loss (Eon) expressions are described in equations
(15)–(17) for typical performance of the
HGTG12N60A4D IGBT [3].
(
(
(
)
)
)
 a1 ⋅ Tj 2 + a2 ⋅ Tj + a3 ⋅ e a10 ⋅I + 


2
a11
Vsat (I,Tj ) =  a4 ⋅ Tj + a5 ⋅ Tj + a6 ⋅ I
+ 


 a7 ⋅ Tj 2 + a8 ⋅ Tj + a9

(
(15)
)
Eoff Vclamp ,I,Tj =
(b1 + b 2 ⋅ Tj ) ⋅ e b3⋅I + 
V


clamp
⋅ (b8 + b9 ⋅ I ) ⋅ (b 4 + b5 ⋅ Tj ) ⋅ I +

400


2
b6 ⋅ I + b7 ⋅ Tj

(16)
Eon (V , I , Tj ) =
c 10⋅Tj

+ c 4 ⋅ Tj + c 5 ⋅ I 2 
c1 ⋅ V c 9 + c 2 ⋅  c 3 ⋅ e

+ (c6 + c7 ⋅ Tj ) ⋅ I + c 8 ⋅ Tj

(
) (
)
(17)
Turn-off expression (16) and coefficients b1
through b7 correspond to IGBT performance in a
clamped inductive turn-off switching circuit.
Expression (17) describes the hard-switched Eon2
turn-on losses with the IGBT which includes losses
from an external diode (equivalent to that in the copackaged version of the IGBT) reverse recovery
current. The junction temperature of this external
diode is assumed to correspond to that of the copackaged HGT12N60A4D IGBT (a semiconductor
characterization practice).
The loss coefficients were developed using a 15V
IGBT gate drive waveform. These equations may
be used to represent other IGBT types by
developing a new set of coefficients [1].
The outputs of (16) and (17) are the IGBT turnoff and turn-on losses in joules per switching-cycle.
Coefficient values are provided in [3].
C. IGBT Behavioral Model Input Voltages and
Currents
To demonstrate the SPICE implementation of
(15)-(17), an HGTP12N60A4D IGBT behavioral
model was developed [2] using the Intusoft SPICE
simulator “B” function as shown in Fig. 14.
A basic sub-circuit avgIGBT was developed to
provide an effective means of adding additional
IGBT model types. The sub-circuit was designed to
receive six inputs and provide three outputs, all
referenced to Tcase. Two bi-directional terminals,
Tj and Zjc, provide a circuit interface to the IGBT's
thermal impedance model. A schematic symbol
avgIGBT was generated to provide a simple method
of implementing this component in a SPICE
schematic.
Model and symbol input are defined as:
Iton = Load current at IGBT turn-on
Ion
= Average IGBT collector current during
conduction
Itoff = Collector current at IGBT turn-off
Tj = IGBT and clamp diode junction temperature
Vton = IGBT collector voltage at turn-on
Vtoff = IGBT collector clamp voltage at turn-off
Output Eon represents the Eon2 turn-on energy
loss (J) for the Iton, Vton and Tj input values.
Output Eoff represents the turn-off energy loss (J)
for the Itoff, Vtoff and Tj input values. Output Vsat
is the saturated on-state voltage for the Ion and Tj
inputs. The IGBT’s junction to case thermal
impedance is represented as a multi-stage RC ladder
network internally connected between Zjc and
Tcase.
Whereas the Tj schematic-symbol terminal is
provided for open-loop simulation, the Zjc terminal
is used for closed-loop simulation by connecting it
to Tj and supplying this node with a current equal to
total IGBT losses (W). Because the thermal
impedance network is internally connected between
Zjc and Tcase, the voltage at terminal Zjc is equal to
the IGBT junction temperature (1V = 1oC) as long
as Tcase is set to a voltage equal to the case
temperature.
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Fairchild Power Seminar 2007
Icollector (amps)
Eon
7
21.0
Turn-On Loss (joules)
V(1)
635U
V(7)
-1.00
Tran 0
tim e
3.00
-20.5U
T ran
0
X2
HGTP12N60A4
Icollector
time
Eon
Iton
3.00
Turn-Off Loss (joules)
Ion
1
Eof f
V6
4
Eoff
6
Itof f
434U
V(6)
Tj
Vsat
Vton
Zjc
-18.7U
Tran
0
time
3.00
Tcase
Vtof f
Vsat
5
Tjunction
Vsat (volts)
2
127
V3
V5
390
V(2)
72.5
Tran 0
time
2.03
V(5)
621M
Tran 0
3.00
time
3.00
Tjunction (degrees C)
Fig. 14 Basic IGBT behavioral model avgIGBT.
X11
K1 = 1
K2 = -1
DC Output Voltage
Vout
X12
DIVIDE
K1
SUM2
Vout
390
Duty_Cy cle
A
4
DutyCycle
A/B
K2
B
Vrms Input
1V=1V
AC Input Voltage
VinABS
DUTY CYCLE
X17
ABS
VAC_IN
VinRMS
1.02
VacABS
Tran
657M
480M
time
500M
A
Vrms
90
ABS
K*A*B
39.1
IGBT Duty Cycle
B
V (5)
X10
MUL
K= 1
Vref
VacInput
-264M
Tran
480M
134
-6.36
V9
Tran
480M
1.4142 Vpeak
50Hz
X18
MUL
K= 1
X13
DIVIDE
time
500M
Switc hingFreq
X15
K1 = -0.5
K2 = 1
PktoPkRippleI
K1
Ion
Eoff_Joules
K*A*B
A/B
30
21
ABS
6
18
B
DutyCycle
PktoPkRippleI
X8
K1 = 1
K2 = 0.5
A
8.25
Tj
Vsat
Vton
Z jc
Vtoff
T case
B
22
ON_STATE_LOSS
K*A*B*C
C
OnStateWatts
Tjunc tion
Tj
Vout
113
V(18)
Pout
Vpout
500V
5
K3
X7
K1 = 1
K2 = 1
K3 = 1
X1
K= 1
VCE_ON
Itoff
36
K2
SUM3
EoffWatts
B
24
Eoff
B
AC Input Current
1 Volt per Amp
K*A*B
Eon
Iton
Ion
K1
SUM2
K2
A
X2
HGTP12N60A4
Itoff
G1
1
K1
K*A*B
B
17
500M
Total IGBT Losses
EonWatts
A
Eon_Joules
time
Turn_On_Loss
X6
TURN_OFF_LOSS
K= 1
K2
A
A
Iton
Vfreq
100kV
SUM2
X3
ABS
X5
K= 1
Sw itching Frequency
1 Volt/Hz
VA CABS
TJ
-393M
Tran
480M
Pow er Out
1V=1W
time
500M
104
Tran 480M
T_Case
Av erage On-State Current
1V/amp
PACKAGE 23
1.80
A
DutyCycle
RIPPLE_CURRENT
Tran
B
28
time
500M
Rsink _amb
1.15
T_Sink
V_Initial_Temp
110V
V6
Csink_amb
1
X25
X20
K= 1
1
42
A/B
K*A*B
SwitchingFreq
Pk toPkRippleI
A
A
15
VL1
500uV
-85.7M
480M
X9
SWITCH
26
45
K*A*B
Value of Boost Inductor
1V=1Henry
500M
Cc ase_sink
5.75E-1
Rcase_sink
.55
X19
K= 1
VacABS
time
Junction Temperature
9
Vamb
50Vdc
Ripple_Current
B
B
Ambient Temp
1V=1 degree C
Peak-to-Peak
Boost Inductor
Ripple Current
Fig. 15 PFC behavioral model implementation.
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Fairchild Power Seminar 2007
D. Behavioral Model Implementation
In Fig. 14, a 0 to 20V 1Hz ramp is applied to the
model Iton, Ion and Itoff terminals representing a 0
to 20A 1Hz collector current.
The junction
temperature is stepped from 75 to 150oC 1.5
seconds into the simulation while the turn-on (Vton)
and turn-off (Vtoff) voltages are maintained at
390V. Analysis of the wave shapes on the right side
of the schematic reveal the impact the current and
temperature changes have on the model outputs.
Fig. 15 illustrates a closed loop form
implementation of the behavioral model within a
power factor controller circuit.
Functional
description is provided in [2]
VI. DIODE REVERSE RECOVERY CURRENT
WAVEFORMS: ACCURACY LIMITATIONS
Diode reverse recovery current (IRM) is an included
function with each of Fairchild’s MOSFET PSPICE
models. It is modeled with a diode in PSPICE. The
simulated reverse recovery for the FDB8441 40V
2.5mΩ MOSFET [14] at 25oC for a slew rate of
100A/µs is shown in Fig. 16. Measured results are
shown in Fig. 17. Simulated reverse recovery time
trr is 50.5ns (di/dt = 100A/µs, 25oC) while the data
sheet typical is 52ns thus showing good agreement.
While it is accurate under data sheet conditions it
may not track over a wide range of operating
conditions.
Fig. 17 Measured FDB8441 diode reverse recovery waveform at 25oC,
100A/µs. The vertical scale is 5A per division.
A limitation of this diode model is that there is
little trr variation as a function of operating
conditions, and simulations at various forward
conduction currents show little change in the
reverse recovery waveform. For many real devices,
however, trr becomes significantly longer at higher
forward current, higher di/dt, and higher
temperature. Results are summarized in tables VI
and VII.
TABLE VI
DIODE REVERSE RECOVERY AT VARIOUS TEMPERATURES
ISD=20A, di/dt=100A/µs
Temp (°C)
25 simulated
25 measured
125 simulated
125 measured
25A
20A
Irm (A)
-3.40
-2.4
-3.27
-2.8
TABLE VII
SIMULATED DIODE REVERSE RECOVERY AT VARIOUS CURRENTS
15A
Temp=25°C, di/dt=100A/µs
10A
ISD (A)
15
35
50
75
5A
0A
-5A
1.95us
2.00us
I(X1:s)
Trr (ns)
50.50
56
49.44
58
2.05us
2.10us
2.15us
2.20us
2.25us
2.30us
Time
Fig. 16 Simulated FDB8441 diode reverse recovery waveform at 25oC,
100A/µs.
Trr (ns)
50.39
49.70
49.35
49.51
Qrr (nC)
81.70
81.14
80.57
80.73
Irm (A)
-3.45
-3.54
-3.53
-3.52
While these intrinsic body diode models provide
good results, it is important to be aware of their
limitations. In practice, the reverse recovery is
modeled under data sheet conditions.
These limitations are due to the diode models as
implemented in SPICE. The SPICE primitive diode
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model is limited in its ability to represent minority
charge concentration under operating conditions.
Therefore, all SPICE MOSFET intrinsic body
diodes and diode models will have these limitations
regardless of device manufacturer. Other simulators
(e.g. Saber) may overcome these problems but that
has not been explored at this time.
VII. CONVERGENCE ISSUES
There are many issues that can lead to simulation
convergence problems. Complexity of the circuit
being simulated can be a leading cause. As the
circuit becomes more complex there are more node
voltages and device currents that need to be
calculated. Not only can convergence be a problem,
but long run times can be a problem with highly
complex circuits. One solution here is to simplify
the circuit whenever possible. Can the circuit be
implemented with a simplified model instead of a
detailed complex model? For instance, if one is
only concerned with on-state circuit losses, a
MOSFET model could be replaced with an ABM
resistor model (previously described). The ABM
resistor would be modeled to describe the RDS(on) vs.
temperature characteristics of the MOSFET. This
ABM model could then replace the complex
MOSFET model.
Careful placement of large value resistors around
parasitic elements can help overcome convergence
issues. In circuits where layout parasitic elements
must be simulated, placing a 1MΩ in parallel with
parasitic capacitors or inductors is recommended.
OrCAD® recommends that all inductors have a
parallel resistor [5]. Doing so models eddy current
losses and bandwidth limitations of inductors at
high frequencies. (18) describes the recommended
parallel resistance value for a given inductance,
where fq is the roll-off frequency resulting from the
inductor’s interwinding capacitance.
R = 2π * f q * L
(18)
Simulation time and convergence may also be
improved by defining circuit initial conditions.
Both capacitors and inductors have initial condition
parameters that may be defined. By setting these
conditions to the expected operating values,
convergence can be greatly improved. Setting
proper initial conditions can also reduce the number
of cycles necessary to reach a steady state solution.
In some circumstances, a significant reduction in
simulation time to reach steady state may be
achieved.
Adjusting simulation tolerance settings can also
help. These can be set in the simulation profile
under the options tab shown in Fig. 18. DC
convergence problems can be reduced by selecting
the GMIN stepping option.
Fig. 18 PSPICE simulation profile.
Other frequently adjusted options are ABSTOL
and VNTOL. ABSTOL is the accuracy of currents.
In most circuits using power devices, accuracy
down to the default value 1pA is not required. This
can be set to 1µA to improve convergence and
simulation time with no noticeable degradation of
the simulation output. VNTOL is the accuracy of
voltages. The default value of 1µV is generally a
good setting. VNTOL can also be relaxed to
improve convergence.
Accuracy of charges is defined with CHGTOL.
Its default value of 0.01pC can be relaxed to 1.0pC
and give good simulation results.
Increasing the various iteration limits ITL1, ITL2
and ITL4 can also be helpful. Each of these can be
set to 150 for improved results with complex
circuits.
Perhaps the biggest improvement in simulation
and convergence can be realized by using
Fairchild’s new Bsim3 MOSFET models [13]. The
Bsim3 uses a greatly reduced sub circuit macro
model to represent the MOSFET. The previous
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generation Fairchild Semiconductor SPICE level 1
model has a component count of 36 compared to 14
used in the Bsim3. When running a simplified DCDC converter, simulation time was reduced by 52%.
simulation profile and select Configuration Files
tab and category Library as shown in Fig. 20.
VIII. MOSFET SYMBOL USAGE
Fairchild Semiconductor provides MOSFET
symbols for use in OrCAD® schematic capture
tools. A link to the symbol files can be found in [6].
The symbols files provided are for either OrCAD®
Capture or OrCAD® Schematic. The file should be
saved in the directory where model library files are
located.
From an open schematic, select the icon or menu
item to place a new part. The Place Part window is
shown in Fig. 19.
Fig. 20 Simulation settings menu.
Select the Browse button to locate the library file
containing the model to be simulated. Next select
the Add to Design button to make the model ready
for simulation.
If a different model is to be used at a later point
in time, not all of these steps are required. From the
schematic, simply change the name of the MOSFET
model. Then add the library file to the simulation
profile if this has not been previously added.
Alternatively, a library can be added globally to
Capture. When adding the library file to the
simulation profile shown in Fig. 20 select the Add
as Global button. This library file will then be
available for all designs in Capture.
Fig. 19 Place Part menu.
In this window select Add Library. Browse to
and open the symbol file that was downloaded, and
saved to the working directory. From this new
library, select the symbol Fairchild MOS Std and
place into schematic. Once the MOSFET symbol
has been placed the model name will need to be
changed. Double click Fairchild MOSFET on
symbol just placed and enter the model name to be
simulated.
The final step is to add the library to the
simulation profile.
Within Capture open a
IX. FAIRCHILD SEMICONDUCTOR ON-LINE TOOLS
FETBench® is a Fairchild Semiconductor SPICE
based design aide that helps designers shorten
design times and reduce time to market. This
design tool incorporates a wide range of Fairchild
low-voltage MOSFETs targeting computing and
ultra-portable applications. FETBench® can save,
recall and share design simulations. MOSFET
models are based on Berkeley SPICE BSIM3
version 3.1 device models, offering broad simulator
compatibility. This tool (Fig. 21) may be found online [7].
Design activity may be saved for future use. Key
FETBench features include:
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- MOSFET device selection
- Application analysis
- Thermal simulation
B. Application Analysis Module
Applications analysis along with device selection
is made within this module. Key features include:
- Circuit selection
i. Synchronous rectifier buck
ii. Synchronous rectifier buck
with FAN5236 controller
iii. Boost converter
iv. Load switch
v. Bi-directional load switch
- Input and output requirement definitions.
- Device selections (device combinations
may are permissible)
Fig. 21 Web site FETBench menus
A. Device Analysis Module
This module offers a search capability based on
either prior knowledge of an existing device of
interest, or on required parametric characteristics.
(While this search is limited to MOSFETs suitable
for computing and ultra-portable applications, all
Fairchild MOSFETs may be searched by selecting
“MOSFETs” on the Fairchild home page.) Once a
device has been selected, a device analysis menu
can perform a number of types of analysis. This
module offers:
- In-circuit device analysis
C. Thermal Analysis Module
Once inputs to the Application Analysis Module
have been completed and the average power
dissipation in each device of interest has been
determined, a thermal analysis may be performed
with the use of the Thermal Analysis module (Fig.
22). Key features include:
- Curve Tracer Analysis
i. ID vs VDS (vary VGS, TJ)
ii. RDS(on) vs ID (vary VGS, TJ)
iii. Gate charge vs VGS (vary VDS)
iv. RDS(on) vs VGS (vary ID, TJ)
v. Reverse conduction characteristics ID
vs VDS (vary VGS)
- Dynamic Characteristics
Fig. 22 Example FETBench thermal analysis menus
i. Switching characteristics
- Definition of the thermal environment
ii. Reverse recovery characteristics
- Definition of the multilayer PCB design
- Definition of airflow
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- Placement
components.
of
power
dissipating
X. SUMMARY
Electrical and thermal simulation models as well as
behavioral models are useful tools in the hands of
the design engineer to gain further design insight.
Understanding methods to model real device
characteristics not captured in the basic models,
plus methods to improve simulation convergence,
can increase the value of simulation in the design
process. Ultimately improved design robustness
can be achieved.
REFERENCES
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
R. H. Randall, A. Laprade, B. Wood "Characterizing IGBT Switching
Losses for Switched Mode Circuits", PCIM Europe 2000, pp. 269-275,
June 2000.
R. H. Randall, A. Laprade, A. Craig, "Analyzing IGBT Losses by
Translating Empirical Data Into SPICE Behavioral Models", PCIM
Europe 2000, pp. 263-268, June 2000.
Fairchild Semiconductor Corporation, Mountaintop, PA, Data Sheet
HGTP12N60A4D, http://www.fairchildsemi.com.
R. H. Randall, A. Laprade, “Behavioral Model Analyzes IGBT Losses in
Sinusoidal Circuits“ PCIM Europe 2001, pp. 165-170, June 2001.
“Exploring the Nature of Spice Convergence Problems”, OrCAD Design
Network, 5/99.
http://www.fairchildsemi.com/models/PSPICE/Discrete/MOSFET.html
http://www.fairchildsemi.com/designcenter/index.html
http://www.transim.com/fairchild/index.html
http://www.fairchildsemi.com/whats_new/spm_tool.html
http://www.fairchildsemi.com/whats_new/offline_smps_toolkit.html
http://www.fairchildsemi.com/whats_new/pfc_toolkit.html
Fairchild Semiconductor Corporation, Mountaintop, PA, Data Sheet
FDB8445, http://www.fairchildsemi.com.
http://www.fairchildsemi.com/models/Pspice_Bsim3.1/Discrete/MOSF
ET.html
Fairchild Semiconductor Corporation, Mountaintop, PA, Data Sheet
FDB8441, http://www.fairchildsemi.com.
http://www.systat.com/products/TableCurve2D/
Scott Pearson has worked in the semiconductor industry
for the past 17 years. For the past 12 years Scott has
been involved in MOSFET characterization, testing and
Spice modeling.
He has been with Fairchild
Semiconductor since May 1989. Scott obtained his B.
Eng. from Penn State University.
Alain Laprade has worked as a power supply designer
for 14 years in applications including computer power,
high power telecommunications and space designs. He
has been with Fairchild Semiconductor Corporation since
February 1998 working in industrial, cell phone and
automotive applications. Alain obtained his B.Eng. from
McGill University in 1982 and his M.Eng. from McGill
University in 1984.
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