a
FEATURES
Recovers Signal from 100 dB Noise
2 MHz Channel Bandwidth
45 V/ ␮ s Slew Rate
–120 dB Crosstalk @ 1 kHz
Pin Programmable, Closed-Loop Gains of ⴞ 1 and ⴞ 2
0.05% Closed-Loop Gain Accuracy and Match
100 ␮ V Channel Offset Voltage (AD630BD)
350 kHz Full Power Bandwidth
Chips Available
PRODUCT DESCRIPTION
The AD630 is a high precision balanced modulator that combines a flexible commutating architecture with the accuracy and temperature stability afforded by laser wafer trimmed thin film resistors. Its signal processing applications include balanced modulation and demodulation, synchronous detection, phase detection, quadrature detection, phase-sensitive detection, lock-in amplification, and square wave multiplication. A network of on-board applications resistors provides precision closed-loop gains of
±
1 and
±
2 with 0.05% accuracy (AD630B). These resistors may also be used to accurately configure multiplexer gains of +1, +2, +3, or +4. Alternatively, external feedback may be employed, allowing the designer to implement high gain or complex switched feedback topologies.
The AD630 can be thought of as a precision op amp with two independent differential input stages and a precision comparator that is used to select the active front end. The rapid response time of this comparator coupled with the high slew rate and fast settling of the linear amplifiers minimize switching distortion. In addition, the AD630 has extremely low crosstalk between channels of –100 dB @ 10 kHz.
The AD630 is used in precision signal processing and instrumentation applications that require wide dynamic range. When used as a synchronous demodulator in a lock-in amplifier configuration, it can recover a small signal from 100 dB of interfering noise (see Lock-In Amplifier Applications section). Although optimized for operation up to 1 kHz, the circuit is useful at frequencies up to several hundred kilohertz.
Other features of the AD630 include pin programmable frequency compensation, optional input bias current compensation resistors, common-mode and differential-offset voltage adjustment, and a channel status output that indicates which of the two differential inputs is active. This device is now available to
Standard Military Drawing (DESC) numbers 5962-8980701RA and 5962-89807012A.
FUNCTIONAL BLOCK DIAGRAM
R
IN
A 1
2.5k
⍀
CM OFF
ADJ
6
AMP A
CM OFF
ADJ
5
CH A+
CH A–
2
20
R
IN
B 17
2.5k
⍀
AMP B
A
B
CH B+ 18
CH B– 19
SEL B 9
SEL A 10
COMP
DIFF OFF
ADJ
4
DIFF OFF
ADJ
3
–V
AD630
10k ⍀
12
11
COMP
+V
S
13 V
OUT
10k
⍀
14 R
B
5k ⍀
15 R
F
16
7
R
A
CHANNEL
STATUS
B/A
8
–V
S
PRODUCT HIGHLIGHTS
1. The configuration of the AD630 makes it ideal for signal processing applications, such as balanced modulation and demodulation, lock-in amplification, phase detection, and square wave multiplication.
2. The application flexibility of the AD630 makes it the best choice for applications that require precisely fixed gain, switched gain, multiplexing, integrating-switching functions, and high speed precision amplification.
3. The 100 dB dynamic range of the AD630 exceeds that of any hybrid or IC balanced modulator/demodulator and is comparable to that of costly signal processing instruments.
4. The op amp format of the AD630 ensures easy implementation of high gain or complex switched feedback functions.
The application resistors facilitate the implementation of most common applications with no additional parts.
5. The AD630 can be used as a 2-channel multiplexer with gains of +1, +2, +3, or +4. The channel separation of
100 dB @ 10 kHz approaches the limit achievable with an empty IC package.
6. The AD630 has pin strappable frequency compensation (no external capacitor required) for stable operation at unity gain without sacrificing dynamic performance at higher gains.
7. Laser trimming of comparator and amplifying channel offsets eliminates the need for external nulling in most cases.
REV. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved.

AD630
Last content update 05/03/2013 01:15 pm
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(@ 25 ⴗ C and ⴞ V
S
= ⴞ 15 V, unless otherwise noted.)
AD630J/AD630A
Min Typ Max
AD630K/AD630B
Min Typ Max Min Model
GAIN
Open-Loop Gain
±
1,
±
2 Closed-Loop Gain Error
Closed-Loop Gain Match
Closed-Loop Gain Drift
CHANNEL INPUTS
V
IN
Operational Limit 1
Input Offset Voltage
Input Offset Voltage
T
MIN
to T
MAX
Input Bias Current
Input Offset Current
Channel Separation @ 10 kHz
COMPARATOR
V
IN
Operational Limit
1
Switching Window
Switching Window
T
MIN
to T
MAX
Input Bias Current
Response Time (–5 mV to +5 mV Step)
Channel Status
I
SINK
@ V
OL
= –V
S
+ 0.4 V
2
Pull-Up Voltage
DYNAMIC PERFORMANCE
Unity Gain Bandwidth
Slew Rate 3
Settling Time to 0.1% (20 V Step)
OPERATING CHARACTERISTICS
Common-Mode Rejection
Power Supply Rejection
Supply Voltage Range
Supply Current
OUTPUT VOLTAGE, @ R
L
= 2 k
Ω
T
MIN
to T
MAX
Output Short-Circuit Current
TEMPERATURE RANGES
Rated Performance–N Package
Rated Performance– D Package
90
(–V
S
+ 4 V) to (+V
S
– 1 V)
500
1.6
85
90
±
5
±
10
0
–25
2
45
3
110
0.1
0.1
2
800
100 300
10 50
100
±
2.0
100 300
200
105
110
4
25
(–V
S
+ 33 V)
±
16.5
5
70
+85
100 120
2
0.05
0.05
(–V
S
+ 4 V) to (+V
S
– 1 V)
100
1.6
90
90
±
5
±
10
0
–25
100
200
2
45
3
100
10
100
110
110
4
25
160
300
50
(–V
S
+ 3 V) to (+V
S
±
1.5
– 1.5 V) (–V
S
+ 3 V) to (+V
S
– 1.5 V)
±
1.5
±
2.0
300
(–V
S
+ 33 V)
±
16.5
5
70
+85
90
(–V
S
+ 4 V) to (+V
S
– 1 V)
500
1000
300
50
(–V
S
+ 3 V) to (+V
S
– 1.3 V)
±
1.5
1.6
90
90
±
5
±
10
–55
AD630S
Typ Max
100
200
2
45
3
110
0.1
0.1
2
100
10
100
110
110
4
25
N/A
±
2.5
300 mA
(–V
S
+ 33 V) V
±
16.5
5
+125
Unit
V
µ
V
µ
V nA nA dB dB
%
% ppm/
°
C
V mV mV nA ns
MHz
V/
µ s
µ s dB dB
V mA
V mA
°
C
°
C
NOTES
1
If one terminal of each differential channel or comparator input is kept within these limits the other terminal may be taken to the positive supply.
2
3
I
SINK
@ V
OL
= (–V
S
+ 1); V is typically 4 mA.
Pin 12 Open. Slew rate with Pin 12 and Pin 13 shorted is typically 35 V/
µ s.
Specifications subject to change without notice.
–2– REV. E

AD630
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . 600 mW
Output Short-Circuit to Ground . . . . . . . . . . . . . . . Indefinite
Storage Temperature, Ceramic Package . . . –65
°
C to +150
°
C
Storage Temperature, Plastic Package . . . . . –55 ° C to +125 ° C
Lead Temperature Range (Soldering, 10 sec) . . . . . . . . 300
°
C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150 ° C
ORDERING GUIDE
THERMAL CHARACTERISTICS
␪
JC
␪
JA
20-Lead PDIP (N)
20-Lead Ceramic DIP (D)
20-Lead SOIC (R-20)
24 ° C/W 61 ° C/W
35
°
C/W 120
°
C/W
20-Lead Leadless Chip Carrier LCC (E) 35
°
C/W 120
°
C/W
38
°
C/W 75
°
C/W
Model Temperature Ranges
AD630JN
AD630KN
0 ° C to 70 ° C
0
°
C to 70
°
C
AD630AR –25 ° C to +85 ° C
AD630AR-REEL –25
°
C to +85
°
C
AD630AD
AD630BD
AD630SD
AD630JCHIPS
AD630SCHIPS
–25 ° C to +85 ° C
–25
°
C to +85
°
C
–55 ° C to +125 ° C
–55
°
C to +125
°
C AD630SD/883B
5962-8980701RA –55 ° C to +125 ° C
AD630SE/883B –55
°
C to +125
°
C
5962-89807012A –55 ° C to +125 ° C
0
°
C to 70
°
C
–55 ° C to +125 ° C
Package Description Package Option
PDIP
PDIP
SOIC
N-20
N-20
R-20
SOIC 13" Tape and Reel R-20
SBDIP D-20
SBDIP
SBDIP
D-20
D-20
SBDIP
SBDIP
CLCC
CLCC
Chip
Chip
D-20
D-20
E-20A
E-20A
CHIP METALLIZATION AND PINOUT
Dimensions shown in inches and (millimeters).
Contact factory for latest dimensions.
PIN CONFIGURATIONS
20-Lead SOIC, PDIP, and CERDIP
R
IN
A 1
CH A+ 2
20 CH A–
DIFF OFF ADJ 3
19 CH B–
18 CH B+
DIFF OFF ADJ
CM OFF ADJ
CM OFF ADJ
CHANNEL STATUS B/ A
–V
S
8
SEL B
9
4
5
6
7
17 R
IN
B
AD630
16 R
A
TOP VIEW
(Not to Scale)
15 R
F
14 R
B
13
V
OUT
12 COMP
SEL A 10 11 +V
S
20-Terminal CLCC
CHIP AVAILABILITY
The AD630 is available in laser trimmed, passivated chip form. The figure above shows the AD630 metallization pattern, bonding pads and dimensions. AD630 chips are available; consult factory for details.
DIFF OFF ADJ 4
CM OFF ADJ 5
CM OFF ADJ 6
CHANNEL STATUS B/A 7
–V
S
8
3 2 1 20 19
AD630
TOP VIEW
(Not to Scale)
18 CH B+
17 R
IN
B
16
15
14
R
A
R
F
R
B
9 10 11 12 13
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD630 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. E –3–

15 15
10
R
L
=
2k ⍀
C
L
= 100pF
V i
5k ⍀ 5k ⍀
5
2k
⍀
V
O
100pF
0
1k 10k 100k
FREQUENCY (Hz)
1M
TPC 1. Output Voltage vs. Frequency
C
L
= 100pF
f = 1kHz
10
5
V i
5k
⍀
5k
⍀
R
L
CAP IN
V
O
100pF
0
1 10 100 1k 10k 100k 1M
RESISTIVE LOAD ( ⍀ )
TPC 2. Output Voltage vs. Resistive
Load
120
100
40
20
80
60
0
1 10 100 1k 10k
FREQUENCY (Hz)
100k
TPC 4. Common-Mode Rejection vs. Frequency
–20
–40
20
0
60
40
UNCOMPENSATED
COMPENSATED
–60
–5 –4
TPC 5.
–3 –2 –1 0 1 2 3 4 dV
O
INPUT VOLTAGE (V)
vs. Input Voltage dt
5
18
15 V i
5k ⍀ 5k ⍀
2k ⍀
10
V
O
100pF
5
f = 1kHz
C
L
= 100pF
0
0 5 10 15
SUPPLY VOLTAGE ( ⴞ V)
TPC 3. Output Voltage Swing vs.
Supply Voltage
120
100
80
UNCOMPENSATED
0
45
60
40
20
COMPENSATED
90
135
0
0 10 100 1k 10k 100k
FREQUENCY (Hz)
1M
180
10M
TPC 6. Gain and Phase vs. Frequency

20mV/DIV
(V o
)
100
90
20mV
20mV/DIV
(V i
)
10
0%
20mV
TOP TRACE: Vo
BOTTOM TRACE: Vi
500ns
16
5k
⍀
15
2
20
19
18
V i
10k ⍀
14
9
10
CH A
CH B
10k
⍀
12
13
V
O
TPC 7. Channel-to-Channel Switch-Settling Characteristic
50mV 1mV
50mV/DIV
(V i
)
100
90
1mV/DIV
(A)
100mV/DIV
(V o
)
10
0%
100mV 500ns
TOP TRACE: Vi
MIDDLE TRACE: SETTLING
ERROR (A)
BOTTOM TRACE: Vo
V i
TOP
TRACE
10k ⍀
14
10k ⍀
15 20
2
CH A
12
13
1k ⍀
MIDDLE
TRACE
(A)
30pF
TEKTRONIX
7A13
V
O
BOTTOM
10k ⍀
TRACE
10k ⍀
TPC 8. Small Signal Noninverting Step Response
10V 1mV 5 ␮ s ⴞ 10V 20kHz
(V i
)
100
90
1mV/DIV
(B)
10V/DIV
(V o
)
10
0%
10V
TOP TRACE: Vi
MIDDLE TRACE: SETTLING
ERROR (B)
BOTTOM TRACE: Vo
V i
TOP
TRACE
14
10k ⍀
15
10k ⍀
20
2
CH A
12
13
10k ⍀
HP5082-2811
10k ⍀
V
O
BOTTOM
TRACE
(B)
MIDDLE
TRACE
AD630
TPC 9. Large Signal Inverting Step Response
REV. E –5–

AD630
TWO WAYS TO LOOK AT THE AD630
The functional block diagram of the AD630 (see page 1) shows the pin connections of the internal functions. An alternative architectural diagram is shown in Figure 1. In this diagram, the individual A and B channel preamps, the switch, and the integrator output amplifier are combined in a single op amp. This amplifier has two differential input channels, only one of which is active at a time.
+V
S
11 15
16
SEL B 9
SEL A 10
1
2
20
19
18
17
R
A
5k ⍀
2.5k
⍀
2.5k
⍀
A
B
R
B
10k ⍀
R
F
10k ⍀
14
13
12
7 B/A
8
–V
S
Figure 1. Architectural Block Diagram
HOW THE AD630 WORKS
The basic mode of operation of the AD630 may be easier to recognize as two fixed gain stages which can be inserted into the signal path under the control of a sensitive voltage comparator. When the circuit is switched between inverting and noninverting gain, it provides the basic modulation/demodulation function. The AD630 is unique in that it includes laser wafer trimmed thin-film feedback resistors on the monolithic chip. The configuration shown in
Figure 2 yields a gain of
±
2 and can be easily changed to
±
1 by shifting R
B
from its ground connection to the output.
The comparator selects one of the two input stages to complete an operational feedback connection around the AD630. The deselected input is off and has a negligible effect on the operation.
V i
16
R
A
5k ⍀
15
2
20
19
18
A
B R
B
10k ⍀
14
9
10
R
F
10k ⍀
13
V
O
Figure 2. AD630 Symmetric Gain ( ± 2)
When Channel B is selected, the resistors R
A
and R
F
are connected for inverting feedback as shown in the inverting gain configuration diagram in Figure 3. The amplifier has sufficient loop gain to minimize the loading effect of R
B
at the virtual ground produced by the feedback connection. When the sign of the comparator input is reversed, Input B will be deselected and A will be selected. The new equivalent circuit will be the noninverting gain configuration shown in Figure 4. In this case, R
A
will appear across the op amp input terminals, but since the amplifier drives this difference voltage to zero, the closed-loop gain is unaffected.
The two closed-loop gain magnitudes will be equal when R
F
/R
A
= 1 + R
F
/R
B
, which will result from making R
A
equal to R
F
R
B
/
(R
F
+ R
B
) the parallel equivalent resistance of R
F
and R
B
.
The 5 k
Ω
and the two 10 k
Ω
resistors on the AD630 chip can be used to make a gain of 2 as shown below. By paralleling the 10 k
Ω
resistors to make R
F
equal to 5 k
Ω
and omitting R
B
, the circuit can be programmed for a gain of
±
1 (as shown in
Figure 9a). These and other configurations using the on-chip resistors present the inverting inputs with a 2.5 k Ω source impedance. The more complete AD630 diagrams show 2.5 k Ω resistors available at the noninverting inputs which can be conveniently used to minimize errors resulting from input bias currents.
R
F
10k ⍀
V i
R
A
5k ⍀
R
B
10k
⍀ V
O
= –
R
F
R
A
V i
V i
Figure 3. Inverting Gain Configuration
R
A
5k
⍀
R
B
10k ⍀
R
F
10k ⍀
V
O
=
(
1+
R
F
)
V i
R
B
–6–
Figure 4. Noninverting Gain Configuration
CIRCUIT DESCRIPTION
The simplified schematic of the AD630 is shown in Figure 5.
It has been subdivided into three major sections, the comparator, the two input stages, and the output integrator. The comparator consists of a front end made up of Q52 and Q53, a flip-flop load formed by Q3 and Q4, and two current steering switching cells Q28, Q29 and Q30, Q31. This structure is designed so that a differential input voltage greater than 1.5 mV in magnitude applied to the comparator inputs will completely select one of the switching cells. The sign of this input voltage determines which of the two switching cells is selected.
CH A–
20
+V
S
11 i
55
SEL A
10 Q52 Q53
Q33
Q62
9
SEL B
Q3 Q4
Q28 i
22
CH A+
2
CH B+
19
CH B–
18
Q34
Q30
Q29
Q65
Q31
Q35 Q36 i
73
Q67
Q24
Q44
Q70
13 V
OUT
Q74
C121
C122
Q32
Q25
12
COMP i
23
–V
S
8
3
DIFF
OFF ADJ
4
DIFF
OFF ADJ
5
CM
OFF ADJ
6
CM
OFF ADJ
Figure 5. AD630 Simplified Schematic
REV. E

The collectors of each switching cell connect to an input transconductance stage. The selected cell conveys bias currents i
22 and i
23
to the input stage it controls, causing it to become active.
The deselected cell blocks the bias to its input stage which, as a consequence, remains off.
The structure of the transconductance stages is such that it presents a high impedance at its input terminals and draws no bias current when deselected. The deselected input does not interfere with the operation of the selected input ensuring maximum channel separation.
Another feature of the input structure is that it enhances the slew rate of the circuit. The current output of the active stage follows a quasi-hyperbolic-sine relationship to the differential input voltage. This means that the greater the input voltage, the harder this stage will drive the output integrator, and the faster the output signal will move. This feature helps ensure rapid, symmetric settling when switching between inverting and noninverting closed loop configurations.
The output section of the AD630 includes a current mirrorload (Q24 and Q25), an integrator-voltage gain stage (Q32), and a complementary output buffer (Q44 and Q74). The outputs of both transconductance stages are connected in parallel to the current mirror. Since the deselected input stage produces no output current and presents a high impedance at its outputs, there is no conflict. The current mirror translates the differential output current from the active input transconductance amplifier into single-ended form for the output integrator. The complementary output driver then buffers the integrator output to produce a low impedance output.
OTHER GAIN CONFIGURATIONS
Many applications require switched gains other than the ± 1 and
±
2 which the self-contained applications resistors provide. The
AD630 can be readily programmed with three external resistors over a wide range of positive and negative gain by selecting and
R
B
and R
F
to give the noninverting gain 1 + R
F
/R
B
and subsequent
R
A
to give the desired inverting gain. Note that when the inverting magnitude equals the noninverting magnitude, the value of R
A
is found to be R
B
R
F
/(R
B
+ R
F
). That is, R
A
should equal the parallel combination of R
B
and R
F
to match positive and negative gain.
The feedback synthesis of the AD630 may also include reactive impedance. The gain magnitudes will match at all frequencies if the A impedance is made to equal the parallel combination of the B and F impedances. The same considerations apply to the
AD630 as to conventional op amp feedback circuits. Virtually any function that can be realized with simple noninverting “L network” feedback can be used with the AD630. A common arrangement is shown in Figure 6. The low frequency gain of this circuit is 10. The response will have a pole (–3 dB) at a frequency f
⯝
1/(2
π
100 k
Ω
C) and a zero (3 dB from the high frequency asymptote) at about 10 times this frequency. The
2 k Ω resistor in series with each capacitor mitigates the loading effect on circuitry driving this circuit, eliminates stability problems, and has a minor effect on the pole-zero locations.
As a result of the reactive feedback, the high frequency components of the switched input signal will be transmitted at unity gain while the low frequency components will be amplified. This arrangement is useful in demodulators and lock-in amplifiers. It increases the circuit dynamic range when the modulation or interference is substantially larger than the desired signal amplitude. The output signal will contain the
REV. E –7–
AD630 desired signal multiplied by the low frequency gain (which may be several hundred for large feedback ratios) with the switching signal and interference superimposed at unity gain.
C
2k ⍀
10k ⍀
2k ⍀
100k ⍀
C
V i
2
20
19
18
A
B 12
13
V
O
11.11k
⍀
SEL B
SEL A
9
10
7
8
–V
S
CHANNEL
STATUS
B/
A
Figure 6. AD630 with External Feedback
SWITCHED INPUT IMPEDANCE
The noninverting mode of operation is a high input impedance configuration while the inverting mode is a low input impedance configuration. This means that the input impedance of the circuit undergoes an abrupt change as the gain is switched under control of the comparator. If gain is switched when the input signal is not zero, as it is in many practical cases, a transient will be delivered to the circuitry driving the AD630. In most applications, this will require the AD630 circuit to be driven by a low impedance source which remains “stiff ” at high frequencies. Generally, this will be a wideband buffer amplifier.
FREQUENCY COMPENSATION
The AD630 combines the convenience of internal frequency compensation with the flexibility of external compensation by means of an optional self-contained compensation capacitor.
In gain of ± 2 applications, the noise gain that must be addressed for stability purposes is actually 4. In this circumstance, the phase margin of the loop will be on the order of 60
°
without the optional compensation. This condition provides the maximum bandwidth and slew rate for closed loop gains of |2| and above.
When the AD630 is used as a multiplexer, or in other configurations where one or both inputs are connected for unity gain feedback, the phase margin will be reduced to less than 20
°
.
This may be acceptable in applications where fast slewing is a first priority, but the transient response will not be optimum.
For these applications, the self-contained compensation capacitor may be added by connecting Pin 12 to Pin 13. This connection reduces the closed-loop bandwidth somewhat and improves the phase margin.
For intermediate conditions, such as gain of ± 1 where loop attenuation is 2, use of the compensation should be determined by whether bandwidth or settling response must be optimized.
The optional compensation should also be used when the AD630 is driving capacitive loads or whenever conservative frequency compensation is desired.
OFFSET VOLTAGE NULLING
The offset voltages of both input stages and the comparator have been pretrimmed so that external trimming will only be required in the most demanding applications. The offset adjustment of the two input channels is accomplished by means of a differential and common-mode scheme. This facilitates fine adjustment of system errors in switched gain applications. With

AD630 the system input tied to 0 V, and a switching or carrier waveform applied to the comparator, a low level square wave will appear at the output. The differential offset adjustment potentiometers can be used to null the amplitude of this square wave
(Pins 3 and 4). The common-mode offset adjustment can be used to zero the residual dc output voltage (Pins 5 and 6).
These functions should be implemented using 10k trim potentiometers with wipers connected directly to Pin 8 as shown in
Figures 9a and 9b.
CHANNEL STATUS OUTPUT
The channel status output, Pin 7, is an open collector output referenced to –V
S
that can be used to indicate which of the two input channels is active. The output will be active (pulled low) when Channel A is selected. This output can also be used to supply positive feedback around the comparator. This produces hysteresis which serves to increase noise immunity. Figure 7 shows an example of how hysteresis may be implemented. Note that the feedback signal is applied to the inverting (–) terminal of the comparator to achieve positive feedback. This is because the open collector channel status output inverts the output sense of the internal comparator.
10
9
100 ⍀
1M ⍀
+5V
100k ⍀
100k ⍀
7
8
–15V
AD630 when used to modulate a 100 kHz square wave carrier with a 10 kHz sinusoid. The result is the double sideband suppressed carrier waveform.
These balanced modulator topologies accept two inputs, a signal
(or modulation) input applied to the amplifying channels and a reference (or carrier) input applied to the comparator.
MODULATION
INPUT
CARRIER
INPUT
10k
⍀
CM
ADJ
6
1
2.5k
⍀
2
AMP A
A
5
20
17
2.5k
⍀
18
B
AMP B
19
COMP
9
10
10k
⍀
DIFF
ADJ
4 3
–V
10k
⍀
AD630
14
10k
⍀
15
5k
⍀
16
7
12
11
13
8
+V
S
MODULATED
OUTPUT
SIGNAL
–V
S
Figure 9a. AD630 Configured as a Gain-of-One Balanced
Modulator
Figure 7. Comparator Hysteresis
The channel status output may be interfaced with TTL inputs as shown in Figure 8. This circuit provides appropriate level shifting from the open-collector AD630 channel status output to
TTL inputs.
+5V
+15V
AD630
100k ⍀
7
6.8k
⍀
2N2222
22k ⍀
IN 914s
TTL INPUT
8
–15V
Figure 8. Channel Status—TTL Interface
APPLICATIONS: BALANCED MODULATOR
Perhaps the most commonly used configuration of the AD630 is the balanced modulator. The application resistors provide precise symmetric gains of
±
1 and
±
2. The
±
1 arrangement is shown in
Figure 9a and the ± 2 arrangement is shown in Figure 9b. These cases differ only in the connection of the 10 k Ω feedback resistor
(Pin 14) and the compensation capacitor (Pin 12). Note the use of the 2.5 k
Ω
bias current compensation resistors in these examples. These resistors perform the identical function in the
± 1 gain case. Figure 10 demonstrates the performance of the
MODULATION
INPUT
CARRIER
INPUT
10k
⍀
CM
ADJ
6
1
2.5k
⍀
2
AMP A
A
5
20
17
2.5k
⍀
18
B
AMP B
19
COMP
9
10
10k
⍀
DIFF
ADJ
4 3
–V
10k
⍀
AD630
14
10k ⍀
15
5k
⍀
16
7
12
11
13
8
+V
S
MODULATED
OUTPUT
SIGNAL
–V
S
Figure 9b. AD630 Configured as a Gain-of-Two Balanced
Modulator
5V 5V 20
␮ s
MODULATION
INPUT
CARRIER
INPUT
OUTPUT
SIGNAL
10V
Figure 10. Gain-of-Two Balanced Modulator Sample
Waveforms
–8– REV. E

BALANCED DEMODULATOR
The balanced modulator topology described above will also act as a balanced demodulator if a double sideband suppressed carrier waveform is applied to the signal input and the carrier signal is applied to the reference input. The output under these circumstances will be the baseband modulation signal. Higher order carrier components that can be removed with a low-pass filter will also be present. Other names for this function are synchronous demodulation and phase-sensitive detection.
PRECISION PHASE COMPARATOR
The balanced modulator topologies of Figures 9a and 9b can also be used as precision phase comparators. In this case, an ac waveform of a particular frequency is applied to the signal input and a waveform of the same frequency is applied to the reference input. The dc level of the output (obtained by low-pass filtering) will be proportional to the signal amplitude and phase difference between the input signals. If the signal amplitude is held constant, the output can be used as a direct indication of the phase. When these input signals are 90
°
out of phase, they are said to be in quadrature and the AD630 dc output will be zero.
PRECISION RECTIFIER ABSOLUTE VALUE
If the input signal is used as its own reference in the balanced modulator topologies, the AD630 will act as a precision rectifier. The high frequency performance will be superior to that which can be achieved with diode feedback and op amps. There are no diode drops that the op amp must “leap over” with the commutating amplifier.
LVDT SIGNAL CONDITIONER
Many transducers function by modulating an ac carrier. A linear variable differential transformer (LVDT) is a transducer of this type. The amplitude of the output signal corresponds to core displacement. Figure 11 shows an accurate synchronous demodulation system which can be used to produce a dc voltage that corresponds to the LVDT core position. The inherent precision and temperature stability of the AD630 reduce demodulator drift to a second-order effect.
AD630
2.5kH
Z
2V p-p
SINUSOIDAL
EXCITATION
E1000
SCHAEVITZ
A
LVDT
AD544
FOLLOWER
16 B
5k ⍀
1 ⴞ
2.5k
⍀
15
AD630
2 DEMODULATOR
10k ⍀
A
14
17
10k ⍀
20
19
B
12
C
13
100k ⍀
1 ␮ F
2.5k
⍀
D
PHASE
SHIFTER
9
10
Figure 11. LVDT Signal Conditioner
AC BRIDGE
Bridge circuits that use dc excitation are often plagued by errors caused by thermocouple effects, 1/f noise, dc drifts in the electronics, and line noise pick-up. One way to get around these problems is to excite the bridge with an ac waveform, amplify the bridge output with an ac amplifier, and synchronously demodulate the resulting signal. The ac phase and amplitude information from the bridge is recovered as a dc signal at the output of the synchronous demodulator. The low frequency system noise, dc drifts, and demodulator noise all get mixed to the carrier frequency and can be removed by means of a low-pass filter.
Dynamic response of the bridge must be traded off against the amount of attenuation required to adequately suppress these residual carrier components in the selection of the filter.
Figure 12 is an example of an ac bridge system with the AD630 used as a synchronous demodulator. The bridge is excited by a
1 V 400 Hz excitation. Trace A in Figure 13 is the amplified bridge signal. Trace B is the output of the synchronous demodulator and Trace C is the filtered dc system output.
1V
400Hz
350
⍀
350 ⍀
+15V
350 ⍀
350 ⍀
49.9
⍀
+IN
AD8221
REF
A
–IN
9
SEL B
11
+V
S
16 R
A
17 R
IN
B
AD630AR
V
OUT
13
B
4.99k
⍀ 4.99k
⍀ 4.99k
⍀
2 ␮ F 2 ␮ F 2 ␮ F
19 CH B–
COMP 12
20 CH A–
15
R
F
R
IN
A
1
SEL A –V
S
10 8
R
14
B
C
Figure 12. AC Bridge System
–15V
REV. E –9–

AD630
3
C. 200 m V/DIV
[ T
B. 200 m V/DIV
]
500 ␮ s/DIV
T
A. 200 m V/DIV
Figure 13. AC Bridge Waveforms (1 V Excitation)
LOCK-IN AMPLIFIER APPLICATIONS
Lock-in amplification is a technique used to separate a small, narrow-band signal from interfering noise. The lock-in amplifier acts as a detector and narrow-band filter combined. Very small signals can be detected in the presence of large amounts of uncorrelated noise when the frequency and phase of the desired signal are known.
The lock-in amplifier is basically a synchronous demodulator followed by a low-pass filter. An important measure of performance in a lock-in amplifier is the dynamic range of its demodulator.
The schematic diagram of a demonstration circuit which exhibits the dynamic range of an AD630 as it might be used in a lock-in amplifier is shown in Figure 14. Figure 15 is an oscilloscope photo demonstrating the large dynamic range of the AD630.
The photo shows the recovery of a signal modulated at 400 Hz from a noise signal approximately 100,000 times larger.
CLIPPED
BAND-LIMITED
WHITE NOISE
AD542
B
16
5k
⍀
1
2.5k
⍀
AD630
15
10k ⍀
20
19
A
13
17
2.5k
⍀
B
100dB
ATTENUATION
14 10k
⍀
R
C
100R
AD542
100R
C
A
10
0.1Hz
MODULATED
400Hz
CARRIER
CARRIER
PHASE
REFERENCE
9
Figure 14. Lock-In Amplifier
LOW-PASS
FILTER
OUTPUT
5V 5V 5s
100
90
MODULATED SIGNAL (A)
(UNATTENUATED)
ATTENUATED SIGNAL
PLUS NOISE (B)
10
0%
OUTPUT
5mV
Figure 15. Lock-In Amplifier Waveforms
The test signal is produced by modulating a 400 Hz carrier with a 0.1 Hz sine wave. The signals produced, for example, by chopped radiation (i.e., IR, optical) detectors may have similar low frequency components. A sinusoidal modulation is used for clarity of illustration. This signal is produced by a circuit similar to Figure 9b and is shown in the upper trace of Figure 15. It is attenuated 100,000 times normalized to the output, B, of the summing amplifier. A noise signal that might represent, for example, background and detector noise in the chopped radiation case, is added to the modulated signal by the summing amplifier. This signal is simply band limited clipped white noise.
Figure 15 shows the sum of attenuated signal plus noise in the center trace. This combined signal is demodulated synchronously using phase information derived from the modulator, and the result is low-pass filtered using a 2-pole simple filter which also provides a gain of 100 to the output. This recovered signal is the lower trace of Figure 15.
The combined modulated signal and interfering noise used for this illustration is similar to the signals often requiring a lock-in amplifier for detection. The precision input performance of the
AD630 provides more than 100 dB of signal range and its dynamic response permits it to be used with carrier frequencies more than two orders of magnitude higher than in this example.
A more sophisticated low-pass output filter will aid in rejecting wider bandwidth interference.
–10– REV. E

REV. E
OUTLINE DIMENSIONS
20-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]
(D-20)
Dimensions shown in inches and (millimeters)
0.005 (0.13) MIN
20
PIN 1
1
0.080 (2.03) MAX
11
0.300 (7.62)
0.280 (7.11)
10
0.200 (5.08)
MAX
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
1.060 (28.92)
0.990 (25.15)
0.100
(2.54)
BSC
0.060 (1.52)
0.015 (0.38)
0.070 (1.78)
0.030 (0.76)
0.150
(3.81)
MIN
SEATING
PLANE
0.320 (8.13)
0.300 (7.62)
0.015 (0.38)
0.008 (0.20)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
20-Lead Plastic Dual In-Line Package [PDIP]
(N-20)
Dimensions shown in inches and (millimeters)
0.180 (4.57)
MAX
20
1
0.985 (25.02)
0.965 (24.51)
0.945 (24.00)
11
10
0.015 (0.38) MIN
0.295 (7.49)
0.285 (7.24)
0.275 (6.99)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.100
(2.54)
BSC
0.060 (1.52)
0.050 (1.27)
0.045 (1.14)
SEATING
PLANE
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
COMPLIANT TO JEDEC STANDARDS MO-095-AE
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
20-Terminal Ceramic Leadless Chip Carrier [LCC]
(E-20A)
Dimensions shown in inches and (millimeters)
0.358 (9.09)
0.342 (8.69)
SQ
0.100 (2.54)
0.064 (1.63)
0.358
(9.09)
MAX
SQ
0.088 (2.24)
0.054 (1.37)
0.075 (1.91)
REF
0.095 (2.41)
0.075 (1.90)
0.011 (0.28)
0.007 (0.18)
R TYP
0.075 (1.91)
REF
0.055 (1.40)
0.045 (1.14)
0.200 (5.08)
REF
0.100 (2.54) REF
0.015 (0.38)
MIN
19
18 20 4
3
13
14
1
BOTTOM
VIEW
0.028 (0.71)
0.022 (0.56)
8
0.050 (1.27)
BSC
9
0.150 (3.81)
BSC
45 TYP
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
–11–
AD630

AD630
20-Lead Standard Small Outline Package [SOIC]
Wide Body
(R-20)
Dimensions shown in millimeters and (inches)
13.00 (0.5118)
12.60 (0.4961)
20
1
11
10
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
1.27
(0.0500)
BSC
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
0.33 (0.0130)
0.20 (0.0079)
8 ⴗ
0 ⴗ
0.75 (0.0295)
0.25 (0.0098) ⴛ 45 ⴗ
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-013AC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Revision History
Location
6/04—Data Sheet changed from REV. D to REV. E.
Page
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Replaced Figure 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Changes to AC BRIDGE section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Replaced Figure 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Changes to LOCK-IN AMPLIFIER APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6/01—Data Sheet changed from REV. C to REV. D.
Changes to SPECIFICATION TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
–12– REV. E