CprE 488 – Embedded Systems Design
Lecture 1 – Introduction
Joseph Zambreno
Electrical and Computer Engineering
Iowa State University
www.ece.iastate.edu/~zambreno
rcl.ece.iastate.edu
The trouble with computers, of course, is that they’re very sophisticated idiots. They do
exactly what you tell them at amazing speed – The Doctor
What is an Embedded System?
• The textbook definitions all have their limits
• An embedded system is simultaneously:
1. “a digital system that provides service as part of a
larger system” – G. De Micheli
2. “any device that includes a programmable computer
but is not itself a general-purpose computer” – M.
Wolf
3. “a less visible computer” - E. Lee
4. “a single-functioned, tightly constrained, reactive
computing system” – F. Vahid
5. “a computer system with a dedicated function within
a larger mechanical or electrical system, often with
real-time computing constraints” – Wikipedia
Zambreno, Fall 2015 © ISU
CprE 488 (Introduction)
Lect-01.2
Perspective Matters!
• These definitions quickly become blurred
when changing perspective:
Part of a larger system:
Not general-purpose:
Less visible:
Tightly constrained:
Dedicated function:
Zambreno, Fall 2015 © ISU
CprE 488 (Introduction)
Lect-01.3
Another Practical Definition
• An embedded system is a computing system that uses an ARM
processor
• Multiple caveats:
– There is a significant 8-bit embedded market as well (e.g. PIC, Atmel,
8051)
– ARM is also attempting to grow into the desktop and server market
Zambreno, Fall 2015 © ISU
CprE 488 (Introduction)
Lect-01.4
A Different Paradigm
• Cyber-Physical System (CPS): an integration of
computation with physical processes
– Embedded computers monitor and control the physical
processes
– Feedback loops – physical processes affect computation,
and vice versa
• Examples tend to include networks of interacting components
(as opposed to standalone embedded devices)
• Still a matter of perspective as networks can span continents or be
enclosed in a single chip
Zambreno, Fall 2015 © ISU
CprE 488 (Introduction)
Lect-01.5
Scale of Embedded Devices
• Even as Electrical and Computer Engineers it can be
easy to understate the scale (both in terms of size
and ubiquity) of embedded devices
• SanDisk microSD card
• 100 MHz ARM CPU
• But for what reason?
Zambreno, Fall 2015 © ISU
• Apple Lightning Digital AV Adapter
• 256 MB DDR2, ARM SoC
CprE 488 (Introduction)
Lect-01.6
This Course’s Focus
• Embedded system design – the methodologies, tools, and platforms
needed to model, implement, and analyze modern embedded
systems:
– Modeling – specifying what the system is supposed to do
– Implementation – the structured creation of hardware and software
components
– Analysis – understanding why the implementation matches (or fails to
match) the model
– Design is not just hacking things together (which is admittedly also fun)
• What makes embedded system design uniquely challenging?
– System reliability needs:
• Can’t crash, may not be able to reboot
• Can’t necessarily receive firmware / software updates
– System performance and power constraints:
• Real-time issues in many applications
• (Potentially) limited memory and processing power
– System cost:
• Fast time to market on new products
• Typically very cost competitive
Zambreno, Fall 2015 © ISU
CprE 488 (Introduction)
Lect-01.7
CprE 488 Survival Skills
Necessary Skill
Gained From
Software Development (General)
ComS 207/227, EE 285
Pointers
Pointers
CprE 288
Memory and Peripheral Interfacing
CprE 288
CPU Architecture
CprE 381
HDL Design
CprE 381
Circuits and Signals
EE 230, EE 224
Critical Thinking
Your Parents
Planning and Hard Work
Your Parents
• Any course that claims to teach you how to design embedded
systems is somewhat misleading you, as the technology will
continue to undergo rapid change
• Our goal: provide a fundamental understanding of existing design
methodology coupled with some significant experience on a
current state-of-the-art platform
Zambreno, Fall 2015 © ISU
CprE 488 (Introduction)
Lect-01.8
CprE 488 – Meet the Staff
Prof. Joseph Zambreno
zambreno@iastate.edu
Office Hours: F 1-2 (327 Durham)
c
Ian McInerney
cpre488-tas@iastate.edu
Office Hours: M 12-2, F 2-4 (2041 Coover)
Teaching
Assistants
Tessa, Johnny, Joey
(Exam grading mostly)
Zambreno, Fall 2015 © ISU
CprE 488 (Introduction)
Lect-01.9
CprE 488 – Resources
• Main text: M. Wolf. Computers as
Components (3rd edition): Principles of
Embedded Computing System Design,
Morgan Kaufmann, 2012.
• We are here to help, but communication is key!
• Key online resources:
– Class webpage: class.ece.iastate.edu/cpre488 – contains
lecture notes, assignments, documentation, general
schedule information
– Blackboard space: bb.its.iastate.edu – will be heavily used
for announcements, discussion, online submission, grading
– Class wiki: wikis.ece.iastate.edu/cpre488 – updated (by
you!) to include general tips and tricks and project
photos/videos
Zambreno, Fall 2015 © ISU
CprE 488 (Introduction)
Lect-01.10
Weekly Layout (Tentative)
Monday
Tuesday
Wednesday
Thursday
Friday
9 am
Lab A
(2041 Coover)
10 00
11 00
12 pm
1 00
Ian
(2041 Coover)
Lecture
(1226 Howe)
Lecture
(1226 Howe)
Joe
(327 Durham)
2 00
3
Ian
(2041 Coover)
00
Lab B
(2041 Coover)
4 00
5 00
Zambreno, Fall 2015 © ISU
CprE 488 (Introduction)
Lect-01.11
FPGA Design Tools
• Necessary steps (scripts will be provided to help automate):
1.
2.
Login to any of the departmental Linux machines:
• Remote access to machines on the list here:
http://it.engineering.iastate.edu/remote/
• Use Cygwin/X (ssh), NX client (preferred if the machine supports it)
• Some extra machines connected to FPGA boards if you really need them
From the bash shell, enter the following:
source /remote/Xilinx/14.6/settings64.sh
export PATH=$PATH:/remote/Modelsim/10.1c/modeltech/linux_x86_64/
export LM_LICENSE_FILE=1717@io.ece.iastate.edu:27006@io.ece.iastate.edu
Zambreno, Fall 2015 © ISU
CprE 488 (Introduction)
Lect-01.12
Lecture Topic Outline
Lect-01:
• Lect-02:
• Lect-03:
• Lect-04:
• Lect-05:
• Lect-06:
• Lect-07:
• Lect-08:
Introduction
Embedded Platforms
Processors and Memory
Interfacing Technologies
Software Optimization
Accelerator Design
Embedded Control Systems
Embedded OS
Zambreno, Fall 2015 © ISU
CprE 488 (Introduction)
Lect-01.13
Machine Problems (MPs)
• 5 team-based, applied assignments
– Graded on completeness and effort
– Significant hardware and software components
– Two weeks each, with in-class and in-lab demos
• Tentative agenda:
– MP-0:
– MP-1:
– MP-2:
– MP-3:
– MP-4:
Platform Introduction
Quad UAV Interfacing
Digital Camera
Target Acquisition
UAV Control
Zambreno, Fall 2015 © ISU
CprE 488 (Introduction)
Lect-01.14
Course Project
• Student-proposed, student-assessed embedded system
design project
• Essentially a capstone project – integrating your
knowledge in digital logic, programming, and system
design
• Something reasonable in a 5-6 week timeframe, likely
leveraging existing lab infrastructure
• Deliverables:
– Project proposal presentation and assessment rubric (week 9)
– Project presentation and demo (10 minutes, week 16)
– Project page on class wiki, with images / video (continuous)
Zambreno, Fall 2015 © ISU
CprE 488 (Introduction)
Lect-01.15
Grading Policies
• Grade components:
–
–
–
–
–
Machine Problems [5x]
Homework
Class Participation
Midterm Exams [2x]
Final Project
(40%)
(10%)
(5%)
(30%)
(15%)
• At first glance, CprE 488 appears to be quite a bit of work!
– Yes. Yes it is. 
– The lab/final project component is probably the most important
– If you are a valuable member of your lab team, you will get an A
• Our goals as your instructor:
– To create a fun, yet challenging, collaborative learning environment
– To motivate the entire class to a 4.0 GPA
– To inspire you to learn more (independent study / MS thesis ideas?)
Zambreno, Fall 2015 © ISU
CprE 488 (Introduction)
Lect-01.16
Illustrative Design Exercise
• An illustrative example of embedded system
design inspired by Chapter 1 of the M. Wolf
textbook
GPS Navigation Unit
Zambreno, Fall 2015 © ISU
CprE 488 (Introduction)
Lect-01.17
Some High-Level Challenges
• How much hardware do we need?
– How big is the CPU? Memory?
• How do we meet our deadlines?
– Faster hardware or cleverer software?
• How do we minimize power?
– Turn off unnecessary logic? Reduce memory
accesses?
• Multi-objective optimization in a vast design
space
Zambreno, Fall 2015 © ISU
CprE 488 (Introduction)
Lect-01.18
Some High-Level Challenges [cont.]
• Does it really work?
– Is the specification correct?
– Does the implementation meet the spec?
– How do we test for real-time characteristics?
– How do we test on real data?
• How do we work on the system?
– Observability, controllability?
– What is our development platform?
Zambreno, Fall 2015 © ISU
CprE 488 (Introduction)
Lect-01.19
Abstraction Levels
• Growing system complexities
 Move to higher levels of abstraction [ITRS07, itrs.net]
 Electronic system-level (ESL) design
Algorithm
1E0
1E1
1E2
1E3
RTL
Gate
1E4
1E5
Accuracy
System level
System
level
Number of components
Abstraction
Level
1E6
Transistor
1E7
Source: R. Doemer, UC Irvine
Zambreno, Fall 2015 © ISU
CprE 488 (Introduction)
Lect-01.20
Abstraction Levels [cont.]
High abstraction
unstructured
Structure
Implementation Detail
physical layout
Spatial order
Zambreno, Fall 2015 © ISU
untimed
Timing
real time
Low abstraction
Temporal order
CprE 488 (Introduction)
Lect-01.21
Top-Down Design Flow
requirements
pure functional
Product planning
Specification
constraints
untimed
System Design
bus functional
timing accurate
Architecture
Processor Design
RTL / ISA
Implementation
cycle accurate
Logic Design
gates
gate delays
Structure
Zambreno, Fall 2015 © ISU
Timing
CprE 488 (Introduction)
Lect-01.22
• Hardware
– Microarchitecture
– Register-transfer level (RTL)
CPU
System Implementation
Mem
Program
EXE
IC
RTOS
HAL
Bridge
Arbiter
• Software binaries
– Application object code
– Real-time operating
system (RTOS)
– Hardware abstraction layer (HAL)
• Interfaces
– Pins and wires
– Arbiters, muxes, interrupt
controllers (ICs), etc.
– Bus protocol state machines
Zambreno, Fall 2015 © ISU
HW
IP
 Further logic and
physical synthesis
 Manufacturing
 Prototyping
boards
CprE 488 (Introduction)
Lect-01.23
Requirements
• Plain language description of what the user
wants and expects to get
• May be developed in several ways:
– Talking directly to customers
– Talking to marketing representatives
– Providing prototypes to users for comment
Zambreno, Fall 2015 © ISU
CprE 488 (Introduction)
Lect-01.24
Functional vs. Non-Functional Requirements
• Functional requirements:
– output as a function of input
• Non-functional requirements:
– time required to compute output;
– size, weight, etc.;
– power consumption;
– reliability;
– etc.
Zambreno, Fall 2015 © ISU
CprE 488 (Introduction)
Lect-01.25
GPS Navigation Unit Requirements
• Functionality: For automotive use. Show major roads
and landmarks.
• User interface: At least 400 x 600 pixel screen.
Three buttons max. Pop-up menu.
• Performance: Map should scroll smoothly. No more
than 1 sec power-up. Lock onto GPS within 15
seconds.
• Cost: $120 street price = approx. $30 cost of goods
sold.
Zambreno, Fall 2015 © ISU
CprE 488 (Introduction)
Lect-01.26
GPS Navigation Unit Requirements [cont.]
• Physical size/weight: Should fit in hand
• Power consumption: Should run for 8 hours
on four AA batteries
• Any others?
Zambreno, Fall 2015 © ISU
CprE 488 (Introduction)
Lect-01.27
System Specification
• Capture requirements
– Functional
Natural language
 Ambiguous
 Incomplete
• Free of any implementation
details
– Non-functional
• Quality metrics, constraints
• Formal representation
– Models of computation
• Analysis of properties
– Executable
• Validation through simulation
P1
d
P3
C1
P5
d
P2
P4
C2
 Application development
Precise description of desired system behavior
Zambreno, Fall 2015 © ISU
CprE 488 (Introduction)
Lect-01.28
GPS Specification
• Should include:
– What is received from GPS;
– Map data;
– User interface;
– Operations required to satisfy user requests;
– Background operations needed to keep the
system running
Zambreno, Fall 2015 © ISU
CprE 488 (Introduction)
Lect-01.29
GPS Unit System Specification (Diagram)
GPS
receiver
search
engine
database
Zambreno, Fall 2015 © ISU
renderer
display
user
interface
CprE 488 (Introduction)
Lect-01.30
System Architecture
CPU
– Processors
Arbiter
• General-purpose, programmable
• Digital signal processors (DSPs)
• Application-specific instruction
set processor (ASIP)
• Custom hardware processors
• Intellectual property (IP)
P1
P3
CPU Bus
P2
– Memories
Mem
C1, C2
Bridge
• Processing elements (PEs)
C1, C2
P5
P4
HW
IP Bus
IP
• Communication elements (CEs)
– Transducers, bus bridges
– I/O peripherals
• Busses
– Communication media
• Parallel, master/slave protocols
• Serial and network media
Zambreno, Fall 2015 © ISU
 Heterogeneous multiprocessor systems
 Multi-Processor Systemon-Chip (MPSoC)
CprE 488 (Introduction)
Lect-01.31
GPS Unit System Architecture (HW)
display
frame
buffer
CPU
GPS
receiver
memory
Zambreno, Fall 2015 © ISU
panel I/O
CprE 488 (Introduction)
Lect-01.32
GPS Unit System Specification (SW)
position
pixels
database
search
renderer
user
interface
timer
Zambreno, Fall 2015 © ISU
CprE 488 (Introduction)
Lect-01.33
Design and Integration
• Must spend time architecting the system
before you start coding
• Some components are ready-made, some
can be modified from existing designs, others
must be designed from scratch
• Next, must put together the components.
– Many bugs appear only at this stage
• Have a plan for integrating components to
uncover bugs quickly, test as much
functionality as early as possible
Zambreno, Fall 2015 © ISU
CprE 488 (Introduction)
Lect-01.34
Acknowledgments
• These slides are inspired in part by material
developed and copyright by:
– Marilyn Wolf (Georgia Tech)
– Frank Vahid (UC-Riverside)
– A. Gerstlauer (UT-Austin)
– Daniel Gajski (UC-Irvine)
– Ed Lee (UC-Berkeley)
– James Hamblen (Georgia Tech)
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CprE 488 (Introduction)
Lect-01.35