3.3 Integrated Circuit Chips
• Categorized to three groups: memory, microprocessor (logic), applicationspecific integrated circuit (ASIC).
• Examples:
CMOS: (invertor, NOT), AND, OR, NOR, NAND, XOR, XNOR
Memory (DRAM, SRAM, EPROM, NAND flash)
Complementary MOS, CMOS inverter = NOT
Vout
Vin
low/high
(∅
∅/1)
High/low
(1/∅
∅)
Vout
Vin
Grace H. Ho, Department of Applied Chemistry, National University of Kaohsiung
1
3.3 Integrated Circuit Chips
Example: CMOS inverter = NOT
Bias supply
A
• Widely used since 1980s.
• Low power consumption
(Simplified statement: At any point of
time in circuit operation only either
pmos or nmos is in on state, so there is
no shortcircuit path from VDD to GND
during operation.
Grace H. Ho, Department of Applied Chemistry, National University of Kaohsiung
Y
grounded
2
3.3 Integrated Circuit Chips
Example: AND閘
閘
P3
P4
P
N2
N1
N
(0, 0):
(0, 1):
(1,0):
(1,1):
Vdd-Q4-Y’-inverter & Vdd-Q3-Y’-inverter
Vdd-Q4-Y’-inverter
Vdd-Q3-Y’-inverter
Ground-Q1-Q2 –Y’ –inverter
Grace H. Ho, Department of Applied Chemistry, National University of Kaohsiung
low
low
low
high
3
3.3 Integrated Circuit Chips
Example: OR閘
閘
P3
P4
N1
(0, 0): Vdd-Q3-Q4-Y’-inverter
(0, 1): GND-Q2-Y’-inverter
(1, 0): GND-Q1-Y’-inverter
(1, 1): GND-Q1, Q2 -Y’-inverter
Grace H. Ho, Department of Applied Chemistry, National University of Kaohsiung
P
N2
N
low
high
high
high
4
3.3 Integrated Circuit Chips
Example: NAND閘
閘
P3
P4
N3
N1
Grace H. Ho, Department of Applied Chemistry, National University of Kaohsiung
Vdd-Q3, Q4-Y
Vdd-Q3-Y
Vdd-Q4-Y
GND-Q1-Q2-Y
5
3.3 Integrated Circuit Chips
Example: NAND閘
閘
Grace H. Ho, Department of Applied Chemistry, National University of Kaohsiung
6
3.3 Integrated Circuit Chips
Example: NOR閘
閘
Grace H. Ho, Department of Applied Chemistry, National University of Kaohsiung
7
3.3 Integrated Circuit Chips
Example:
XOR閘
閘 , EOR gate, or
EXOR gate
(exclusive OR gate)
Example: XNOR閘
閘
Grace H. Ho, Department of Applied Chemistry, National University of Kaohsiung
8
3.3 Integrated Circuit Chips
http://www.allaboutcircuits.com/textb
ook/digital/chpt-3/gate-universality/
Gate Universality: NAND and NOR gates possess a special property: they
are universal. That is, given enough gates, either type of gate is able to mimic
the operation of any other gate ty
CMOS
Inverter:
NOR
NAND
Grace H. Ho, Department of Applied Chemistry, National University of Kaohsiung
9
3.3 Integrated Circuit Chips
http://www.allaboutcircuits.com/textb
ook/digital/chpt-3/gate-universality/
Gate Universality:
NAND
Grace H. Ho, Department of Applied Chemistry, National University of Kaohsiung
NOR
10
Homework: Universal gates
瞭解 and邏輯判斷
http://www.allaboutcircuits.com/textbook/digital/chpt3/gate-universality/ 上面的例子。
“Given enough NAND (NOR) gates, NAND (NOR)
gates are able to mimic the operation of any other gate
type.”
Grace H. Ho, Department of Applied Chemistry, National University of Kaohsiung
11
3.3 Integrated Circuit Chips
3.3.1 Memory – Dynamic random access memory (DRAM)
• Examples:
CMOS (invertor, NOT), AND, OR, NAND
Memory (DRAM, SRAM, EPROM, NAND flash)
• DRAM- Can be assessed to read or write (0 or 1) in any order, in contrast
to a cassette tape, which employs sequential access.
• The most commonly used memory chip inside computers for data storage.
• 1 transistor + 1 capacitor = 1T1C.
Circuit of a DRAM memory cell.
Grace H. Ho, Department of Applied Chemistry, National University of Kaohsiung
12
3.3.1 Memory – Dynamic random access memory (DRAM)
Write:
1. Drive bit line
2. Select row
Read:
1. Precharge bit line to Vdd/2
2. Select row
3. Cell and bit line share charges
Minute voltage changes on the
bit line
4. Sense (fancy sense amp)
Can detect changes of ~1
million electrons
5. Write: restore the value
Refresh
1. Just do a dummy read to every
cell.
www-inst.eecs.berkeley.edu/~cs150/fa04/Lecture/lec16.ppt
Grace H. Ho, Department of Applied Chemistry, National University of Kaohsiung
13
3.3 Integrated Circuit Chips
3.3.1 Memory – Static random access memory (SRAM)
• Examples: Memory (DRAM, SRAM, EPROM, NAND flash)
• SRAM: a four transistors and two resistors (4T2R) or 6T device, using
latching transistors to keep the instruction or data memory.
- Much faster than DRAM, since no recharge to the capacitor is needed.
- An SRAM chip is much larger and more expensive than a DRAM chip.
- Used as cache memory (快速儲藏區
快速儲藏區 ) in computers to store the most
frequently used instructions. (v.s. DRAM used for less frequently used
instructions and data, and flash drives and hard disk drives (HDDs) being
nonvolatile memories.)
- Most logic IC chips, ASIC chips, and field programmable gate array
(FPGA) chips have embedded cache memory, which integrates SRAM
into their chip.
- SRAM arrays always have the highest device
density, and are used as the test vehicles for
technology development and qualification.
Grace H. Ho, Department of Applied Chemistry, National University of Kaohsiung
14
3.3.1 Memory – Static random access memory (SRAM)
Example: SRAM
How does an SRAM work?
Standby
- The word line is open
M5 and M6 disconnect the cell from the bit lines.
- The two cross-coupled inverters (M1 – M4) continue to reinforce each
other as long as they are connected to the supply (Vdd).
Access
transistor
Bitline-not
Bistable latching
circuitry (Flip-flop)
to store each bit.
CMOS
Inverter
“NOT”
Grace H. Ho, Department of Applied Chemistry, National University
of Kaohsiung
https://en.wikipedia.org/wiki/Static_random-access_memory
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3.3.1 Memory – Static random access memory (SRAM)
Example: SRAM
How does an SRAM work?
Read:
1. Select row
2. Cell pulls one line low and one high
3. Sense output on BL and BL-NOT
Write:
1. Drive bit lines
To write a 0: Set BL to 0 and BLNOT to 1.
To write a 1: Set BL to 1 and BLNOT to 0.
2. Select row
• Why does this work?
– When one bit-line is low, it will force output high; that will set new state
https://en.wikipedia.org/wiki/Static_random-access_memory
Grace H. Ho, Department of Applied Chemistry, National University of Kaohsiung
16
3.3.1 Memory – EPROM
: Erasable Programmable Read-Only Memory
EEPROM: Electric EPROM
nonvolatile memory
• A floating gate connects to
nowhere.
Permanently stores electrons
as digital data.
• VG>VT>0:
- Electrons conduct from source
to drain.
- Some electrons (hot electrons)
tunnels through the thin Gox
into the floating gate and stay
there for years.
• Either UV or biasing
the control gate to
erase memory.
Grace H. Ho, Department of Applied Chemistry, National University of Kaohsiung
17
3.3.1 Memory – NAND Flash
Flash memory
• EEPROM that costs significantly less to manufacture. Introduced by Toshiba in
1984.
• Example: 64-bit NAND flash circuit.
- 64 word lines (0-63)
- SG0: the nMOS to select the string to the ground (source)
- SG1: the nMOS to allow the string to be selected by the bit line.
NAND flash used in USB
flash drives, solid state disks
(SSDs), memory cards for
mobile phones, digital
cameras, digital camcorders,
and other mobile devices.
SSDs are faster and more
reliable and also consume less
power than HDDs.
$$$$ *10 times.
Grace H. Ho, Department of Applied Chemistry, National University of Kaohsiung
18
BiCMOS
• BiCMOS makes use of the best features of both CMOS and bipolar technology.
Low-power, high density CMOS structures.
CMOS as logic circuit, bipolar for input/output, faster than CMOS.
• Complex digital control of high-power loads:
(1) Digital / analog converter (DAC) to drive signals used to control
electromechanical equipment.
(2) Analog / digital converter (ADC) to measure the outcome of analog drive
signals.
Grace H. Ho, Department of Applied Chemistry, National University of Kaohsiung
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