Digital Signal Processing
Vref
Analog signal (time
varying, continuous)
Incoming
samples
Analog-toDigital
Converter
(ADC)
0
Applications
0x030,
0x4A,
0x12,
0xAF, etc.
Time
Vref
Digitalto-Analog
Converter
(DAC)
new
waveform
0
Time
0x0B3,
0x23,
0xCF,
0x78, etc.
µProcessor
performs
computation
• Audio
– Speech recognition
– special effects (reverb, noise cancellation, etc)
• Video
– Filtering
– Special effects
– Compression
• Data logging
Outgoing samples
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1
Vocabulary
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2
Digital-to-Analog Conversion
• ADC (Analog-to-Digital Converter) – converts an analog
signal (voltage/current) to a digital value
• DAC (Digital-to-Analog Converter) – converts a digital
value to an analog value (voltage/current)
• Sample period – for ADC, time between each conversion
For a particular binary code, output a voltage between
0 and Vref
Vref
D[7:0]
Vout
DAC
– Typically, samples are taken at a fixed rate
• Vref (Reference Voltage) – analog signal varies between 0
and Vref, or between +/- Vref
• Resolution – number of bits used for conversion (8 bits, 10
bits, 12 bits, 16 bits, etc).
• Conversion Time – the time it takes for a analog-to-digital
conversion
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Assume a DAC that uses an unsigned binary input code,
with 0 < Vout < Vref. Then
D= 0000 0000
D= 0000 0001
D = 0000 0010
...
D = 1111 1111
(one LSB)
Vout = Vref(255/256) (full scale)
3
DAC Output Plot
Vout
Vout = 0V
Vout = Vref(1/256 )
Vout = Vref(2/256)
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4
Typical DAC Output
Output signal
increases in 1 LSB
increments.
4/256 Vref
3/256 Vref
2/256 Vref
1/256 Vref
0
1
2
3
From http://www.allaboutcircuits.com
Input code
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1
DAC Architecture (cont)
DAC Architecture
Note ratios of
resistors
This is a binary code
Operational
Amplifier can be
used to sum
voltages.
From http://www.allaboutcircuits.com
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7
From http://www.allaboutcircuits.com
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8
Another View
DAC Architecture (cont)
A 3-bit DAC, called an R/2NR DAC. Resistors are
scaled by powers of 2 (this is hard to do in practice).
Resistance values are still R, 2R, 4R
From http://www.allaboutcircuits.com
From http://www.allaboutcircuits.com
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R/2R DAC
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10
Commercial DACs
• Either voltage or current DACs
– Current DACs require an external operational amplifier
to convert to voltage
• Precision up to 16-bits
• Key timing parameter is settling time - amount of
time it takes to produce a stable output voltage
once the input code has changed
• We will use an 8-bit voltage DAC with an I2C
interface from Maxim semiconductor
Via circuit analysis, can prove this is an
equivalent circuit.
Now only need resistances of R, 2R –
this is easy to do. This is the most
common DAC architecture.
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From http://www.allaboutcircuits.com
11
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12
2
DAC Application
A 1-bit ADC
Phosper
Vertical Deflection
Cathode
R
DAC
G 8
B 8
8
DAC
DAC
Vref
Red
Electron Beams
(Red, Green Blue)
Green
Vin
R
Vref/2
Blue
Grid
Vout=Vdd is Vin > Vref/2
-
Vout=0 if Vin < Vref/2
digital signal
comparator
13
V 0.1
A 2-bit ADC
Vin
+
-
3/4Vref
Vin
+
B
1/2Vref
Vin
+
C
-
1/4Vref
R
14
ADC Architectures
A
-
R
+
Horizontal Deflection
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R
Vdd
R
High speed video
DACs produce RGB
signals for color CRT
R
analog signal
• The previous architectures are called Flash ADCs
A B C
D1 D0
------------0 0 0
0 0
0 0 1
0 1
0 1 1
1 0
1 1 1
1 1
–
–
–
–
–
D[1:0]
• Successive approximation ADCs
(other codes
don’t cares)
– Use only one comparator
– Take one clock cycle per bit
– High precision (16-bit converters are available)
Encoding logic
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Fastest possible conversion time
Requires the most transistors of any architecture
N-bit converter requires 2N-1 comparators.
Commercially available flash converters up to 12 bits.
Conversion done in one clock cycle
15
Successive Approximation ADC
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16
Commercial ADCs
First, set DAC to produce
Vref/2.
Output of Comparator is
Q[N-1] (MSB)
If MSB =1 , then Vin
between Vref and Vref/2, so
set DAC to produce ¾ Vref.
If MSB=0, then Vin
between Vref/2 and 0, so set
DAC to ½ Vref.
Output of comparator is now
Q[N-2].
• Key timing parameter is conversion time – how
long does it take to produce a digital output once a
conversion is started
• Up to 16-bit ADCs available
• Separated into fast/medium/low speed families
– Serial interfaces common on medium/low speed ADCs
• For high-precision ADCs, challenge is keeping
system noise from affecting conversion
– Assume a 16-bit DAC, and a 4.1V reference, then 1 LSB
= 4.1/216 = 62 µV.
Do this for each bit.
Output is Q[N].
From http://www.allaboutcircuits.com
Takes N cycles.
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18
3
PIC16 A/D
Input Pins
• PIC16F873 has onboard A/D
–
–
–
–
–
Successive approximation
10 bit resolution
Reference voltage can be Vdd or separate voltage
Multiple input (more than one input channel)
Time per bit(Tad) for conversion is either 2Tosc, 8Tosc, or
32 Tosc, where Tad cannot be less than 1.6 us (Tosc =
1/Fosc)
• Total conversion time is 10* Tad +Taq (acquisition)
– Taq is approximately 20 us; acquisition time is the amount of
time input capacitor requires to charge up to input voltage.
– So a 20 Mhz Fosc, Tosc = .05 us, so 32Tosc = 1.6 us;
conversion time = 10*1.6 us + 20 us = 36 us.
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Analog input channels (AN0,AN1, AN4)
Can be analog
input channels
or Vref+/Vref-
19
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20
Acquisition Time
Channel
select
analog
mux.
Acquisition time is the time required for the analog input voltage
to be sampled by the input capacitor.
A/D Block
Diagram
Vref+/Vref- select
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21
Voltage References
Example Commercial voltage reference: 2.048v, 2.5v , 3v, 3.3v,
4.096v, 5v (Maxim 6029)
Vdd
Vref
This process is also called sample and hold.
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Key parameter for a voltage is
stability over temperature operating
range. Need this to be less than ½
of a LSB value.
– ADCON1 used to configure port A for analog/digital
inputs, voltage reference
– ADCON0 used for clock selection, analog input selection,
start/finish conversion status.
• ADRESH, ADRESL -10-bit results returns in two
registers
– 10-bit result can be configured to be left or right justified.
ADRESH : ADRESL
ADRESH : ADRESL
DD DDDDDDDD
00000098 76543210
DDDDDDDD DD
98765432 10000000
Right justified
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• ADCON0, ADCON1 – configuration registers
We will use Vdd as our voltage reference for convenience, but will
be throwing away at least two bits of precision due to Vdd
fluctations.
4.096v
When the conversion begins, the sampling switch is OPENED and
the input capacitor holds the input voltage while the conversion is
done.
PIC A/D Registers
Stability of voltage reference is critical for high precision
conversions.
5V
The sampling switch is CLOSED during this time.
23
Left justified
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4
MAXIM 517 DAC
Max517 I2C Transaction
R/2R DAC
I2C
interface
Not present on
Max517, Vref
instead.
First byte: Device address
Personalizes device
address
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Third Byte:
output byte to
DAC
Second Byte: DAC
command byte
25
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Command Format
Device Address Format
Only command byte we will use for Max517 will be
00000000 = 0x00 as this does a write to DAC0.
For Max517, bits [7:3] = 01011
If AD1:AD0 tied to gnd then address is: 01011000 = 0x58
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Testing the ADC and DAC
Timing
Analog
input
Vdd
Analog out, To
multimeter or scope
16F873
RA0/AN0
Max517 DAC has a 6 us settling time.
Requires 3 bytes over I2C bus to write a new value.
10K Pot.
Maxim 517
OUT1
OUT0
AD1
RC3/SCK/SCL
SCL
RC4/SDI/SDA
SDA
AD0
Vdd
If you have trouble
distinguishing which
8-pin DIP in your
parts kit is the
MAX517, look for the
Maxim symbol on the
package.
At 400Khz, one bit time = 2.5 us.
Each byte is 8 bits + 1 ACK.
This diagram assumes that 10K pullups are already on the
SCL/SDA lines from the previous lab.
So 27 bits * 2.5 us = 67.5 us not counting software overhead. So
we are limited by I2C bus speed, not by the DAC settling time.
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Read the voltage from the potentiometer via the PIC A/D, write
this digital value to the DAC. The DAC output voltage should
match the potentiometer voltage.
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5
Potentiometer
Vdd
dactest.c
A variable resistor. Tie outer two legs
to Vdd/GND. Voltage on middle leg
will vary between Vdd/GND as
potentiometer is adjusted, changing the
position of the wiper on the resistor.
/* A/D Setup */
/* all bits input */
TRISA = 0xFF;
A/D Configuration
/* A0 analog input, others digital,right
justification of result */
ADCON1 = 0x8E;
/* sampling freq = Fsoc/32, channel 0 */
ADCON0 = 0x80;
/* turn on ADC*/
bitset(ADCON0,0);
printf("ADC is configured!!!");
pcrlf();
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31
V 0.1
dactest.c (cont.)
dactest.c (cont.)
int adc_value;
for(;;) {
bitset(ADCON0, 2); /* start conversion */
/* wait for end of conversion */
while (bittst(ADCON0,2));
#define DAC 0x58
/* read result */
Read from A/D, print
adc_value = 0;
adc_value = adc_value | (ADRESH << 8);
adc_value = adc_value | (ADRESL);
printf("%x",adc_value);
pcrlf();
i2c_WriteTo(DAC);
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Invert
Clipped
33
34
• Vocabulary
• DAC R/2N architecture
• ADC Flash, Successive approximation
architectures
• PIC A/D
Vnew = Vold >> 1
– How to configure
– Acquisition, Conversion time
– How to start do conversion, read result
Vnew = Vref-Vold
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V 0.1
What do you have to know?
Vnew = Vold << 1
‘if’ tests to Vmax
check if Vold
in range
DAC output byte
i2c_Stop();
}
Modify dactest.c to provide four functions:
Divide by 2
DAC command byte
i2c_PutByte(val);
Modifications to dactst.c
Multiply by 2
device address byte
i2c_PutByte(0x00);
Only write upper 8
bits to DAC
}
/* I2C DAC 01011000 */
void update_dac(unsigned char val) {
dac_value = ((adc_value >> 2)) & 0x00ff;
/* now write to DAC */
update_dac(dac_value);
32
• Max517 DAC usage
Vmin
35
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6