Protecting low voltage signals from ESD: Facts and myths

Protecting low-voltage signals from ESD
Facts and myths about low-voltage ESD protection solutions
Joe Salvador, (former) Director of Marketing,
Consumer & Computing Products, California Micro Devices
As semiconductor manufacturing geometries shrink, many system design engineers
find they are spending increasing amounts of time worrying about how to select appropriate
external electrostatic discharge (ESD) protection devices. A topic that was once an
afterthought for most board designers has now become a primary design consideration.
Unfortunately, there is a lot of confusion in the market about which parameters are
important when evaluating an ESD device. Issues such as working voltage, breakdown
voltage, clamping voltage, dynamic resistance, and residual current are all important, but
often not understood. ESD vendor datasheets can compound the problem, as they often lack
critical information or even provide misleading data. One such example is the use of “low
voltage” ESD protection solutions and the role that a low voltage diode plays in both signal
integrity and ESD protection.
Before jumping into the details of comparing various ESD protection solutions, it is important
to first understand how modern semiconductor devices can be damaged during an ESD
event. A typical example of an ESD event occurs when an end user touches an exposed port
or interface on an electronics device. In this situation, voltage discharges in excess of 30 kV
are possible under normal operating conditions.
Most electronic devices designed today are required to meet a minimum of 8 kV contact
discharge or 15 kV air discharge, based on the international standard IEC61000-4-2.
Unfortunately, most semiconductor devices will not withstand this level of electrical stress
and can be permanently damaged. To survive, additional off-chip protection circuits be
designed into the system.
Small geometry semiconductor devices are typically damaged due to excessive voltage, high
current levels, or a combination of both. High voltage levels can cause gate oxide punchthrough, while excessive current can cause junction failures and metallization traces to melt.
As manufacturing geometries decrease, the voltage and current levels that cause these
problems are also decreasing, making it even more critical to provide adequate external
(Note: there is a useful glossary of ESD-related definitions at the end, after “About the
author; be sure you are familiar with these and their specific meanings in this context.)
Where to focus: voltage, current, or both?
Ideally, an ESD protection device will clamp the ESD voltage to just above the working
voltage of the I/O line, while shunting all of the ESD current away from the protected
circuitry. In practice, this is impossible, so the designer must choose a device that provides
the lowest clamping voltage and lowest residual current possible.
Many ESD protection vendors focus on their device clamping voltage. This can often be
misleading, as the typical ESD datasheet shows a clamping voltage during a pulse of 1 A, with
a rise time of 8 microseconds. In contrast, an 8KV IEC61000-4-2 ESD pulse has a 1 nsec rise
time, with a peak pulse current of 30 A, Figure 1.
Figure 1: IEC61000-4-2 ESD pulse waveform
In some cases, this 1 A clamping voltage is also often confused with the ESD diode’s working
voltage, or the ESD diode’s breakdown voltage, all of which will typically be much lower than
the actual clamping voltage during an ESD event.
In many ESD devices, the relationship between breakdown voltage and clamping voltage can
be simplified as a roughly linear relationship where:
Vclamp = Vbreakdown + (Rdyn x current)
Therefore, the clamping voltage Vclamp is related to both the breakdown voltage Vbreakdown of
the ESD device and its dynamic resistance Rdy.
Many ESD protection vendors focus on the first parameter – Vbreakdown. By lowering the
breakdown voltage, they argue, they will lower the clamping voltage. While this is true, all
else being equal, it does not have as big of an impact as would initially be expected.
Some ESD vendors even go so far as to say you NEED a lower breakdown-voltage ESD circuit
when protecting low-voltage I/O lines. This is absolutely NOT true. In fact, some “high
voltage” devices actually provide lower clamping voltages than low-voltage ESD devices,
while also providing lower residual current.
Clamping Voltage Example
In a typical system, a discrete TVS (DUT – device under test) device is placed near the
connector to shunt any induced ESD current back to chassis ground, and back out of the
system. In Figure 2, Z1 represents the DUT or protection device, while the DUP (device under
protection) shows both internal circuitry U1 as well as on-chip ESD protection (D1 and D2).
Figure 2: Ideal protection circuit in a system
It is often assumed that as long as Z1’s Vclamp voltage on the I/O node is kept low enough such
that D1 (on a positive strike) and D2 (on a negative strike) do not begin to conduct, that no
damage will occur to the DUP. While this is indeed true, it also cannot be realistically
achieved during actual ESD strikes of several kilovolts.
Even a zero-ohm resistor on a trace will not clamp the 1 ns peak voltage of an IEC61000-4-2
strike to 0 V, because the package inductance increases the dynamic resistance during the
transient. In reality, all TVS DUTs will behave more generally like the simplified circuit of
Figure 3.
Figure 3: Simplified realistic model of system’s protection circuit
After the trigger voltage is reached and the device begins to “turn-on” (the response time),
the DUT presents a time-varying dynamic resistance shunt to ground. This path may actually
appear in series with an effective breakdown voltage and/or snap-back voltage which is also
time variant, depending on the device architecture and also I2R-heating dependent during
the strike. Remember:
Actual DUT will not shunt 100% the current
Rdyn is never 0, and it also has L/C parasitics
What the device under protection (DUP) will see on its input will be the voltage across the
dynamic resistance of the TVS DUT plus the dynamic breakdown voltage or snap-back
voltage of the clamp structure, if any.
Even with a low breakdown voltage and low dynamic resistance of the DUT, D1 or D2 in the
DUP will begin to conduct some current during the strike as a KCL current-sharing mix
between the effective dynamic resistances of the DUT and the DUP. A simple shunt-TVS
DUT can never shunt “all” the current, and the DUP can never expect to see “zero” current
during a strike.
What should be obvious from this discussion is that a low breakdown voltage does not
necessarily result in a lower clamping voltage, which is also dependent on the Rdyn of the
protection device.
To illustrate this, we took publicly available data from two ESD protection devices, one of
which has a 2.5 V standoff voltage (working voltage from 0 to 2.5 V), while the other has a 6
V standoff voltage and 7 V breakdown voltage (Figure 4).1
Figure 4: Comparing two real-world ESD devices
The initial assumption would be that the 2.5 V device should be better, due to its lower
breakdown voltage, but the actual peak-clamping voltage, according to the ESD vendor’s
own datasheet, is significantly higher than the 7 V solution.
One would be surprised to find that, even in the datasheet for a “2.5cV” device, the peak
clamping voltages exceeds 142 V for an 8-kV strike, although the advertised “Rdyn” numbers
are at or below 1 . Using this number, one would expect clamp voltages on an 8-kV IEC
pulse to be no higher than around 30 V.
It turns out that the 2.5V device actually has a higher Rdyn during the ESD strike:
2.5 V “Snapback” Device => 4.6
7 V Dual-Rail Zener Device =>
x 30 A + 2.5 V = 142 V peak
x 30 A + 7.0 V = 112 V peak
Why the apparent discrepancy? Dynamic resistance here is the actual instantaneous
impedance presented to the wide bandwidth ESD pulse. Many datasheets reference a
number derived from an 8/20 s pulse, which is much slower than ESD and glosses over
high-frequency parasitics and packaging issues.
The most important observations here are:
regardless of whether the 1 IEC61000-4-5 numbers ,or a back-calculated
impedance, is calculated from actual observations, the actual voltage seen by the
Product names and vendors have been removed as this article was not meant to showcase one vendor’s products
vs. another’s. Data is available on request.
DUP is likely to be far in excess of the breakdown or snapback voltage with even the
very best devices,
when using a simple shunt-only type device, the DUP will have to survive this
overstress for a short period of time.
Voltage vs. Current – what really matters
Many system design engineers would be shocked to learn that their 2.5 V (or even 7 V) ESD
solutions were clamping at over 100 V. Luckily, due to the short width of the ESD pulse,
most DUPs can tolerate these voltages. In fact, most ESD damage is related more to high
residual currents and total dissipated energy during the pulse than it is to the ESD clamping
Lowering the DUT’s dynamic resistance will reduce the residual current, as well as reducing
the clamping voltage. As low dynamic resistance will lower both the Vclamp and Iresidual, it
should be obvious that Rdyn is one of the most important parameters when evaluating an ESD
protection solution, and is much more critical than lowering a breakdown voltage by a
couple of volts.
In some cases, reducing Rdyn of the ESD device can prove difficult. For example, vendors of
low capacitance protection circuits usually must make a tradeoff: as they strive for lower
capacitance to achieve improved signal integrity, they often must compromise with
increased dynamic resistance due to the smaller size of the low-capacitance circuit.
Choosing a low-voltage protection solution can also create unintended signal-integrity issues
as well. Take another example, shown in Figure 5, where an ESD vendor has published the
following data in their datasheet for three similar devices with different breakdown voltages:
Device A
Device B
Device C
Working peak
reverse voltage
2.5 V
5.0 V
6.0 V
Ir (uA) @ Vrwm
Vbr @ 1mA
Leakage current at
working peak
reverse voltage
6.0 uA
4.0 V
0.05 uA
6.2 V
0.01 uA
6.8 V
Figure 5: Leakage current in example low voltage ESD diodes5
In this case, the vendor is offering diodes with peak working voltages of 2.5 V, 5.0 V, and 6.0
V. A system designer tempted to use the lowest breakdown voltage solution should choose
Amerasekera A and Duvvury C 2002 ESD in Silicon Integrated Circuits 2nd Ed. (New York: Wiley)
“Peak current failure levels in ESD sensitive semiconductor devices and their application in evaluation of
materials used in ESD protection” Journal of Physics: Conference Series 142 (2008)
Consistent with ESD failure analysis performed at California Micro Devices on multiple semiconductor devices
Product names and vendors have been removed as this article was not meant to showcase one vendor’s products
vs. another’s. Data is available on request.
Device A. However, this device results in significantly higher leakage current in the operating
range than Device B or Device C. Whether this loss in signal integrity is acceptable must be
determined by the system design engineer, but it is an important consideration – generally,
the closer the ESD device breakdown voltage is to the signal’s peak voltage, the greater the
leakage and thus the greater impact on signal integrity.
In cases where the DUT is extremely sensitive, even very low Rdyn and low-voltage solutions
may prove to be inadequate to protect very-small-geometry circuits. In these cases, other
methods of limiting current must be employed.
This can be accomplished in several ways. One method often used includes the integration of
impedance-matched inductance or resistance into the circuit between the DUT and the DUP.
Another common practice is to use multiple clamping stages, essentially creating two or
three shunt stages between the I/O connector and the DUP.
While these approaches may seem cumbersome and expensive, recently ESD products have
been introduced that integrate these functions into a single device, making the designer’s
task simpler while providing dramatically better ESD protection and improved high speed
signal integrity. Additional information on these and other ESD protection solutions can be
found on
Lowering the breakdown voltage of an ESD device in order to provide improved ESD
protection seems intuitively obvious. In practice though, this provides little value and can
even be misleading when compared to other parameters of a protection device, particularly
the dynamic resistance of the ESD device.
In the case of sensitive I/O’s, the increased leakage of lower breakdown-voltage ESD
solutions can even cause signal integrity issues. To properly evaluate ESD devices, system
designers need to understand and compare issues such as clamping voltages, dynamic
resistance, residual current and total power dissipation during an ESD strike.
Unfortunately, very few ESD device datasheets provide this data. Until they do, system
designers need to beware of marketing claims, carefully test ESD-protection solutions in the
lab, and demand datasheet improvements from their ESD protection suppliers.
About the author
Joe Salvador was formerly Director of Marketing, Consumer & Computing Products at
California Micro Devices ( in Milpitas, California. He received his BSE
in Computer Science Engineering from the University of Pennsylvania, and his MBA form
Carnegie Mellon.
ESD definitions
Working Voltage – range where the device is considered “off”, conducting little to
no energy (typically < 1 A). The expected range of signal voltages on the I/O line
being protected should be within the working voltage range.
Breakdown Voltage – when the device begins to conduct current. Typically
specified at a range of 1mA to 10mA. Note – this is NOT the clamping voltage.
Clamp Voltage – the voltage seen at the protected device during an ESD event.
Care must be taken when reading datasheets. Most ESD device datasheets
specify a clamping voltage based on an IEC61000-4-5 pulse at 1 A of current,
rather than an IEC61000-4-2 pulse at 30 A. These values are usually very different.
Iresidual – the current during an ESD strike that is not shunted by the protection
device, but instead reaches the device being protected.
Rdyn – the dynamic resistance of an ESD device during an energy pulse. As Rdyn of
an ESD device increases, both the clamping voltage and residual current also