FT13
VSD537
VSD2537
Session-10
Case study on PLL
Session delivered by:
Chandramohan P.
©M. S. Ramaiah School of Advanced Studies
1
FT13
Introduction
VSD2537
A phase-locked loop (PLL) is a circuit that synchronizes the output signal of an
oscillator with a reference or input signal in frequency as well as in phase.
PLL Targeted
for design
Wireless PLL
Communication
[16]Transceiver [17]
Application System
in Wireless
©M. S. Ramaiah School of Advanced Studies
2
FT13
Introduction (cont ...)
VSD537
VSD2537
PLLs have a wide applications for Frequency Synthesis. In such case the output
of PLL is a multiple of the frequency of the input reference signal.
PLL as Frequency Synthesizer [14]
The phase detector tracks the changes in input w.r.t. the output provided to it
through feedback. This changes the control voltage for VCO to change its
frequency to be in alignment to the multiple of the reference signal
©M. S. Ramaiah School of Advanced Studies
3
FT13
Introduction
VSD537
VSD2537
A phase-locked loop (PLL) is a circuit that synchronizes the output signal of an
oscillator with a reference or input signal in frequency as well as in phase.
PLLs have wide applications for Frequency Synthesis. In such case the output of
PLL is a multiple of the frequency of the input reference signal.
PLL as Frequency Synthesizer [14]
The phase detector tracks the changes in input w.r.t. the output provided to it
through feedback. This changes the control voltage for VCO to change its
frequency to be in alignment to the multiple of the reference signal
©M. S. Ramaiah School of Advanced Studies
4
FT13
Introduction (cont ...)
VSD2537
PLLs are often used in the I/O interfaces of digital integrated circuits in order to
hide clock distribution delays and to improve overall system timing by closely
tracking the input clock.
Need for Low Jitter:
• High-speed circuits create a noisy environment which causes the clock to jitter
• Tolerance for jitter has shrunk due to the decrease in period of the output clock
Why Adaptive Bandwidth?
An adaptive bandwidth that tracks with the operating frequency helps to sustain
the best jitter performance of the PLL over a wide frequency range
Preference for Charge Pump PLL:
• Phase Detector (PD) provide a non-linear modelling of a linear block
• Phase and Frequency Detector (PFDs) have been widely used (replacing PD)
for their extended tracking range, frequency-aided acquisition and low cost
• Charge pump usually accompanies the PFD, to convert the timed logic levels of
the PFD into analog signals suitable for controlling the VCO
©M. S. Ramaiah School of Advanced Studies
5
FT13
VSD537
VSD2537
Summary of Literature Survey
Comparison of Various PLL Architectures [3], [6-8]
Year
Author(s)
Title
Publication
Specifications
Features
Limitations
2004
Tian Jun, Wang A Monolithic 1
Zhigong, Liang GHz 0.6µm CMOS
Bangli, Hu Yan, Low Jitter PLL [6]
Shi Yi and
Zheng Youdou
Proceedings of the
The RMS jitter is lower
Based on the negative
Needs modifications to make it
7th International
than 4.8 ps at 1 GHz
conductance configuration
suitable for the use of the gigabit
Conference on Solid- The phase noise is as
Novel differential delay cells
Ethernet systems and SDH
State and Integrated
slender as -97 dBc/Hz at
with active inductor loads are
STM-4 digital optical
Circuits Technology
10 kHz offset
used to lower phase noise and to
communication systems
2004, pp. 1500-1503, The total power
improve linearity of the ring
October 2004
consumption is 214 mW
VCO
when the PLL is locked at
1 GHz under a single 5 V
supply
2004
Nicola Da Dalt,
Edwin Thaller,
Peter Gregorius
and Lajos Gazsi
A Low Jitter
Triple-Band Digital
LC PLL in 130nm
CMOS [7]
Proceeding of the
Die area as small as
30th European Solid- 0.24mm2
State Circuits
16mA of current,
Conference 2004, pp. Consumption
371-374, September Long-term jitter of 640fs
2004
2004
Roberto Nonis,
Nicola Da Dalt,
Pierpaolo
Palestri and Luca
Selmi
Modeling, design
and
characterization of
a new low jitter
analog dual tuning
LC-VCO PLL
architecture [8]
It features very low VCO gain
The inaccuracy of the simulated
Proceedings of the
Integrated jitter to be
for noise rejection
phase noise of the crystal
International
0.74 ps
oscillator used as reference,
Symposium on
The circuit area is 0.7mm2 It is equipped with an automatic
improvement on jitter
Circuits and Systems The power consumption is analog calibration of the VCO
32mW
curve
performance has been 43%
2004, pp. IV - 553instead of the predicted 72%
556, May 2004
2002
Nicola Da Dalt,
Sven Derksen,
Patrizia Greco,
Christoph
Sandner, Harald
Schmid and
Klaus
Strohmayer
A Fully Integrated
2.4GHz LC-VCO
Frequency
Synthesizer with 3ps Jitter in 0.18µm
Standard Digital
CMOS Copper
Technology [3]
IEEE Transactions
3-ps rms long-term jitter
on Solid-State
on a 200-MHz output
Circuits, vol. 37, No. 20-mW power
7, pp. 959-962, July
consumption
2002
Area of 0.7 mm2
A digital core and a digitally
The low frequency modulation
controlled LC oscillator
scheme has to remain
It supports triple-band operation
undistorted to avoid additional
in multi-GHz range (2.lGHz
determinist jitter or wander
3.3GHz and 4.4GHz) with a
Needs BIAS stage to generate
single programmable coil
the currents needed for the DCO
and CML dividers
Use of an LC voltage-controlled The disadvantage is the larger
oscillator (LC-VCO) as the core
area required by the LC-VCO,
oscillator
due to the metal coil. The
The synthesizer is designed to
integrated LC-VCOs using a
provide various output clock
metal coil as an inductor on
signals for a transceiver chip
digital CMOS technologies,
yields excellent phase-noise
performance
©M. S. Ramaiah School of Advanced Studies
6
FT13
Summary of Literature Survey (cont ...)
VSD537
VSD2537
PLL Feature : Pros and Cons [15]
PLL Feature
High bandwidth
Advantages
•
•
•
Low tracking jitter
Low long-term jitter
Needed for deskew PLLs
•
•
•
•
Low bandwidth
•
•
•
Tracking bandwidth
(i.e. selfbiased PLLs)
•
•
•
•
•
Low-Q VCO
(ring/relaxation
oscillators)
High-Q VCO
(LC/Xtal oscillator)
•
•
•
•
•
Low period jitter
Period jitter filtering
Low frequency overshoot
Wide operating frequency range
Wide multiplication range
Constant loop dynamics
Maximizes tracking bandwidth
Minimizes PVT sensitivity
Wide VCO frequency range
Can have low period jitter
Most common approach for digital chips
Low long-term and period jitter
Long-term and period jitter filtering Low phase noise
•
Poor long-term jitter (without high-Q VCO)
No long-term jitter filtering (without high-Q VCO)
•
Constrained analog circuits
•
•
•
•
•
•
High supply/substrate
noise rejection
Low power
Fast locking
Clock recovery
•
•
•
•
Required for good jitter performance
Reduces power requirements
Reduced lock time (important for low power, low
bandwidth, and clock recovery applications)
Used for data communication applications
Disadvantages
No long-term or period jitter filtering
More difficult to avoid pattern jitter
Difficult to implement frequency spreading
Higher frequency overshoot
•
•
•
•
•
High phase noise
Not suitable for SONET transmit clocks
Narrow VCO frequency range
Requires a lot of characterization
Large area
Chip may be doomed without it
Increases jitter levels
Possible frequency
overshoot or instability
Typically have false lock problems
May need frequency acquisition aids
©M. S. Ramaiah School of Advanced Studies
7
FT13
Solution Procedure
Selection Criteria and Tradeoff in PLL features
Literature
Selection
Criteria
Review
PLL Design Specifications
PLL Concept and
PLL Design
its Advancements
Design Specifications for
individual blocks of PLL
PLL Architecture Selection
Architecture Selection for
each PLL block
VSD2537
Various PLL
DesignStates
Operating
Specifications
PLL Frequency
Spectrum
PLL
Types of PLL
Architectures
Architecture
Merits
& demerits
for blocks
GDSII Generation for PLL Design
OK
Not OK
Post-Layout Simulation
Parasitic Extraction from Layout
OK
Layout
Validations
Not OK
(DRC& LVS)
Layout design for individual Blocks
and integration for the entire PLL
Software Reference Modeling
for individual PLL Blocks
PLL Applications
Software
Use of Matlab for
Reference
Modeling
Design and Simulation of PLL design
Software Reference Modeling
for the complete PLL Design
Measurement of
Modeling for
PLL parameters
the PLL
Design and Simulation of schematic
of individual PLL Blocks
Pre-Interim
Post-Interim
©M. S. Ramaiah School of Advanced Studies
8
FT13
Design Specifications
VSD2537
The design specifications are evaluated based on the literature survey and the
architecture selected. The PLL specifications are
Architectural Specifications :
• A Digital PLL with a PFD and a Charge Pump with passive Filter
• Enhanced dual D-Flip Flop PFD to reduce Dead Zone and provide Adaptability
• Current Mode Charge Pump with 2nd Order loop filter to maintain simplicity
Functional Specifications:
• Reference Frequency – 10MHz
• VCO Free Running Frequency – 2.4GHz
• VCO Sensitivity – 155MHz/V
• Charge pump current - 100µA
• Jitter – 4.3ps
• 0.18µm CMOS Technology for implementation
• Operating Voltage – 1.8V
©M. S. Ramaiah School of Advanced Studies
9
FT13
VSD537
VSD2537
Reference Model
• Simulink toolbox in Matlab is used for drafting the reference model for PLL.
It provides a graphical mode of implementation.
The VCO output getting
stabilized in this region
Matlab Modeling for a PLL as Frequency Synthesizer
©M. S. Ramaiah School of Advanced Studies
10
FT13
Reference Model Simulation
VSD537
VSD2537
Matlab Modeling Results
©M. S. Ramaiah School of Advanced Studies
11
FT13
Target Specifications
VSD2537
Specifications for the Schematic Design:
• Reference Frequency – 10MHz
• VCO Free Running Frequency – 2.4GHz
• VCO Sensitivity – 155MHz/V
• Charge pump current - 100µA
• Jitter – 4.3ps
• 0.18µm CMOS Technology for implementation
• Operating Voltage – 1.8V
©M. S. Ramaiah School of Advanced Studies
12
FT13
Design of PLL as Frequency Synthesizer
VSD537
VSD2537
Input
10 MHz
Reference Design 1 [1]
Output
2.4 GHz
Design Selected for Implementation
Reference Design 2 [2]
Architecture of Charge Pump Phase Locked Loop as Frequency Synthesizer
•
Virtuoso Schematic Editor (VSE) is used for implementation of the architecture of PLL.
©M. S. Ramaiah School of Advanced Studies
13
FT13
VSD537
VSD2537
Design of PFD
Improves
linearity
near
Simple architecture
Reference Design
has only
the Matlab
stateis designed
using the invertedmodel and thesteady
schematic
output for reset logic
for the same and
analyzed
for the
Dead
zone exists,
reduced
simulation results.
to half reducing the width
Output is slow
of the related transistors
The classic Simple
architecture
Large dead zone
Reference Design 1 [25]
Reference Design 2 [4]
Referenced Design
Reference Design 3 [18]
Fast Frequency Acquisition
Selected – Reduces dead zone and provides
adaptability to the design
Uses NOR based logic with extra
inverters
Specification :
Sensitivity to
Matlab model has extra components that
increase the order of the PLL which detect 10KHz of
Phase difference
introduces stability concerns
at input.
Reference Design 4 [19]
Reference Design 5 [20]
Design Selected for Implementation
Architectures of PFD
•
VSE is used for implementation of the architecture of PFD.
©M. S. Ramaiah School of Advanced Studies
14
FT13
VSD537
VSD2537
Design of D-Flip-flop for PFD
Drawbacks of the
D-Flip Flop for the
use
in PFD
Reference Design –D-FF with clear
Design Selected for Implementation
using pass gates [25]
For Leading VCO phase,
DOWN pulse is generated
For Lagging VCO phase,
UP pulse is generated
For LOCK state,
NO control pulse is generated
The feedback from the output of the two
D-FFs returns back so quickly that the UP
and DOWN signal start toggling, together
with for
thetheclear
signal
when
both are high.
PFD Simulation results
selected
designresults
Simulation
for Updated Reference Design
Design of D-Flip flop with clear for PFD
•
VSE is used for implementation of the D-FF Design, and Spectre for simulations.
©M. S. Ramaiah School of Advanced Studies
15
FT13
Analysis for PFD at 10Mhz
VSD537
VSD2537
Decreasing
For
Lock State, duration of pulse generated varies in the range
of aInput
few psec analyzed against the variations in VDD
Frequency
10 to 9Mhz
PFD design
achieves the
Sensitivity of
10KHz for an
input
reference of
10MHz.
Increasing
Input
Frequency
10 to 11 MHz
For Increasing
Lock State, duration of pulse generated varies in the range
of a few
Feedback
psec analyzed against the variations in Temperature
Frequency
10 to 11 MHz
Decreasing
Feedback
Frequency
10 to 9 MHz
Analysis for PFD Sensitivity
•
Spectre is used for the simulation. The values are further plotted in Excel for comparison.
©M. S. Ramaiah School of Advanced Studies
16
FT13
VSD537
VSD2537
Design of Charge Pump
- Passive
Simple due to passive Selected
Specification :
filter – simple, and
filter
100µA of
Uses Current
current forSource
each
UP and DOWN
Uses Voltage source
Eminently
Practical
operation.
Reference Design 1 [5]
Complex due to active
filter and uses Voltage
source
Unnecessarily Complex
Reference Design 2 [5]
Reference Design 3 [5]
Uses Current source
Complex due to
active filter
Reference Design 4 [5]
Has zero static phase
offset at locked state
Provides testing
flexibility to the PLL
Static phase error minimized using
active current source
Does not provide
precise current
Adds complexities for by
adding extra circuitry
Adds complexities for by adding
extra circuitry
Reference Design 5 [4]
Referenced Design
Reference Design 6 [9]
Reference Design 7 [22]
Design Selected for Implementation
Architectures of Charge Pump
•
VSE is used for implementation of Charge Pump.
©M. S. Ramaiah School of Advanced Studies
17
FT13
VSD537
VSD2537
Analysis for Charge Pump
For Leading VCO phase,
DOWN pulse is generated
Positive current is
produced to increase
VCO control voltage
And negative current is
produced to reduce control
voltage for the VCO
For Lagging VCO phase,
UP pulse is generated
Analysis for Charge Pump controlled by PFD
•
Spectre is used for the simulation. The values are further plotted in Excel for comparison.
©M. S. Ramaiah School of Advanced Studies
18
FT13
VSD537
VSD2537
Design of VCO
+ Easier to derive multiple
bias
Design Equations for VCO + No tail currentThe
reference design does not provide the
+ Rejects high frequency
noise, reduce jitter
- Does not provide 50%
duty cycle
Reference Design 1 [2]
Referenced Design
+ Low gain
- High VCO sensitivity
Reference Design 4 [23]
clock frequencies
- Requires extranumber
period os stages of ring, which are tuned
for the required frequency
of 2.4GHz
to stablize
- Large area
due to the
metal coil
Reference Design 2 [10]
+ Eliminates
its own low
frequency
noise
- Larger area
due to three
inductors
Reference Design 3 [3]
Selected – Wide tuning range
and small area
- Needs Larger drain area to
reduce phase noise
Reference Design 6 [25]
Reference Design 5 [24]
Design Selected for Implementation
Architectures of VCO
•
VSE is used for implementation of VCO.
©M. S. Ramaiah School of Advanced Studies
19
FT13
VSD537
VSD2537
Analysis for VCO
Measurement of VCO time
period (free running
Linear Region of
frequency) to be 2.4 GHz.
Operation
Analyzing the
minimum control
voltage to start
Oscillations for
VCO.
Eye Diagram for
measurement of
VCO jitter = 2.1ps
Eye Diagram for
measurement of
VCO jitter.
Similarly the cutoff point for the
VCO Oscillations.
It is noted that the
cut-off point for
oscillations is less
than the respective
oscillation start
point.
Analysis for VCO
•
Spectre is used for the simulation. The values are further plotted in Excel for comparison.
©M. S. Ramaiah School of Advanced Studies
20
FT13
Design of Frequency Divider
VSD537
VSD2537
Truth Table for
Designing
Divide by 5
circuit
Design for DIV
by 250
Design for Divide by 5
Design for Divide by 2
Architecture of Frequency Divider
•
VSE is used for implementation of VCO.
©M. S. Ramaiah School of Advanced Studies
21
FT13
VSD537
VSD2537
Analysis for Frequency Divider
EXPOITING the limitation of Technology :
The 0.18µm CMOS
technology has a
limitation of 2GHz.
VCO can be
The first divide by 5 counter works as Divide by 6,Adesigned
and
which
provides 2.4GHz
the rest follows normally.
BUT
The total Frequency Divider operation is re structured
to
When a 2.4Ghz
signal comes at the
be as = 6 * 5 * 2 * 2 * 2
input , the circuit
= 240
responds slowly.
So, the Frequency Divider is re-designed.
Divide by 5 circuit
works like a divide
by 6 circuit.
Redesigned circuit for Divide by 240
Analysis for Frequency Divider
•
Spectre is used for the simulation.
©M. S. Ramaiah School of Advanced Studies
22
FT13
VSD537
VSD2537
Schematic for Charge Pump PLL
Charge Pump
PFD
Loop Filter
Input
10 MHz
Divide by 240
Top level PLL
Output
2.4 GHz
VCO
Complete Architecture of the Charge Pump Phase Locked Loop
•
Virtuoso Schematic Editor (VSE) is used for implementation of the architecture of PLL.
©M. S. Ramaiah School of Advanced Studies
23
FT13
Layout Implementation for CPPLL
Layout Methodology
VSD537
VSD2537
Charge Pump
PFD
Divide by 240
• The floorplanning for the PLL is done estimating the area of each
Loop Filter
block
• The layout forInputeach block
is tothe
be made
individually considering
NOW
layouts
CP
the abutments10Mhz
with the other cells
VCO
are to be stitched
by 240
• Divide
Individual
Layouts are validated for DRC and LVS
together
Outputthe complete design
• All blocks are integrated
together for
Top level PLL
2.4 GHz
LPFLVS
• The complete designPFD
is validated for DRC and
VCO
Complete Architecture of the Charge Pump Phase Locked Loop
•
Virtuoso Layout Editor (VLE) and VXL are used for implementation of the PLL Design
©M. S. Ramaiah School of Advanced Studies
24
FT13
Post Layout Simulations and Analysis
VSD537
VSD2537
Initially the PLL gets
a difference if phase
and frequency.
Initial Phase
Difference
Phase & Frequency matched
and Vctrl got constant
The Phase detector
detects the same &
controls the current
through the Charge
Pump.
The charge pump the
varies the control
voltage for VCO
accordingly.
Finally, the phase
and frequency is
matched and the
Vctrl also stabilizes.
Post Layout Simulation results for Charge Pump Phase Locked Loop
•
Spectre is used for the simulation. The values are further plotted in Excel for comparison.
©M. S. Ramaiah School of Advanced Studies
25
FT13
VSD537
VSD2537
Results and Discussion
1st Ref.
2nd Ref.
3rd Ref.
Design [23] Design [8] Design [3]
Matlab
Specs
PreLayout
Post
Layout
180nm
180nm
180nm
100nm
120nm
180nm
1.8V
1.8V
1.4-2.0V
1.2V
1.5V
1.6-2.0V
Reference Frequency
10MHz
10MHz
10MHz
500MHz
400MHz
25MHz
VCO Free Running Frequency
2.4GHz
2.4GHz
2.4GHz
2GHz
2.1GHz
2.4GHz
155MHz/V
768MHz/V
839MHz/V
2.6GHz/V
-
-
100µA
100µA
39.33µA
25µA†
24µA†
12.5µA†
RMS Jitter
4.3ps*
@2.4GHz
4.5ps
@2.4GHz
6.6ps
@2.4GHz
2.8ps
@2Ghz
0.74ps
@10MHz
3ps
@200MHz
Power Consumption
25mW*
@2.4GHz
13.41mW
@2.4GHz
17.68mW
@2.4GHz
30mW
@2GHz
32mW
@2GHz
20mW
@2.4GHz
Chip Area
0.25mm2*
0.25mm2*
9171.5µm2
0.15mm2
0.7mm2
0.7mm2
Parameter
Feature Size
Operating Voltage
VCO Sensitivity
Charge Pump Current
* These are the proposed values based on the analysis of reference designs.
† The current values are approximated based on the power and operating voltage, for comparison.
©M. S. Ramaiah School of Advanced Studies
26
FT13
Contribution against Challenges
VSD537
VSD2537
•
The general D-flip flop cannot be used with PFD as the reset signal makes the output of
PFD oscillating
» New D-flip flop based on NAND latch is designed for the requirement.
•
PFD is to be designed to reduce the dead zone
» Enhanced dual D-flip flop PFD used which also provides Adaptability
•
The 180nm CMOS technology has a limitation of 2GHz and VCO free running frequency of
2.4GHz is to be designed
» Ring-type VCO architecture selected and tuned for required specifications
•
Frequency divider of 240 is required to convert 2.4GHz signal to 10MHz in the technology
limited for 2GHz
» Limitation of technology exploited to use Div_by_200 circuit as Div_by_240
•
Reduce jitter for the design using a Ring-Oscillator VCO
» Test setup done to analyze PFD, Charge Pump and VCO at different PVTs
and tune the same
©M. S. Ramaiah School of Advanced Studies
27
FT13
Conclusion
VSD537
VSD2537
• The traditional D-Flip flop with clear cannot be used for PFD as the PFD
output goes in oscillating state after encountering 1-1 state at the output.
• Use of enhanced dual D-flip flop PFD reduces dead zone and helps to achieve
a sensitivity of 10KHz.
• Adding one bias transistor for each UP and DOWM loop improves the current
at the Charge pump output by 12%.
• The number of stages in the ring oscillator decide the VCO output frequency
while the wp and wn controls the tr and tf respectively. For equal tr and tf for
2.4Ghz output, 5-stage ring oscillator is used with wp= 3.7µm and wn=0.8µm.
• For the 0.18µm technology limited to 2GHz, a divide-by-200 counter operates
as divide-by-240.
• Low Jitter up to 6.6ps is achievable at 2.4Ghz with ring-oscillator type of
VCO by using the enhanced dual D-FF and current mode charge pump.
©M. S. Ramaiah School of Advanced Studies
28
FT13
Suggestions for future work
VSD2537
• The technology has limitation of 2.4Ghz. A mixer can be to mix the 2.4Ghz
VCO output signal with other low frequency. The output of mixer can be
filtered and provided to the frequency divider
• BIST can be implemented for PLL for better performance analysis
©M. S. Ramaiah School of Advanced Studies
29
FT13
References
VSD2537
1.
Zuoding Wang, “An analysis of charge-pump phase-locked loops”, IEEE
Transactions Circuits and Systems I, vol. 52, No. 10, pp. 2128-2138, October
2005
2.
Jaeha Kim, Mark A. Horowitz and Gu-Yeon Wei, “Design of CMOS AdaptiveBandwidth PLL/DLLs: A General Approach”, IEEE Transactions on Circuits
and Systems II: Analog and Digital Signal Processing, vol. 50, No. 11, pp. 860869, November 2003
3.
Nicola Da Dalt, Sven Derksen, Patrizia Greco, Christoph Sandner, Harald
Schmid and Klaus Strohmayer, “A Fully Integrated 2.4GHz LC-VCO
Frequency Synthesizer with 3-ps Jitter in 0.18µm Standard Digital CMOS
Copper Technology”, IEEE Transactions on Solid-State Circuits, vol. 37, No. 7,
pp. 959-962, July 2002
4.
John G. Maneatis, “Low-Jitter Process-Independent DLL and PLL based on
Self-Biased Techniques”, IEEE Transactions on Solid-State Circuits, vol. 31,
No. 11, pp. 1723-1732, November 1996
5.
Floyd M. Gardner, “Charge-Pump Phase-Lock Loops”, IEEE Transactions on
Communications , vol. 28, No. 11, pp. 1849-1858, November 1980
©M. S. Ramaiah School of Advanced Studies
30
FT13
References (cont …)
VSD2537
6.
Tian Jun, Wang Zhigong, Liang Bangli, Hu Yan, Shi Yi and Zheng Youdou, “A
Monolithic 1 GHz 0.6µm CMOS Low Jitter PLL”, Proceedinds of the 7th
International Conference on Solid-State and Integrated Circuits Technology
2004, pp. 1500-1503, October 2004
7.
Nicola Da Dalt, Edwin Thaller, Peter Gregorius and Lajos gazsi, “A Low Jitter
Triple-Band Digital LC PLL in 130nm CMOS”, Proceeding of the 30th
European Solid-State Circuits Conference 2004, pp. 371-374, September 2004
8.
Roberto Nonis, Nicola Da Dalt, Pierpaolo Palestri and Luca Selmi, “Modeling,
design and characterization of a new low jitter analog dual tuning LC-VCO
PLL architecture”, Proceedings of the International Symposium on Circuits and
Systems 2004, pp. IV - 553-556, May 2004
9.
Stefanous Sidiropoulos, Dean Liu, Jaeha Kim, Guyeon Wei and Mark
Horowitz, “Adaptive bandwidth DLLs and PLLs using regulated supply CMOS
buffers”, Symposium on VLSI Circuits 2000, pp. 124-127, June 2000
10. Floyd M. Gardner, “Charge-Pump Phase-Lock Loops”, IEEE Transactions on
Communications , vol. 28, No. 11, pp. 1849-1858, November 1980
©M. S. Ramaiah School of Advanced Studies
31
FT13
References (cont …)
VSD2537
11. Ronald E Best, “Phase-Locked Loops - Design Simulation and Applications”,
Mc-Graw Hill, 5e, ISBN: 0071412018, 2003
12. Dean Banerjee, “PLL Performance, Simulation and Design”, Dog Ear
Publishing, 4e, ISBN: 1598581341, 2002
13. Phase-Locked Loop Tutorial, PLL, “http://www.uoguelph.ca/antoon/gadgets/
pll/pll.html”, Last accessed on 12/11/2008
14. RFC Phase-Lock Loop, “https://intranet.insa-toulouse.fr/view/431/content/
rfc_phase_lock.html”, Last accessed on 18/11/2008
15. Selecting PLLs for ASIC Applications Requires Tradeoffs?, “http://www.
design-reuse.com/articles/?id=8865&print=yes”, Last accessed on 08/11/2008
16. SX1211: Lowest Power Integrated UHF Transceiver, Semtech,
“http://www.semtech .com/products/sx1211/?printable=true”, Last accessed on
18/11/2008
17. GPS Central (Canada) 'BSM Sentinel-FM'?, “http://www.gpscentral.ca/
products/bsm/bsm.htm”, Last accessed on 18/11/2008
©M. S. Ramaiah School of Advanced Studies
32
FT13
References (cont …)
VSD2537
18. G. B. Lee, P. K. Chan and L. Siek, “A CMOS Phase Frequency Detector for charge
pump Phase-Locked Loop”, 42nd Midwest Symposium on Circuits and Systems,
pp. 601-604, August 1999
19. Kun-Seok Lee, Byeong-Ha Park, Han-il Lee, and Min Jong Yoh, “Phase Frequency
Detectors for Fast Frequency Acquisition in Zero-dead-zone CPPLLs for Mobile
Communication Systems”, European Conference on Solid-State Circuits, pp. 1-4,
September 2003
20. S. Brigati, F. Francesconi, A. Malvasi, A. Pesucci and M. Poletti, “Modeling of
Fractional-N division frequency synthesizers with Simulink and Matlab”, The 8th
IEEE International Conference on Electronics, Circuits and Systems, vol. 2, pp.
1081-1084, September 2001
21. Sung-Hyun Yang, Younggap You and Kyoung-Rok Cho, “A New Dynamic D-FlipFlop Aiming at Glitch and Charge Sharing Free”, IEICE Transactions on
Electronics, vol. E86-C, no. 3, March 2003
22. Dieter Haerle, “Charge pump for PLL/DLL”, US007408391B2, August 05, 2008
©M. S. Ramaiah School of Advanced Studies
33
FT13
References (cont …)
VSD537
VSD2537
23. Koichiro Minami, Muneo Fukaishi, Masayuki Mizuno, Hideaki Onishi, Kenji
Noda, Kiyotaka Imai, Tadahiko Horiuchi, Hiroshi Yamaguchi, Takanori Sato,
Kazuyuki Nakamura and Masakazu Yaniashina, “A 0.l0µm CMOS, 1.2V, 2GHz
Phase-Locked Loop with Gain Compensation VCO”, IEEE Custom Integrated
Circuits Conference, pp. 213-216, May 2001
24. Pietro Andreani and Henrik Sjoland, “A 1.8GHz CMOS VCO with Reduced Phase
Noise”, Symposium on VLSI Circuits, pp. 121-122, June 2001
25. R. Jacob Baker, Harry W. Li and David E. Boyce, “CMOS – Circuit Design,
Layout, and Simulation”, IEEE Press, 2e, ISNB 0780334 167, 1998
26. “http://www.ece.stevens-tech.edu/~bmcnair/SwTh-Sum04/quiz4-with-answers.pdf#
search=%22divide%20by%205%20counter%22”, Last accessed on 26/01/2009
©M. S. Ramaiah School of Advanced Studies
34
FT13
VSD2537
Thank You
©M. S. Ramaiah School of Advanced Studies
35