Vol. 34, No. 1
Journal of Semiconductors
January 2013
A fully integrated multi-standard frequency synthesizer for GNSS receivers
with cellular network positioning capability
Li Bin(李斌), Fan Xiangning(樊祥宁)Ž , Li Wei(李伟), Zhang Li(章丽),
and Wang Zhigong(王志功)
Institute of RF- & OE-ICs, School of Information Science and Engineering, Southeast University, Nanjing 210096, China
Abstract: A fully integrated hybrid integer/fractional frequency synthesizer is presented. With a single multiband voltage-controlled-oscillator (VCO), the frequency synthesizer can support GPS, Galileo, Compass and TDSCDMA standards. Design is carefully performed to trade off power, die area and phase noise performance. By
reconfiguring between the integer mode and fractional mode, different frequency resolution requirements and a
constant loop bandwidth for each standard can be achieved simultaneously. Moreover, a long sequence length,
reduced hardware complexity multi-stage-noise-shaping (MASH) –† modulator is employed to reduce fractional
spur in the fractional mode. Fabricated in a 0.18 m CMOS technology, the frequency synthesizer occupies an
active area of 1.48 mm2 and draws a current of 13.4–16.2 mA from a 1.8 V power supply. The measured phase
noise is lower than –80 dBc/Hz at 100 kHz offset and –113 to –124 dBc/Hz at 1 MHz offset respectively, while the
measured reference spur is –71 dBc in integer mode and the fractional spur is –65 dBc in fractional mode.
Key words: multi-standard; frequency synthesizer; global navigation satellite system (GNSS); TD-SCDMA; cellular network positioning
DOI: 10.1088/1674-4926/34/1/015002
EEACC: 2570
1. Introduction
Currently, global positioning system (GPS) dominates the
market of satellite navigation, but other satellite navigation systems will soon be available, such as the Galileo system being
developed by the European Union and the Compass system
(also known as Beidou2) being developed by China. Moreover, the Federal Communications Commission (FCC) regulation (Enhanced 911) has also stated that all cellular devices
should be capable of determining their location with better than
100-m accuracyŒ1; 2 . Taking all this into account, especially
for accurate positioning inside a building or for personal navigation environments, hybrid Global Navigation Satellite System (GNSS) receivers in combination with cellular network
positioning capability, which provide seamless indoor/outdoor
navigation and communication capability, are attracting more
and more attention.
However, there are many challenges in the realization of
such hybrid receivers, especially in the design of a frequency
synthesizer, which should be able to generate clean and stable local oscillator (LO) signals fulfilling the stringent performance requirements imposed by each standard. First, to generate the required LO signals, the frequency synthesizer needs
to provide a very wide frequency tuning range. Although using
a set of voltage controlled oscillators (VCOs) or by multiplying, mixing, or dividing the VCO frequency we can solve this
problem, a large chip area and high power consumption make
it unattractive. Secondly, these standards are very different in
frequency resolution. It is hard to meet these frequency resolutions simultaneously by using an integer-N phase-locked-loop
(PLL), in which frequency resolution is limited by the reference frequency. Compared to the integer-N PLL, a fractionalN PLL allows a potentially arbitrary output frequency resolution and more freedom in the reference frequency choice,
but it suffers from a major drawback called fractional spur.
Thirdly, because of the wide frequency range, the synthesizer
loop bandwidth, which affects the phase noise optimization as
well as the loop stability, may vary quite significantly due to
the large range of N and large variation of VCO gainŒ3 .
To tackle these problems, in this paper, a hybrid integer/fractional frequency synthesizer, which supports GPS,
Galileo, Compass and TD-SCDMA standards, is designed and
implemented using a 0.18 m CMOS process. By reconfiguring between the integer mode for GPS/Galileo/Compass and
the fractional mode for TD-SCDMA, different frequency resolution requirements and a constant loop bandwidth for each
standard can be achieved simultaneously. The key aspects
in achieving these specifications are a programmable integer/fractional frequency divider together with variable reference frequency and programmable charge pump. In addition,
to reduce the chip area and power consumption, only a single
multi-band VCO using a switched capacitor resonator is used
to cover all the required frequency bands. To reduce fractional
spur in the fractional mode, the state of art multi-stage-noiseshaping (MASH) –† modulator is employed. Although this
structure has been proposed in Ref. [4], this paper presents the
first circuit implementation in frequency synthesizer. Moreover, the hardware required for this modulator is considerably reduced by recoding all carry-out signals from accumulatorsŒ5 .
* Project supported by the National Science and Technology Major Project, China (No. 2010ZX03007-002-01) and the State Key Development Program for Basic Research of China (No. 2010CB327404).
Ž Corresponding author. Email: xnfan@seu.edu.cn
c 2013 Chinese Institute of Electronics
Received 16 June 2012, revised manuscript received 10 July 2012
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J. Semicond. 2013, 34(1)
Standards
GPS/Galileo
Compass
TD-SCDMA
L1/E1
L5/E5a
L2/E5b
B1/B2
Li Bin et al.
Table 1. Specifications for the multi-standard frequency synthesizer.
Frequency range (MHz)
Frequency resolution (MHz)
Suitable architecture
1554.96
4.092
Low-IF
1155.99
4.092
Low-IF
1207.14/1186.68
4.092
Low-IF
1540.638/1186.68
4.092
Low-IF
1880–1900
0.2
Zero-IF
2010–2050
0.2
Zero-IF
IF (MHz)
20.46
20.46
20.46
20.46
N/A
N/A
2. Design considerations and synthesizer architecture
2.1. Frequency plan
The frequencies of the LO signals and thus the design of
the frequency synthesizer are strongly relevant to the adopted
receiver topology. When integrating a multi-standard receiver,
zero intermediate frequency (zero-IF) and low intermediate
frequency (low-IF) are the most promising architectures since
they are more capable for monolithic integration than other architectures. In the TD-SCDMA standard, the strong adjacent
channels combined with the limited achievable image rejection more or less dictate a zero-IF. On the other hand, a lowIF is attractive for the GPS, Galileo, and Compass standards
since it avoids the DC offset problem. Consequently, a reconfigurable zero/low-IF architecture seems to be a very promising
option to enhance the interoperability of the receiver. The frequency synthesizer presented in this paper will be designed to
fit in such a hybrid reconfigurable zero-IF/low-IF receiver, in
which zero-IF architecture is configured for the TD-SCDMA
and low-IF architecture for the GPS/Galileo/Compass with an
IF frequency of 20.46 MHz. Specifications in terms of the frequency tuning range and frequency resolution which should be
fulfilled are summarized in Table 1.
Fig. 1. Charge-pump PLL frequency synthesizer.
Fig. 2. The bode plot of jT .s/j.
T .s/ D
2.2. PLL loop bandwidth
The PLL bandwidth is an important design parameter and
must be carefully chosen. As a rule of thumb, to guarantee
loop stability, the bandwidth should be set at less than 10% of
the reference frequency. Moreover, the bandwidth also plays
an important role in the trade-off between phase noise performance and transition locking time. In order to achieve a better phase noise performance while maintaining loop stability
and satisfying the locking time requirements, the loop bandwidth needs to be optimized. However, in the multi-standard
frequency synthesizer, which usually means a wide frequency
output range, a large range of N and large variation of VCO
gain results in a huge variation of the loop bandwidth. This
creates serious problems for the loop stability and makes it
difficult to optimize the performance of the PLL. Therefore,
a constant PLL loop bandwidth for each standard is desirable
in multi-standard frequency.
Consider a general charge-pump PLL frequency synthesizer with a third-order loop filter. As shown in Fig. 1, it consists of a phase-frequency detector (PFD), a charge pump (CP),
a third-order passive loop filter, a VCO, and a divider. The frequency division ratio can be an integer or a fractional number.
The open-loop transfer function can be expressed as follows:
REF .s/
KVCO ICP H.s/
D
;
DIV .s/
2N s
(1)
where KVCO is the VCO gain, ICP is the CP current, N is the
divide ratio, and H (s) is the transfer function of the loop filter,
which is given by
H.s/ T2 s C 1
1
;
s ŒT2 .C1 =CT /s C 1 .T3 s C 1/ CT
(2)
where CT D C1 C C2 C C3 , T2 D R2 C2 , and T3 D R3 C3 .
The magnitude of T .s/.s D j!/ can be calculated as
v
u
KVCO ICP 1 u
1 C .!=!Z /2
t
h
ih
i;
jT .s/j D
2NCT ! 2
1 C .!=!P1 /2 1 C .!=!P2 /2
(3)
where !Z D 1=T2 , !P1 D CT =C1 T2 , !P2 D 1=T3 . Figure 2
shows the bode plot of jT .s/j. The unity gain frequency is denoted as !C , which is the same as the loop bandwidth in general
PLL design.
The variation factors in T .s/ are N , KVCO , ICP , and the
resistance and capacitance in the loop filter. The variation in
N , KVCO , and ICP , which are independent of the frequency,
makes the curve in Fig. 2 shift in the vertical without change
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J. Semicond. 2013, 34(1)
Li Bin et al.
Fig. 3. Block diagram of the multi-standard frequency synthesizer.
the zero and pole. To achieve a constant loop bandwidth, a constant KVCO ICP /N is desired while the loop filter is fixed. In our
design, we reduce the variation of the loop bandwidth by adjusting only ICP . Specially, the following condition
ICP / N=KVCO ;
(4)
would maintain a constant loop bandwidth.
Fig. 4. Complete schematic of the multi-band VCO.
3. Circuit implementation
2.3. Synthesizer design
According to the design specifications, an integer-N PLL
with a 200 kHz reference frequency would require division ratio N to be in excess of 10000. Such a high N leads to a high
in-band phase noise and charge pump current. Although a fractional one can release this constraint, is suffers from fractional
spur. On the other hand, since a wide output frequency range
is required, a single reference frequency may result in very different frequency division ratio N . Large variation of N results
in a PLL loop bandwidth that also varies significantly. It gives
problems for the loop stability and makes it difficult to optimize phase noise as well as lock time.
To tradeoff power, area, and phase noise performance,
a hybrid integer/fractional frequency synthesizer with a variable reference frequency and programmable CP current is employed. Figure 3 illustrates the synthesizer design, which is
based on a single type-II fourth-order PLL. A multi-band VCO,
which operates at the double frequency of the received signal, is used as the oscillation source to avoid VCO pulling.
A divide-by-two circuit connecting to the VCO is used to
generate the quadrature LO signals. To satisfy different frequency resolution requirements, a programmable hybrid integer/fractional frequency divider is employed. Accordingly, the
frequency synthesizer has two modes, i.e. the integer mode
and the fractional mode. For GPS/Galileo/Compass, an integer divider is used, with a reference frequency of 4f0 (f0 D
1.023 MHz). For TD-SCDMA, a 3rd –† modulator with 20bit input is added to modulate the integer-N frequency divider
so that the fractional frequency step resolution can be obtained.
With a reference frequency of 7f0 , a frequency resolution less
than 8 Hz can be achieved. To compensate loop bandwidth
variation, a programmable CP is also adopted. Channel selection and other control signals are provided through digital
logic.
3.1. Multi-band VCO
The VCO is the most critical block in the frequency synthesizer. The two main requirements in our design for the VCO
are low phase noise and wide tuning range. To cover the required frequency range, a multi-band VCO is employed since
a continuous tuning range covering all frequency bands is not
necessary in our design.
Figure 4 shows the complete schematic of the multi-band
VCO, which adopts a cross-coupled complementary topology
without a tail current source. Complementary cross-coupled
transistors M1–M4 are to generate the negative resistance to
compensate for the losses in the LC-tank. The transconductance of the negative resistance is chosen so that the DC voltage
at each side of the tank is maintained at approximately VDD /2.
Biasing this node at VDD /2 allows the oscillation waveform
to be very symmetric, which is beneficial for a low close-in
phase noise performance. To widen the frequency tuning range,
two switched capacitor arrays are used. Switching operation
between different bands with a large frequency shift is realized by a band switched capacitor array, which is controlled
via the band-select-code (BSC). Moreover, to achieve enough
frequency tuning range in each band, a 3-bit binary weighted
switched capacitor array controlled by the frequency-controlcode (FCC) is also used and results in eight tuning curves in
each band. All capacitors used in the switched capacitor array
are metal-to-metal capacitors so as not to degrade the quality
factor of the LC tank. A symmetric octagonal spiral inductor
is used in the LC tank to ensure high quality factor as well as
small chip area. The inductance value is about 1.2 nH and has
a relatively high quality factor (> 10) in the target frequency
range.
To lower phase noise, two noise filtersŒ6 are placed at the
VCO core virtual node to eliminate substrate noise and supply
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J. Semicond. 2013, 34(1)
Li Bin et al.
Fig. 6. Programmable integer/fractional frequency divider.
Fig. 5. Simulated C –V characteristics and Ceff /A of the distributed varactor.
noise at twice the oscillation frequency. In order to meet the
multi-band frequency resonating characteristics, two switched
capacitance arrays are added at the VCO core virtual node to
compensate the node capacitance and allow the virtual node to
oscillate at twice the resonant frequency over the entire tuning
range.
Commonly, fine tuning is achieved by an accumulation
varactor, which exhibits a serious nonlinearity in its C –V characteristic curve. An undesirable side effect associated with
highly nonlinear varactors is that the output frequency depends
not only on the control voltage but also on the amplitude of oscillation. This mechanism, known as amplitude-to-phase (AMPM) noise conversion, is a significant source of VCO phase
noise. According to Ref. [7], the sensitivity of AM-PM is determined by the sensitivity of the varactor’s effective capacitance
(Ceff / to the oscillation amplitude (A), which can be approximated as:
s
Ceff
Cmax Cmin 2Veff
Veff 2
D
:
(5)
1
A
A2
A
Cmax and Cmin are the maximum and minimum smallsignal capacitance of the varactor. Veff is the effective bias voltage of varactor.
Thus, a small sensitivity of Ceff /A is desirable for a reduction in AM-to-PM conversion. To achieve this goal, a distributed varactorŒ8 , in which three varactors with different DC
bias voltages are shunted together, is adopted for fine tuning.
Rather than using a fixed DC bias voltage (i.e., Vb1 D Vb2 D
Vb3 /, the distributed varactor uses different voltage values for
Vb1 , Vb2 , and Vb3 . As a result, the nonlinearities of the three varactors are cancelled. Figure 5 shows the simulated C –V characteristics and the sensitivity of Ceff /A when the DC bias
voltage (Vb1 , Vb2 , and Vb3 / is set at different value sets. A linear varactor can be obtained while the DC bias voltage (Vb1 ,
Vb2 , and Vb3 / is set to be (0.2 V, 0.8 V, and 1.4 V). In addition,
the sensitivity of the Ceff /A is also reduced, leading to a
reduction in AM-to-PM conversion.
3.2. Programmable integer/fractional frequency divider
Figure 6 depicts the block diagram of the programmable
integer/fractional frequency divider. As the key building block
Fig. 7. Block diagram of MASH 1-1-1.
Fig. 8. EFM structure of each stage.
in the proposed frequency synthesizer, it consists of an integerN frequency divider, a 3rd –† modulator, and the control
circuits necessary for mode and channel selection. The operational mode is selected according to the mode select signal
(MS) value: integer mode (MS D 1) or fractional mode (MS D
0).
For the integer-N frequency divider, pulse swallow architecture is adopted since it allows high operation frequency as
well as low power consumption. It includes a dual-modulus
prescaler (DMP), a pulse counter, and a swallow counter. The
division ratio is M D PN C S . In order to cover our required
division ratio range, P is set to be 32 to 47; S is set to be 0 to 15,
while the division ratio of DMP is chosen to be 16/17. Thus,
the division ratio can change from 512 to 1023.
In the fractional mode, the integer-N divider is modulated
by the 3rd –† modulator for fractional division operation.
Since the intrinsic division ratio of the integer-N divider is
still an integer, the quantization noise is inevitably introduced,
and hence, directly affects the frequency synthesizer’s spectral purity. To reduce spurs in the total phase noise of the PLL,
the state of the art MASH 1-1-1 structureŒ4 is used for good
shaping the quantization noise. As shown in Fig. 7, it cascades
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J. Semicond. 2013, 34(1)
Li Bin et al.
Fig. 9. Circuit implementation of the MASH 1-1-1.
three error-feedback-modulators (EFMs) by connecting both
the output and the quantization error to the input of the nextstage EFM. Each EFM constituting the proposed MASH 1-1-1
takes two inputs and generates two outputs to be fed to the next
EFM, as shown in Fig. 8.
Figure 9 illustrates the circuit implementation of the
MASH 1-1-1. The accumulator is used as the digital implementation of the EFM. Each accumulator employs a pipelined
20 bit adder with carry input and a 20 bit register. In order to
provide synchronization among every carry-out signal, three 1bit registers are inserted between the accumulators and errorcancellation-unit (ECU).
To speed up the process and to reduce hardware complexity, four cascaded 5 bit carry-skip-ahead (CSA) adders are used
to realize the 20 bit adder. A 1-bit register is inserted between
each CSA stage to pipeline the 20 bit adder. In addition to this,
we also added an additional 5 bit register to provide time alignment between the input and the output. The bits of both inputs
of the adder should be appropriately delayed to synchronize
them with the true carry signals, conversely, the output bits are
realigned in time by likewise employing the appropriate delays.
The ECU performs the specification of canceling the quantization noise from the front two stages and produces a 3-bit
wide output. It can be realized as two adder-substractor units. If
the carry-out signal ci from every accumulator is treated as 1
and 0 instead of as 1 and 0, such as in the conventional onesŒ5 ,
the value sets of two adder-substractor units should be f 2, 1,
0, 1g and f 4, 3, 2, 1, 0, 1, 2, 3g instead of f 1, 0, 1, 2g
and f 3, 2, 1, 0, 1, 2, 3, 4g. For two’s complement arithmetic, the two adder-substractor units should be 2 and 3 bits
wide while they are 3 and 4 bits wide in conventional ones. As
a result, less logic gates are required to realize it, as the fewer
number of bits required reduces the corresponding hardware
complexity. Since the output of the proposed MASH 1-1-1 is
a signed 3 bits number between 4 and 3, which is exactly opposite to the output of the traditional MASH 1-1-1, in order
to control the integer-N divider, it has to convert it into eight
consecutive unsigned binary numbers. In this paper, we code
the output bits in descending order, the corresponding encoder
needs only two inverts and the final binary control word should
be equal to y2y1y0.
3.3. Other blocks
The divider-by-two circuit is directly connected to the
VCO to provide quadrate outputs, and its operating frequency
Fig. 10. Schematic of the divider-by-two circuit.
should be as high as 4.2 GHz. So the most important features of
the divider-by-two circuit are high speed and good orthogonality. Figure 10 shows the structure of the divide-by-two circuit.
Master-slave flip–flop based on source-coupled-logic (SCL) is
adopted to achieve a good performance. The out-phase output
of the slave flip–flop is fed back to the in-phase input of the
master flip–flop to halve the input frequency.
The phase-frequency-detector (PFD) employed in this frequency synthesizer is a conventional tri-state machine structure
and consists of two D-flip–flops and a NOR gate in the asynchronous reset path, as shown in the left of Fig. 11. The delay of
the NOR gate is adjusted to guarantee a 250 ps on-state pulse
width to eliminate the dead zone. The programmable charge
pump circuit depicted in the middle of Fig. 11 uses a source
switching topology. To improve the matching of the source and
sink currents, cascade structures are used due to high output
impedance. The total output charging pump and discharging
current of the CP is adjusted by digital signal S1S0 to maintain
a constant KVCO ICP /N for each standard. The LPF used in this
synthesizer is a third-order passive resistance-capacitance filter, as shown in the right of Fig. 11. The design parameters are
listed as follows: R1 D 46 k, C1 D 147.5 pF, C2 D 9.2 pF,
R3 D 92 k, C3 D 0.6 pF.
4. Measurement results
The proposed frequency synthesizer has been fabricated
in a 0.18 m CMOS technology, with all circuits blocks integrated on the chip. The die microphotograph of the chip is
shown in Fig. 12. The total chip size is 1.47 1.38 mm2 , with
an active core area of 1.48 mm2 .
With a supply of 1.8 V, current consumption is measured
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J. Semicond. 2013, 34(1)
Li Bin et al.
Fig. 11. Schematic of PFD, CP, and the third-order loop filter.
Table 2. Summary of the measurement results.
Parameter
Value
Technology
0.18 m 1P6M CMOS
VCO frequency range (GHz)
2.26–2.48
2.48–2.78
2.94–3.38
3.45–4.23
Phase noise (dBc/Hz)
< 80 @ 100 kHz
–113 to –124 @ 1 MHz
Reference spur (dBc)
–71 (Integer mode)
Fractional spur (dBc)
–65 (Fractional mode)
Loop bandwidth (kHz)
100
Locking time (s)
< 30
Voltage supply (V)
1.8
Current consumption (mA)
14.9–16.2 (Integer mode)
13.4 (Fractional mode)
Area (mm2 /
1.42
Fig. 12. Chip photo of the frequency synthesizer.
Fig. 13. Measured tuning characteristic of the VCO.
for different standards. For TD-SCDMA mode, the total current consumption is 13.4 mA. For other supported standards,
the current consumption is from 14.9 to 16.2 mA. The output spectrum of multi-band VCO is measured by an Agilent
E4400A spectrum analyzer. Figure 13 shows its frequency tun-
ing curves. With the 5 bit control signal, the VCO exhibits
a tuning of 2.26 to 2.48 GHz, 2.48 to 2.78 GHz, 2.94 to
3.38 GHz, and 3.45 to 4.23 GHz, which is enough for its applications. It should be noted that the VCO demonstrates a linear tuning characteristic that validates the varactor linearization
technique. From the tuning curves, the VCO gain is calculated
and varies from 25 to 127 MHz/V.
The frequency synthesizer phase noise measurement is
also carried out by an E4400A spectrum analyzer. Figure 14
shows four example phase noise plots for each standard. The
phase noise is from 113 to 124 dBc/Hz at a 1 MHz offset and the in-band phase noise is less than 80 dBc/Hz at
a 100 kHz offset. The measured reference spur in the integer
mode is about 71 dBc, as shown in Fig. 15. Figure 16 shows
that the measured out-of-band fractional spur is 65 dBc in
fractional mode. The locking time of the frequency synthesizer
is measured by a Tektronix MSO71254C mixed signal oscilloscope. Figure 17 shows the transient response at the loop filter
output when the target frequency is 1155.99 MHz and 1900
MHz respectively. Since the loop bandwidth is approximately
equal to 100 kHz in the two modes, a similar locking time can
be observed.
Table 2 summarizes the measured results mentioned
above. Table 3 compares the presented synthesizer with recently published multi-standard frequency synthesizer. Com-
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J. Semicond. 2013, 34(1)
Li Bin et al.
Fig. 14. Phase noise measurement results.
Fig. 15. Measured reference spurs.
Fig. 17. Measured locking process in fractional mode and integer
mode.
pared to other published works, the presented synthesizer
shows a wider output frequency range and supports more standards, while providing a reasonable phase noise performance.
Although the current consumption is comparatively higher, it
can be lowered using more advanced technology.
5. Conclusions
Fig. 16. Measured fractional spurs.
A fully integrated multi-standard frequency synthesizer for
a combined GNSS receiver with cellular network positioning
capability is presented. The frequency synthesizer supports the
standards of GPS, Galileo, Compass, and TD-SCDMA. Design
is carefully performed to ensure that the synthesizer meets the
different frequency resolution requirements and at the same
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J. Semicond. 2013, 34(1)
Parameter
Technology*
Supply (V)
Current (mA)
Support standards
Phase noise (dBc/Hz)
Li Bin et al.
Table 3. Performance comparison with other published works.
Ref. [10]
Ref. [11]
Ref. [12]
Ref. [13]
0.18 m
0.18 m
0.13 m
0.13 m
1.8
1.8
1
1.2
6.2
21
4.5
8.6
GPS L1
WCDMA
GPS L1/L2/L5
GPS L1
Galileo E1
Bluetooth
Galileo
Compass B1
Compass B1
ZigBee
E1/E5a/E5b
Compass
B1/B2
GlONASS
L1/L2
–92 @ 100 kHz –95 @ 200 kHz –80 @100 kHz –93 @ 10 kHz
–93 @100 kHz
–115 @ 1 MHz –118 @ 1 MHz –115 @ 1 MHz –118 @ 1 MHz –117 @ 1 MHz
Ref. [9]
0.13 m
1.2
0.93
GPS L1/L5
Reference spur (dBc)
–71
N/A
N/A
–70
–55
Area (mm2 /
NA
0.53
2.1
0.5
0.92
This work
0.18 m
1.8
13.4–16.2
GPS L1/L2/L5
Galileo
E1/E5a/E5b
Compass B1/B2
TD-SCDMA
< 80 @100 kHz
–113 to –124 @
1 MHz
–71
(Integer mode)
1.42
*All implemented in the CMOS process.
time achieves a constant loop bandwidth for each standard.
Fabricated in a 0.18 m CMOS process, the synthesizer occupies an active area of 1.42 mm2 and draws a current of
13.4–16.2 mA from a 1.8 V power supply. Measurement results show that the synthesizer works well and can be used for
the standards mentioned above.
Acknowledgement
We are grateful for the encouraging discussions and technique assistance of the whole team at the Institute of RF- &
OE-ICs, Southeast University.
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