Topics Design rules and fabrication SCMOS scalable design rules Stick diagrams What is “Design Rules”? Design rules determine low-level properties of chip design – – – – Rules about layout of the design Spacing Electrical connection Composition rules » Poly and diff extensions to ensure transistor is well formed – How small a transistor, wire, or via can be made? – Trade-off between integration and fabrication errors » Manufacturing processes have inherent limitations in accuracy » Specify geometry of masks which will provide reasonable yields – Most design rules are based on experience Copyright 1998, 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapter 2 Manufacturing problems Variations in material deposition Variations in temperature Variations in oxide thickness Impurities … Transistor problems Copyright 1998, 2002 Prentice Hall PTR Variations in threshold voltage: – oxide thickness – ion implantation – poly variations Modern VLSI Design 3e: Chapter 2 Copyright 1998, 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapter 2 Changes in source/drain diffusion overlap Variations in substrate Modern VLSI Design 3e: Chapter 2 Wiring problems Diffusion: Poly, metal: – variations in height, width variations in resistance, cap Oxide problems Variations in height Lack of planarity – changes in doping variations in resistance, caps Copyright 1998, 2002 Prentice Hall PTR metal 2 metal 2 metal 1 Shorts and opens: Modern VLSI Design 3e: Chapter 2 Copyright 1998, 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapter 2 Copyright 1998, 2002 Prentice Hall PTR Via problems Via may not be cut all the way through Undersize via has too much resistance Via may be too large and create short Copyright 1998, 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapter 2 MOSIS SCMOS design rules Designed to scale across a wide range of technologies Designed to support multiple vendors Designed for educational use fairly conservative Copyright 1998, 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapter 2 λ and design rules λ is the size of a minimum feature Specifying λ particularizes the scalable rules Parasitics are generally not specified in λ units Wires Copyright 1998, 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapter 2 6 metal 3 3 metal 2 3 metal 1 3 pdiff/ndiff 2 poly Copyright 1998, 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapter 2 Transistors 2 3 Vias 2 Types of via: metal1/diff, metal1/poly, metal1/metal2. 4 3 4 1 1 2 5 Modern VLSI Design 3e: Chapter 2 Copyright 1998, 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapter 2 Copyright 1998, 2002 Prentice Hall PTR Metal 3 via Tub tie Type: metal3/metal2 Rules: 4 1 – cut: 3 x 3 – minimum spacing: 3 –… Modern VLSI Design 3e: Chapter 2 Copyright 1998, 2002 Prentice Hall PTR Copyright 1998, 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapter 2 Spacing Diffusion/diffusion: 3 Poly/poly: 2 Poly/diffusion: 1 Via/via: 2 Metal1/metal1: 3 Metal2/metal2: 4 Metal3/metal3: 4 A stick diagram is a cartoon of a layout. Does show all components/vias (except possibly tub ties), relative placement. Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries. Modern VLSI Design 3e: Chapter 2 Stick diagrams Copyright 1998, 2002 Prentice Hall PTR Stick layers metal 3 Copyright 1998, 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapter 2 Dynamic latch stick diagram VDD metal 2 metal 1 in poly out ndiff pdiff VSS phi’ Modern VLSI Design 3e: Chapter 2 Copyright 1998, 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapter 2 phi Copyright 1998, 2002 Prentice Hall PTR Sticks design of multiplexer NAND sticks VDD Start with NAND gate: a + out out b a b VSS Copyright 1998, 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapter 2 Copyright 1998, 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapter 2 One-bit mux sticks VDD How to build one-bit mux from NAND gate? ai bi a select’ – Inputs: ai, bi – Selector: select – Output: oi a out N1 (NAND) a out select One-bit mux sticks N2 (NAND) out N3 (NAND) » oi = NAND( NAND(ai,select),NAND(bi,select’) ) b b b VSS Copyright 1998, 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapter 2 Modern VLSI Design 3e: Chapter 2 3-bit mux sticks select’ b2 ai bi a1 b1 ai bi a0 ai b0 bi Layout design and analysis tools select select’ a2 Copyright 1998, 2002 Prentice Hall PTR select m2(one-bit-mux) select’ select m1(one-bit-mux) select’ Modern VLSI Design 3e: Chapter 2 select m0(one-bit-mux) VDD oi VSS Layout editors are interactive tools Design rule checkers are generally batch--identify DRC errors on the layout. Circuit extractors extract the netlist from the layout. Connectivity verification systems (CVS) compare extracted and original netlists. o2 VDD oi VSS o1 VDD oi VSS o0 Copyright 1998, 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapter 2 Copyright 1998, 2002 Prentice Hall PTR