Testing (selected from Chapters
4, 5, 7, and 10)
Fault models.
■ Testing of combinational circuits.
■ Testing of sequential circuits.
■
Manufacturing testing
Errors are introduced during manufacturing.
■ Testing verifies that chip corresponds to
design.
■ Varieties of testing:
■
– functional testing;
– performance testing (binning chips by speed).
■
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Testing also weeds out infant mortality.
Revised by SG: January 18, 2004
Modern VLSI Design 3e: Testing (from Chapters 4, 5, 7 & 10)
Testing and faults
■
Fault model:
Copyright  1998, 2002 Prentice Hall PTR
Stuck-at-0/1 faults
Stuck-at-0/1: logic gate output is always
stuck at 0 or 1, independent of input values.
■ Correspondence to manufacturing defects
depends on logic family.
■ Experiments show that 100% stuck-at-0/1
fault coverage corresponds to high overall
fault coverage.
■
– possible locations of faults;
– I/O behavior produced by the fault.
Good news: if we have a fault model, we
can test the network for every possible
instantiation of that type of fault.
■ Bad news: it is difficult to enumerate all
types of manufacturing faults.
■
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Modern VLSI Design 3e: Testing (from Chapters 4, 5, 7 & 10)
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Testing procedure
■
Testing procedure:
– set gate inputs;
– observe gate output;
– compare fault-free and observed gate output.
■
Test vector: set of gate inputs applied to a
system.
Revised by SG: January 18, 2004
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Page 5
Copyright  1998, 2002 Prentice Hall PTR
Stuck-at faults in gates
a
0
0
1
1
Three ways to test NAND for stuck-at-0,
only one way to test it for stuck-at-1.
■ Three ways to test NOR for stuck-at-1, only
one way to test it for stuck-at-0.
Revised by SG: January 18, 2004
Modern VLSI Design 3e: Testing (from Chapters 4, 5, 7 & 10)
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Copyright  1998, 2002 Prentice Hall PTR
OK
1
1
1
0
SA0
0
0
0
0
SA1
1
1
1
1
a
0
0
1
1
b
0
1
0
1
NAND
Revised by SG: January 18, 2004
Modern VLSI Design 3e: Testing (from Chapters 4, 5, 7 & 10)
Testing single gates
■
b
0
1
0
1
OK
1
0
0
0
SA0
0
0
0
0
SA1
1
1
1
1
NOR
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Testing combinational networks
■
100% coverage: test every gate for
– stuck-at-0;
– stuck-at-1.
Assume that there is only one faulty gate
per network.
■ Most networks require more than one test
vector to test all gates.
■
Revised by SG: January 18, 2004
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Copyright  1998, 2002 Prentice Hall PTR
Multiple test example
Example
Can test both NANDs for stuck-at-0
simultaneously (abc = 000).
■ Cannot test both NANDs for stuck-at-1
simultaneously due to inverter. Must use
two vectors.
■ Each extra vector means longer testing time,
longer tester occupation, higher costs.
■ Must also test inverter.
■
Revised by SG: January 18, 2004
Modern VLSI Design 3e: Testing (from Chapters 4, 5, 7 & 10)
Page 9
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Revised by SG: January 18, 2004
Modern VLSI Design 3e: Testing (from Chapters 4, 5, 7 & 10)
Combinational network testing
Two parts to testing:
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Copyright  1998, 2002 Prentice Hall PTR
Test generation (Chapter 10)
Automatic test pattern generation (ATPG)
generates a set of test vectors for a Boolean
network (combinational ATPG) or
sequential machine (sequential ATPG).
■ D notation allows to quickly denote fault:
■
– controlling the inputs of (possibly interior)
gates;
– observing the outputs of (possibly interior)
gates.
– D value on a node means that the signal is 0 in
good and 1 in faulty circuit at that point.
– D’ value is the opposite: 1 in good, 0 in faulty.
Revised by SG: January 18, 2004
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Copyright  1998, 2002 Prentice Hall PTR
Revised by SG: January 18, 2004
Modern VLSI Design 3e: Testing (from Chapters 4, 5, 7 & 10)
Page 12
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PODEM (path-oriented
decision making) algorithm
Goal: propagate D (or D’) value to primary
outputs.
■ PODEM performs combinational test
generation. Uses implicit enumeration.
■ Uses five values: 0, 1, D, D’, and X. Start
all values at X.
■ In worst case, must examine all possible
inputs, but can be implemented to run
quickly.
Fault propagation example
■
Revised by SG: January 18, 2004
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Copyright  1998, 2002 Prentice Hall PTR
Fault propagation example,
cont’d
step 2
Revised by SG: January 18, 2004
Modern VLSI Design 3e: Testing (from Chapters 4, 5, 7 & 10)
start
step 1
Revised by SG: January 18, 2004
Modern VLSI Design 3e: Testing (from Chapters 4, 5, 7 & 10)
Page 14
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Combinational testing example
step 3
Page 15
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Revised by SG: January 18, 2004
Modern VLSI Design 3e: Testing (from Chapters 4, 5, 7 & 10)
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Copyright  1998, 2002 Prentice Hall PTR
Testing procedure
Goal: test gate D for stuck-at-0 fault.
■ First step: justify 0 values on gate inputs.
■ Work backward from gate to primary
inputs:
■
– w1 = 0 (A output = 0);
– i1 = i2 = 1.
■
Testing procedure, cont’d
■
– o1 gives different values if D is true/faulty.
■
– i3 = i4 = 1.
Revised by SG: January 18, 2004
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Copyright  1998, 2002 Prentice Hall PTR
a
SA1
SA0
b
In general, may have to propagate fault
through multiple levels of logic to primary
outputs.
Revised by SG: January 18, 2004
Modern VLSI Design 3e: Testing (from Chapters 4, 5, 7 & 10)
Fault masking
Redundant logic can mask faults:
Work forward and backward:
– F’s other input must be 0 to detect true/fault.
– Justify 0 at E’s output.
– Final result: i5 = 1; i6 = i7 = 0; i8 = don’t care.
■
Similarly:
Observe the fault at a primary output:
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Copyright  1998, 2002 Prentice Hall PTR
Redundancy example
Testing NOR for SA0 requires setting both
inputs to 0.
■ Network topology ensures that one NOR
input will always be 1.
■ Function reduces to 0:
■
– f = ((ab)’ + b)’ = (a’ + b’ + b)’ = 0.
Revised by SG: January 18, 2004
Modern VLSI Design 3e: Testing (from Chapters 4, 5, 7 & 10)
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Copyright  1998, 2002 Prentice Hall PTR
Revised by SG: January 18, 2004
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Redundancies and testing
Redundant logic cannot be controlled.
■ Observations requiring control of redundant
logic may not be possible.
■ Redundant logic should be minimized to
eliminate redundancy. Redundancies can
introduce delay faults and other problems.
■
Revised by SG: January 18, 2004
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Stuck-at-open/closed model
■
Revised by SG: January 18, 2004
Modern VLSI Design 3e: Testing (from Chapters 4, 5, 7 & 10)
Stuck-open behavior
If t1 is stuck-open (switch cannot be closed),
there can be no path from VDD to output
capacitance. So, stuck-open is equivalent to
stuck-at-0 in this case.
■ If t2 is stuck-open, the output can be
discharged when a=1, but not when b=1.
■
Revised by SG: January 18, 2004
Modern VLSI Design 3e: Testing (from Chapters 4, 5, 7 & 10)
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Copyright  1998, 2002 Prentice Hall PTR
Models transistors always on/off.
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Copyright  1998, 2002 Prentice Hall PTR
Fault models in practice
In spite of the existence of many fault
models, the only fault model that is used in
practice is the stuck-at model due to its
simplicity.
■ Many test vectors that are developed for the
stuck-at model also detect other type of
defects.
■
Revised by SG: January 18, 2004
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Copyright  1998, 2002 Prentice Hall PTR
Delay fault
■
Delay falls outside acceptable limits:
– gate delay fault assumes that all delays are
lumped into one gate;
– path delay fault models delay problems along
path through network.
■
Delay problems reduce yield:
– performance problems;
– functional problems in some types of circuits.
Revised by SG: January 18, 2004
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Copyright  1998, 2002 Prentice Hall PTR
Sequential testing
Much harder than combinational testing—
can’t set memory element values directly.
■ Must apply sequences to put machine in
proper state for test, be able to observe
value of test.
■ Or, one must use design-for-testability
techniques: add a scan path.
■
Revised by SG: January 18, 2004
Modern VLSI Design 3e: Testing (from Chapters 4, 5, 7 & 10)
Page 26
Scan flip-flop
Copyright  1998, 2002 Prentice Hall PTR
Scan chain
D
Q/scan_out
D
D
Q/scan_out
0
Q/scan_out
1
scan_in
D
■
scan_mode
Revised by SG: January 18, 2004
Modern VLSI Design 3e: Testing (from Chapters 4, 5, 7 & 10)
scan_in
scan_in
Q
φ
Page 27
Normal flip-flop
behavior when
scan_mode = 0.
Copyright  1998, 2002 Prentice Hall PTR
scan_mode
■
φ
scan_mode
φ
Connect successive scan_outs to scan_ins.
Revised by SG: January 18, 2004
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Copyright  1998, 2002 Prentice Hall PTR
Scan-based testing (1)
When all flip-flops have been incorporated
in a scan chain, they become part of a shift
register.
■ In scan mode, any desired pattern can be
shifted in.
■ By disabling scan mode for one clock cycle
the combinational circuit response to the
pattern can be captured in the flip-flops.
■
Scan-based testing (2)
Primary inputs
■
The response
can be shifted
out and
analyzed.
memory
chip scan_in
Revised by SG: January 18, 2004
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Copyright  1998, 2002 Prentice Hall PTR
Revised by SG: January 18, 2004
Modern VLSI Design 3e: Testing (from Chapters 4, 5, 7 & 10)
Partial scan
Full scan is expensive—must roll out and
roll in state many times during a set of tests.
■ Partial scan selects some registers for
scanability.
■ Requires analysis to choose which registers
are best for scan.
■
Revised by SG: January 18, 2004
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Copyright  1998, 2002 Prentice Hall PTR
Primary outputs
Combinational
logic
Page 30
chip scan_out
Copyright  1998, 2002 Prentice Hall PTR
Boundary scan (Chapter 7)
Boundary scan is a technique for testing
chips on boards. Pads on chips are arranged
into a scan chain that can be used to observe
and control pins of all chips.
■ Requires some control circuitry on pads
along with an on-chip controller and
boundary-scan-mode control pins.
■
Revised by SG: January 18, 2004
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Copyright  1998, 2002 Prentice Hall PTR