Topics
■
Leftover from last class
– Combinational logic network delay (4.4)
» Fanout
» Path delay model
Alternative gate circuits (§3.5)
■ Switch logic (§3.4, §4.7)
■ Power issues (§3.3.5, §3.6)
■
Modern VLSI Design 3e: Chapter 3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Fanout
Fanout adds capacitance
■ How to drive large
fanouts
■
sink
– Increase the size of
source
driver transistors
– Add intermediate buffers
Modern VLSI Design 3e: Chapter 3
sink
sink
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Intermediate Buffers
■
Reconstruction
of circuit is
needed in
some cases
Modern VLSI Design 3e: Chapter 3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Path Delay Model
■
Nodes represent gates
■
Assign delays to edges – signal may have
different delay to different gates
■
Lump gate and wire delay into a single
value
Modern VLSI Design 3e: Chapter 3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Path Delay Graph
network
graph model
Modern VLSI Design 3e: Chapter 3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Critical Path
■
Critical path = path with the longest delay.
■
Can trace transistors which cause delays
that are elements of the critical delay path.
Modern VLSI Design 3e: Chapter 3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Critical Path Through Delay Graph
Modern VLSI Design 3e: Chapter 3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Reducing Critical Path Length
To reduce circuit delay, must speed up the
critical path—reducing delay off the path
doesn’t help.
■ There may be more than one path of the
same delay. Must speed up all equivalent
paths to speed up circuit.
■ Reduce the critical path delay through logic
reconstruction and transistor sizing
■
Modern VLSI Design 3e: Chapter 3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Example of Logic Reconstruction
shallow logic
ab+acd+acef
deep logic
a(b+c(d+ef)))
Does shallow logic always have a shorter
delay than deep logic?
Modern VLSI Design 3e: Chapter 3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Logic Transformation
Can rewrite by using subexpressions.
■ Flattening logic increases gate fanin.
■ Logic rewrites may affect gate placement.
■
Modern VLSI Design 3e: Chapter 3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Transistor Sizing
■
Similar principle as in
driving large loads
– Gate sizing
■
Individual transistor sizing
within a gate
– Balance the delay of pullup
and pulldown
– Reduce body effect
Modern VLSI Design 3e: Chapter 3
VDD
out
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
False Paths
Logic gates are not simple nodes—some
input changes don’t cause output changes.
■ A false path is a path which cannot be
exercised due to Boolean gate conditions.
■ False paths cause pessimistic delay
estimates.
■
Modern VLSI Design 3e: Chapter 3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
False Path Example
Modern VLSI Design 3e: Chapter 3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Logic Optimization
Logic synthesis: transforms Boolean
expressions into logic gate networks in a
particular library.
■ Optimization goals: minimize area, meet
delay constraint.
■
Modern VLSI Design 3e: Chapter 3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Technology-independent
Optimizations
Works on Boolean expression equivalent.
■ Estimates size based on number of literals.
■ Uses factorization, re-substitution,
minimization, etc. to optimize logic.
■ Technology-independent phase uses simple
delay models.
■
Modern VLSI Design 3e: Chapter 3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Technology-dependent
Optimizations
Maps Boolean expressions into a particular
cell library.
■ Mapping may take into account area, delay.
■ May perform some optimizations in
addition to simple mapping.
■ Allows more accurate delay models.
■
Modern VLSI Design 3e: Chapter 3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Topics
■
Alternative gate circuits (§3.5)
– Pseudo-nMOS gates
– DCVS logic
– Domino gates
Switch logic
■ Power issues
■
Modern VLSI Design 3e: Chapter 3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Pseudo-nMOS
■
Uses a p-type as a resistive pullup, n-type
network for pulldowns.
Modern VLSI Design 3e: Chapter 3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Characteristics of Pseudo-nMOS
&Much smaller pullup network area
– E.g., used in the decoding logic
'But if the pulldown network conducts
– Logic 0 output is above VSS
– Consumes static power
– Pulldown time is longer
» Pullup is always conducting
Modern VLSI Design 3e: Chapter 3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
The Logic “0” Output
Pullup and pulldown form a voltage
divider
■ Must size both n and p transistors to
create the VOL
■
VDD
Vout
– L>W for pMOS
– Large W for nMOS
» NAND gate takes huge area!
Modern VLSI Design 3e: Chapter 3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Transistor Ratio Example
■
VOL=0.25(VDD-VSS)
5V
– nMOS in linear region
– pMOS in linear region
1.25V
■
|In|=|Ip|
5V
■
0.5 m parameters
– (Wp/Lp)/(Wn/Ln)=1.8 (5V)
– For 3.3V supply, 3.9
Modern VLSI Design 3e: Chapter 3
GND
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
DCVS Logic
DCVSL = differential
cascade voltage switch
logic.
■ Requires inputs and
their complements, ab
produces outputs and c
their complements.
■
Modern VLSI Design 3e: Chapter 3
VDD
out
Pulldown
network
out’
Pulldown
network dual
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
a’
b’
c’
DCVS Operation
■
No static power consumption
■
Longer delay than CMOS gate
■
Used in symmetric logic functions with
regard to both a and a’
– e.g., multiple input XORs
Modern VLSI Design 3e: Chapter 3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
DCVS example
Modern VLSI Design 3e: Chapter 3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Domino Logic
■
Dynamic logic: precharged logic
– The value might change over time
■
Two phases:
– precharge;
– evaluate.
■
Not a complete logic family—cannot invert.
Modern VLSI Design 3e: Chapter 3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Domino Gate Structure
VDD
Controlled by clock
■ Precharge ( =‘0’)
■
– Only pullup conducts
– All the inputs 0
– Out=‘0’
■
Storage node
out
a
b
Evaluate ( =‘1’)
– Out=‘1’ if pulldown
conducts
Modern VLSI Design 3e: Chapter 3
GND
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Domino Operation
■
The inputs must be monotonically increasing.
Glitch causes storage node to discharge
Modern VLSI Design 3e: Chapter 3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Domino Effect
Gate outputs rise in sequence:
gate 1
Modern VLSI Design 3e: Chapter 3
gate 2
gate 3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Two Questions
■
VDD
Why do we need the output
inverter?
– makes sure that outputs start
low, go high so that domino
output can be connected to
another domino gate;
– protects storage node from
outside influence. Storage
node and inverter have
correlated values.
■
out
a
b
Q
Why do we put transistor Q GND
at the bottom?
Modern VLSI Design 3e: Chapter 3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Charge Sharing
VDD
■
Common problem for all
dynamic circuits
– Shared charge can
produce erroneous output
values
out
a
b
■
Cbig is shared
– Vbig=0.5VDD
C1
C2
Cbig
a=‘1’
b=‘1’
c
C3
c=‘0’
Cbig=3C
GND
Modern VLSI Design 3e: Chapter 3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Domino Logic Characteristics
& Much smaller pullup network area
& Faster speed
' The inputs have to
– Remain constant during evaluation; OR
– Monotonically rise'
Modern VLSI Design 3e: Chapter 3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Domino and Stored Charge
Charge can be stored in source/drain
connections between pulldowns.
■ Stored charge can be sufficient to affect
precharge node.
■ Can be averted by precharging the internal
pulldown network nodes along with the
precharge node.
■
Modern VLSI Design 3e: Chapter 3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Topics
Alternative gate circuits
■ Switch logic (§3.4, §4.7)
■
– Transmission gates
– Multiplexer
■
Power issues
Modern VLSI Design 3e: Chapter 3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Switch Logic
■
■
Implement Boolean
formulas as networks of
switches.
Transmission gates (TG)
C’
– MOS switches
– Do not amplify, smaller area
■
C
Types of transmission gates
– Complementary
– n-types
Modern VLSI Design 3e: Chapter 3
out
in
C
in
out
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Behavior of Transmission Gates
■
VDD
n-type TG
VDD
– Conducts “0” perfectly
– Voltage drop for “1”
■
0
p-type TG
0
– Conducts “1” perfectly
– Voltage drop for “0”
■
VDD-VTn
-VTp
0
CMOS TG
VDD
VDD
– Conducts both “0” and “1”
perfectly
Modern VLSI Design 3e: Chapter 3
VDD
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
n-type Switch Driving Static Logic
■
Switch underdrives static gate, but gate
restores logic levels.
VDD
VDD
0
VDD
Modern VLSI Design 3e: Chapter 3
VDD - VTn
VDD
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
n-type Switch Driving Switch Logic
■
Further voltage drop, potentially dangerous!
– What if it is connected to pseudo-nMOS?
VDD
VDD
0
VDD - VTn
VDD
Modern VLSI Design 3e: Chapter 3
VDD-2VTn
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Boolean Functions and Switches
■
Why are they “Pseudo”?
a
a
b
1
1
pseudo-AND
b
a
Modern VLSI Design 3e: Chapter 3
b
1
pseudo-OR
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Driving Switch Outputs
■
If there is not a path from the power supply
to the output, the output will float
– Would it be useful sometimes?
■
Switch network inputs may be connected to
power supply or logic signals.
Modern VLSI Design 3e: Chapter 3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Multiplexer
■
There is a path from power source if a and c
are outputs of CMOS gates
■
Smaller area than CMOS implementation
b’
a
b
ab’+cb
c
Modern VLSI Design 3e: Chapter 3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
3-1 Multiplexer
■
Conditions to avoid floating
output
– One and only one ctrl signal is
“1”
ctrl1
in1
ctrl2
in2
■
How to construct the control
logic for a 4-1 multiplexer?
Modern VLSI Design 3e: Chapter 3
ctrl3
in3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Switch Multiplexer
Modern VLSI Design 3e: Chapter 3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Topics
Alternative gate circuits
■ Switch logic
■ Power issues (§3.3.5, §3.3.6, §3.6)
■
Modern VLSI Design 3e: Chapter 3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Power Consumption for CMOS Gates
■
For CMOS gates
– Most power consumption: switching
– Static power consumption: leakage currents
■
The energy consumed for a gate to drive a
load is independent of its transistor size
– Egate=1/2CL(VDD-VSS)2
■
Power = E x f = f CL(VDD - VSS)2
Modern VLSI Design 3e: Chapter 3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Power Consumption Circuit
■
Input is square wave.
Modern VLSI Design 3e: Chapter 3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Observations on Power Consumption
Resistance of pullup/pulldown drops out of
energy calculation.
■ Power consumption depends on operating
frequency.
■
– Slower-running circuits use less power (but not
less energy to perform the same computation).
Modern VLSI Design 3e: Chapter 3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei
Power Consumption for the Circuits
■
P= fCL(VDD-VSS)2
– f: frequency. : activity factor
■
Speed-power product
–
–
–
–
Also knows as delay-power product
An important measure of the circuit quality
SP=(1/f)P=CLV2
Frequency drops out, voltage scaling
Modern VLSI Design 3e: Chapter 3
Copyright 2002 Prentice Hall PTR. Adapted by Yunsi Fei