H. Hashemi, X. Guan, and A. Hajimiri, “A Fully Integrated 24-GHz 8-Path Phased-Array Receiver in Silicon,” ISSCC 2004.
A Fully Integrated 24-GHz 8-Path
Phased-Array Receiver in Silicon
Hossein Hashemi1, Xiang Guan2, Ali Hajimiri2
1 University
of Southern California, Los Angeles, CA
2 California Institute of Technology, Pasadena, CA
H. Hashemi, X. Guan, and A. Hajimiri, “A Fully Integrated 24-GHz 8-Path Phased-Array Receiver in Silicon,” ISSCC 2004.
Outline
• Introduction
• Phased-Array Receiver Architectures
• A 24GHz Integrated Phased-Array Receiver
• Measurement Results
• Conclusion
H. Hashemi, X. Guan, and A. Hajimiri, “A Fully Integrated 24-GHz 8-Path Phased-Array Receiver in Silicon,” ISSCC 2004.
The 24-GHz Frequency Band
250 MHz
frequency
22GHz
24GHz
29GHz
Industrial, Scientific, Medical (ISM) / Unlicensed*
Ultra Wide Band (UWB) for Vehicular Radar Systems
* 24.075
- 24.175GHz for field disturbance sensors (FCC Part 15, Section 15.245)
24.0 - 24.25GHz for fixed and point-to-point operation (FCC Part 15, Section 15.249)
H. Hashemi, X. Guan, and A. Hajimiri, “A Fully Integrated 24-GHz 8-Path Phased-Array Receiver in Silicon,” ISSCC 2004.
24-GHz Compared to 2.4- and 5.2-GHz
• Smaller wavelength
λ1 > λ2
– Reduced antenna size and spacing (~ λ)
– Lower effective antenna area (~ λ2)
• Indoor channel characteristic in an office environment 1:
– More isolation between floors
– Less delay spread for line-of-sight
– Comparable excess path loss for line-of-sight
• Less than proportionate increase of power consumption in
a narrowband integrated radio implementation
1
D. Lu and D. Rutledge, “Investigation of Indoor Channels from 2.4GHz to 24GHz,” IEEE International
Antennas and Propagation Society Symposium, June 2003.
H. Hashemi, X. Guan, and A. Hajimiri, “A Fully Integrated 24-GHz 8-Path Phased-Array Receiver in Silicon,” ISSCC 2004.
Outline
• Introduction
• Phased-Array Receiver Architectures
• A 24GHz Integrated Phased-Array Receiver
• Measurement Results
• Conclusion
H. Hashemi, X. Guan, and A. Hajimiri, “A Fully Integrated 24-GHz 8-Path Phased-Array Receiver in Silicon,” ISSCC 2004.
Advantages of Multiple Antennas
• Limiting factors in high speed wireless communications:
– Multi-path Fading
– Co-channel Interference
• Multiple spaced antennas form statistically independent
communications channels in a fading environment.
– Receiver diversity
– Transmitter diversity
• Phased array provides a directional communication
channel.
• Improvement increases with the number of antenna
elements.
H. Hashemi, X. Guan, and A. Hajimiri, “A Fully Integrated 24-GHz 8-Path Phased-Array Receiver in Silicon,” ISSCC 2004.
Phased-Array Principle
k
Rejection of at
Amplification
undesired
desired direction
direction
θ
d≈λ
λ/2
Delay
wave-front
d=
λ
300m/s
≈
= 15cm
2 2 × 1000Hz
sound
nalogy
d
Delay
+
Processor
Delay
Antenna 1
Antenna 2
• Compensate for air propagation delay in order to amplify or
reject signals from certain directions.
• Amplitude control allows for multiple spatial peaks and nulls.
H. Hashemi, X. Guan, and A. Hajimiri, “A Fully Integrated 24-GHz 8-Path Phased-Array Receiver in Silicon,” ISSCC 2004.
Signal-to-Noise Ratio Improvement
SIN,1
NIN,1
SIN,2
NIN,2
+
SOUT = G.n2.SIN
G1
NRX,1
+
SOUT
G1
NRX,2
NOUT = G.n.(NIN+NRX)
SNROUT = n
+
NOUT
SIN,n
SIN
NIN+NRX
NIN,n
+
G1
NRX,n
Example: n=8 , SNRIN=6dB , BW=250MHz , NF1-path= 10dB
sensitivity = 10log[C/(I+N)] + 10log(kBTB) + NF
= (6 + 9)
+ (-174 + 84) + 10
= -65 dBm
*
Assuming equal input signal and noise power levels and identical paths.
[dBm]
H. Hashemi, X. Guan, and A. Hajimiri, “A Fully Integrated 24-GHz 8-Path Phased-Array Receiver in Silicon,” ISSCC 2004.
Signal Path Phase Shifting Architectures
G1
Delay
G1
A/D
G2
Delay
G1
A/D
G1
A/D
A/D
+
LO
Gn
Delay
Digital
Baseband
Combining
and
Processing
LO
RF Phase Shifting
Baseband Processing
Linear RF Phase Shifters
High
None
A/D Requirements
Low / Moderate
Severe
Power Consumption
Moderate
High
Analog Dynamic Range
High
Low
Versatility
Low
High
H. Hashemi, X. Guan, and A. Hajimiri, “A Fully Integrated 24-GHz 8-Path Phased-Array Receiver in Silicon,” ISSCC 2004.
LO Phase Shifting Architecture
Heterodyne Version
GRF
Homodyne Version
G1
GIF
φ1
GRF
φ1
G2
GIF
+
φ2
GRF
φ2
+
A/D
Gn
GIF
φn
A/D
LO
φn
• Compensate propagation delay by phase shifting the LO,
• Ideal for narrowband channels,
• Accuracy is inversely proportional to the bandwidth.
H. Hashemi, X. Guan, and A. Hajimiri, “A Fully Integrated 24-GHz 8-Path Phased-Array Receiver in Silicon,” ISSCC 2004.
Narrowband vs. Wideband
Signal constellations of a QPSK signal with 6dB SNR at each
antenna input of an 8-path array at 24-GHz carrier frequency.*
BW = 250MHz
Data Rate = 333Mbps
*
Courtesy of Abbas Komijani, Caltech.
BW = 5GHz
Data rate = 6.67Gbps
H. Hashemi, X. Guan, and A. Hajimiri, “A Fully Integrated 24-GHz 8-Path Phased-Array Receiver in Silicon,” ISSCC 2004.
Outline
• Introduction
• Phased-Array Receiver Architectures
• A 24GHz Integrated Phased-Array Receiver
• Measurement Results
• Conclusion
H. Hashemi, X. Guan, and A. Hajimiri, “A Fully Integrated 24-GHz 8-Path Phased-Array Receiver in Silicon,” ISSCC 2004.
24GHz 8-Path Phased-Array Receiver
24-GHz
LNA
RF Mixer
LO1Φ1
LO1Φ2
LO1Φ3
LO1Φ4
ϕ1...ϕ16
LO1Φ1
LO1Φ2
16:1 Phase-Selector
LO1Φ3
16:1 Phase-Selector
LO1Φ4
16:1 Phase-Selector
LO1Φ5
16:1 Phase-Selector
LO1Φ6
16:1 Phase-Selector
LO1Φ7
16:1 Phase-Selector
LO1Φ8
16:1 Phase-Selector
19.2-GHz 16-Phase VCO
16:1 Phase-Selector
Vcntrl
÷4
LO2_Q
Loop Filter
LO2_I
÷64
Charge Pump
refin
Phase-Frequency
Detector
bitin
LO1Φ5
Phase-Select Shift-Register
CLK
4.8-GHz IF Mixer BB Buffer
LO1Φ6
IF Amplifier
LO1Φ7
LO1Φ8
Σ
Band-gap &
PTAT
references
LO2_I
LO2_Q
QBB IBB
Vsupply
75-MHz
H. Hashemi, X. Guan, and A. Hajimiri, “A Fully Integrated 24-GHz 8-Path Phased-Array Receiver in Silicon,” ISSCC 2004.
Beam Steering w/ Discrete LO Steps
R
elativeA
rray-G
ain(dB
)
Relative
Array
Gain
(dB)
0
-5
-10
-15
-20
-25
-30
-35
-40
0
20
40
60
80
100
120
140
160
180
Incidence
Angle
(degrees)
Incidence
Angle (degrees)
• 4-bit phase selection resolution,
• Forward looking beam steering steps of ~10°,
• Sufficient coverage of the entire range of angles,
• Narrow beam width provides spatial selectivity,
• Nulls affected by asymmetric LO phase distribution.
H. Hashemi, X. Guan, and A. Hajimiri, “A Fully Integrated 24-GHz 8-Path Phased-Array Receiver in Silicon,” ISSCC 2004.
24-GHz Two-Stage Low Noise Amplifier
One Signal Path
Simulated Performance
Vdd
Vin
Vbias
Vout
(dB)
Vbias
30
25
Noise Figure
20
S21
15
10
5
0
-5
-10
14
16
18
20
22
24
26
28
30
Frequency (GHz)
• Simultaneous noise and power match for the LNA,
• Impedance match between stages for max power transfer,
• 8-mA DC current consumption from a 2.5-V supply.
H. Hashemi, X. Guan, and A. Hajimiri, “A Fully Integrated 24-GHz 8-Path Phased-Array Receiver in Silicon,” ISSCC 2004.
RF Mixers and IF Combining Structure
IF+
IF+
LO+
LO-
Mixer
Cell
Vbias2
IF2IF3+
LO3+
IF-
IF3IF4+
LO4+
LO+
Vbias2
RF
Vdd
IF+
IF1IF2+
LO2+
LO-
LO+
RF
IF1+
LO1+
IF-
IF-
IF4IF5+
LO5+
Vbias1
Matched
to LNA
Output
IF5IF6+
LO6+
IF6IF7+
LO7+
IF7IF8+
LO8+
IF8-
Mixer
Mixer
Mixer
Mixer
Mixer
Mixer
Mixer
Mixer
Cell 1 LO2- Cell 2 LO3- Cell 3 LO4- Cell 4 LO5- Cell 5 LO6- Cell 6 LO7- Cell 7 LO8- Cell 8
LO1RF1
RF2
RF3
RF4
RF5
RF6
RF7
RF8
• Mixer outputs combined in current domain via a binary tree.
H. Hashemi, X. Guan, and A. Hajimiri, “A Fully Integrated 24-GHz 8-Path Phased-Array Receiver in Silicon,” ISSCC 2004.
IF Amplifier and Image-Reject Mixers
Vdd
BBi+
Vbias
IF+
Vbias
IF-
LO2i+
BBiLO2i-
Vbias
LO2i+
Vbias
Vbias
Vbias
to Quadrature Mixer
• The intermediate frequency is 4.8-GHz,
• Tuned loads at IF.
to Quadrature Mixer
H. Hashemi, X. Guan, and A. Hajimiri, “A Fully Integrated 24-GHz 8-Path Phased-Array Receiver in Silicon,” ISSCC 2004.
16-Phase Voltage-Controlled Oscillator
167.5°
135°
337.5°
0°°
22.5°
180°
202.5°
Vdd
VCNTRL
Vout225°
315°
45°
Vin+
292.5°
112.5°
270°
247.5°
Vout+
Vin-
67.5°
Vbias
90°
• 16-phase, 19.2-GHz CMOS VCO,
• An 8-stage ring structure generates 16 equally spaced phases,
• Single pole gain stage would require GBW larger than 46-GHz,
• Amplifiers tuned close to ωosc due to large tank Q,
• Symmetric layout minimizes relative deviation of phases.
H. Hashemi, X. Guan, and A. Hajimiri, “A Fully Integrated 24-GHz 8-Path Phased-Array Receiver in Silicon,” ISSCC 2004.
19-GHz Integer-N Frequency Synthesizer
fref
75-MHz
PFD
Charge
Pump
Loop
Filter
VCNTRL
19.2-GHz
fout
one VCO phase
÷ 256
• Third order loop,
• Bandwidth of 7-MHz and settling time less than 50µs,
• Multi-switch charge pump to minimize reference feedthrough,1
• Standard tri-state frequency phase detector (PFD),
• Master-slave latches with emitter controlled logic (ECL) for
divide-by-two circuits.
1
J. Cranincks and M. Steyaert, “Wireless CMOS Frequency Synthesizer Design,” Kluwer Academic
Publishers, 1998.
H. Hashemi, X. Guan, and A. Hajimiri, “A Fully Integrated 24-GHz 8-Path Phased-Array Receiver in Silicon,” ISSCC 2004.
Phase-Selecting (analog multiplexing)
Vdd
Phase-Selector
LOΦ1..8+
Φ1..8
112.5°° 90°° 67.5°°
45°°
135°°
22.5°°
157.5°°
0°°
Vdd
LOΦ1+
Vdd
LOΦ1..8Φ1..8
Vdd
Vdd
LOΦ1- LOΦ2+
selΦ1
Vdd
LOΦ2-
LOΦ8+
Vdd
LOΦ8-
selΦ8
selΦ2
Vbias
Vdd
Sign-Selector
LOΦ1..16Φ1..16
LOΦ1..16+
Φ1..16
Vdd
Vdd
Vdd
LOΦ1..8+
LOΦ1..8-
sel180°°
sel180°°
Vdd
LOΦ1..8+
Vbias
• 23+2=10 total phase selectors instead of 24=16,
• A dummy array is included to maintain constant loading
H. Hashemi, X. Guan, and A. Hajimiri, “A Fully Integrated 24-GHz 8-Path Phased-Array Receiver in Silicon,” ISSCC 2004.
Oscillator Phase Distribution Network
Global Distribution Tree
1st path
16
16
16
2nd
4th path
5th path
16
16
16
16
16
LO phases
16
16
6th
16
path
7th path
8th path
16
0°
180°
202.5°
22.5°
45°
225°
16
path
3rd path
Transmission Line Array
16
337.5°
157.5°
16
• The adopted distribution tree and phasing sequence minimizes
the unwanted electromagnetic coupling between paths.*
*
X. Guan, H. Hashemi, A. Komijani, and A. Hajimiri, “Multiple Phase Generation and Distribution for a
Fully Integrated 24-GHz Phased-Array Receiver in Silicon,” to be presented at RFIC’04, June 2004.
H. Hashemi, X. Guan, and A. Hajimiri, “A Fully Integrated 24-GHz 8-Path Phased-Array Receiver in Silicon,” ISSCC 2004.
Outline
• Introduction
• Phased-Array Receiver Architectures
• A 24GHz Integrated Phased-Array Receiver
• Measurement Results
• Conclusion
H. Hashemi, X. Guan, and A. Hajimiri, “A Fully Integrated 24-GHz 8-Path Phased-Array Receiver in Silicon,” ISSCC 2004.
Die Microphotograph
3.5mm
1-Channel
Phase Selector
LO Phase
Distribution
16-phase
Oscillator
Frequency
Synthesizer
Biasing
Circuitry
3.3mm
1 RF Channel
(LNA + mixer)
IF Mixers &
BB Amps
Implemented in a SiGe Process (fT,HBT=120GHz , LCMOS=0.18µm)
H. Hashemi, X. Guan, and A. Hajimiri, “A Fully Integrated 24-GHz 8-Path Phased-Array Receiver in Silicon,” ISSCC 2004.
High Frequency Test Setup
Control Lines (connected to PC)
Gold Wirebond
Duriod
Ground
Electroplated Gold
Chip
Silver Epoxy
Power Supply
Brass Substrate
RF Inputs
Synthesizer Reference
200 µm
Baseband Outputs
• Short and symmetric connections to multiple inputs,
• Efficient grounding at high frequencies,
• Compatible with patch antenna technology.
H. Hashemi, X. Guan, and A. Hajimiri, “A Fully Integrated 24-GHz 8-Path Phased-Array Receiver in Silicon,” ISSCC 2004.
Small Signal Response
Single Path Gain [dB]
Image Band
Input Reflection, S11 [dB]
Signal Band
40
0
Image
Rejection
20
0
-10
-20
`
-20
-30
-40
-40
10
0
5
10
15
20
Frequency (GHz)
25
30
15
20
25
Frequency (GHz)
30
35
• 18dB larger signal gain for the 8-path array,
• 9dB SNR improvement in the 8-path array,
• Image rejection can be further enhanced by using narrowband
antennas1.
*
D. Lu, M. Kovacevic, J. Hacker, and D. Rutledge, “A 24-GHz Active Patch Array,” International Journal
of Infrared and Millimeter Waves, pp. 693-704, May 2002.
H. Hashemi, X. Guan, and A. Hajimiri, “A Fully Integrated 24-GHz 8-Path Phased-Array Receiver in Silicon,” ISSCC 2004.
Single Path Large Signal Behavior
Compression Point
Two Tone Test *
1dB
20
main
20
Pout [dBm]
Pout [dBm]
40
0
intermod
-20
10
0
-10
-40
-27
-11
-40
-30
-20
-10
-60
-50
Pin (dBm)
• Intermodulation slope is 2.5dB/dB,
• Higher-order nonlinearity affect the system.
*
Two in-band tones with 5-MHz separation are applied.
-40
-30
Pin (dBm)
-20
-10
H. Hashemi, X. Guan, and A. Hajimiri, “A Fully Integrated 24-GHz 8-Path Phased-Array Receiver in Silicon,” ISSCC 2004.
16-Phase Voltage-Controlled Oscillator
Phase Noise (dBc/Hz) *
VCO Frequency (GHz)
21
-70
20.5
-80
20
-90
19.5
-100
19
18.5
0
0.5
1
1.5
2
Vcntrl [V]
2.5
3
-110
100k
1M
Offset Frequency [Hz]
10M
• Non-intrusive measurement using a pick-up coil,
• Phase noise variations with frequency in stand-alone VCO.
*
Phase noise curve for VCO frequency of 18.7-GHz.
H. Hashemi, X. Guan, and A. Hajimiri, “A Fully Integrated 24-GHz 8-Path Phased-Array Receiver in Silicon,” ISSCC 2004.
19-GHz Frequency Synthesizer
[dBm]
Locked Spectrum
Phase Noise (dBc/Hz)
-40
-40
-50
-60
-60
-80
-70
-100
-80
-120
-90
-140
-100
19.18
19.19
19.2
19.21
Frequency [GHz]
19.22
20.2-GHz
18.4-GHz
19.2-GHz
20log(28)
75-MHz reference
-160
100
10k
1M
Offset Frequency [Hz]
• Synthesizer locking range is greater than 2-GHz, *
• Similar in-band phase noise for all locked frequencies,
• Phase noise measurements limited by reference noise.
*
By varying the reference frequency
100M
H. Hashemi, X. Guan, and A. Hajimiri, “A Fully Integrated 24-GHz 8-Path Phased-Array Receiver in Silicon,” ISSCC 2004.
Array Measurement Set-up
Laptop for array programming
Signal Generator
Power Supply
24,000,000,000 Hz
HP 83650B
2.5 V
Variable Phase-Shifter
RF1
X8
Agilent E 3644A
Control Bits
Vdd
Phased-Array Receiver
75,000,000 Hz
HP 8643A
RF8
Power Divider
BB+ BB-
refin
Spectrum Analyzer
Baseband
Power-Combiner
HP 8563E
Microwave Cable
• Phase-Shifters at input emulate propagation delay.
H. Hashemi, X. Guan, and A. Hajimiri, “A Fully Integrated 24-GHz 8-Path Phased-Array Receiver in Silicon,” ISSCC 2004.
2-Path Array Patterns
-135°
-90°
180°
1
0.8
0.6
0.4
0.2
0
-45°
-135°
-90°
135°
-135°
-90°
90°
180°
1
0.8
0.6
0.4
0.2
0
-45°
45°
135°
-135°
-90°
90°
45°
180°
1
0.8
0.6
0.4
0.2
0
0
0
180°
1
0.8
0.6
0.4
0.2
0
180°
1
0.8
0.6
0.4
0.2
0
180°
1
0.8
0.6
0.4
0.2
0
-45°
135°
-90°
90°
45°
0
-45°
135°
-90°
90°
45°
0
-135°
-45°
-45°
135°
90°
45°
0
135°
-135°
-90°
90°
45°
0
-135°
-90°
90°
45°
-45°
0
-135°
135°
180°
1
0.8
0.6
0.4
0.2
0
180°
1
0.8
0.6
0.4
0.2
0
135°
90°
45°
-45°
0
H. Hashemi, X. Guan, and A. Hajimiri, “A Fully Integrated 24-GHz 8-Path Phased-Array Receiver in Silicon,” ISSCC 2004.
4-Path Array Patterns
Measured
Theoretical
170°
160°
150°
140°
0
1
0.8
0.6
0.4
0.2
0
170°
10°
160°
20°
30°
130°
120°
40°
140°
50°
130°
60°
110°
150°
90°
160°
150°
140°
0
1
0.8
0.6
0.4
0.2
0
20°
30°
40°
50°
60°
70°
90°
70°
90°
80°
Measured
10°
80°
40°
60°
100°
130°
110°
100°
30°
110°
80°
120°
20°
50°
Measured
170°
10°
120°
70°
100°
0
1
0.8
0.6
0.4
0.2 b
0
170° 1 0
160°
0.8
150°
0.6
0.4
140°
0.2
0
130°
10°
20°
30°
40°
50°
120°
60°
110°
70°
100°
90°
80°
H. Hashemi, X. Guan, and A. Hajimiri, “A Fully Integrated 24-GHz 8-Path Phased-Array Receiver in Silicon,” ISSCC 2004.
Measured Performance Summary
Signal Path Performance (per path)
Peak Gain
Noise-Figure
Input-Referred 1dB Compression Point
Input-Referred Intercept Point
On-chip Image Rejection
Input reflection Coefficient (S11)
43dB
8.0dB
-27dBm
-11.5dBm (2 tones 5MHz apart)
35dB
-10 to -20dB
LO Path Performance
Synthesizer Locking Range
KVCO
VCO Phase-Noise
2 GHz (10%)
2.1 GHz/V @19.2GHz
-103dBc/Hz @ 1MHz offset from 18.7GHz
Complete Receiver Performance (8 paths)
Total Array Gain
SNR Improvement
Beam-steering Resolution (forward looking)
Beam-forming Peak-to-Null Ratio
Power Dissipation @ 2.5V
61dB
9dB
<10°
up to 20dB (measured for 4 path)
364mA
287mA (w/o biasing and baseband buffers)
Implementation
Technology
Die Area
SiGe, 120GHz HBT, 0.18µm CMOS
3.5mm x 3.3mm
H. Hashemi, X. Guan, and A. Hajimiri, “A Fully Integrated 24-GHz 8-Path Phased-Array Receiver in Silicon,” ISSCC 2004.
Summary
• Multiple antenna offer more efficient solutions at higher
frequencies.
• 24-GHz is a good candidate for a variety of future wireless
communication schemes and automotive radar applications.
• Phase shifting has been performed at the local oscillator
path using a multi-phase synthesizer and symmetric
distribution networks.
• The first fully-integrated phased-array system at 24-GHz
using a silicon technology has been demonstrated.
H. Hashemi, X. Guan, and A. Hajimiri, “A Fully Integrated 24-GHz 8-Path Phased-Array Receiver in Silicon,” ISSCC 2004.
Acknowledgements
• Lee Center for Advanced Networking, Caltech,
• Caltech Center for Neuromorphic Systems Engineering
(CNSE),
• National Science Foundation (NSF),
• IBM Corporation for chip fabrication,
• R. Aparicio, R. Chunara, A. Komijani, A. Natarajan, D. Lu,
N. Wadefalk, A. Shen, and Prof. D. Rutledge from Caltech.