IEEE Asian Solid-State Circuits Conference
3-3
November 12-14, 2007 / Jeju, Korea
A Low-Power, 3–5-GHz CMOS UWB LNA Using Transformer Matching Technique
Dong Hun Shin1, Jaejin Park2, and C. Patrick Yue1
1
Dept. of Electrical & Computer Engineering, University of California, Santa Barbara, CA 93106
2
Samsung Electronics, Giheung, Gyeonggi-do, Korea
Abstract — This paper presents the design of a 3−5-GHz
CMOS ultra-wideband (UWB) low-noise amplifier (LNA)
utilizing an on-chip transformer to achieve low-power
operation and to realize a compact input matching network.
Detailed analyses of the input match, voltage gain, and noise
figure of the LNA are provided. Implemented in 0.13-µm
CMOS, the LNA achieves a maximum power gain of 16.2
dB, an input return loss of greater than 11.0 dB, and a
minimum noise figure of 2.8 dB for the 3−5-GHz UWB
while consuming only 6.7 mW from a 1.2-V supply. The
active area of the fabricated CMOS UWB LNA is 0.32 mm2.
The input match of a cascode stage with degeneration
inductor is inherently narrowband due to the series RLC
resonant circuit formed by Ls and Cgs1+Cd [5]. In this
work, a transformer with a shunt capacitor (Cp) is utilized
to absorb this series RLC circuit into a wideband
matching network.
VDD
Rload
Lload
Vout
Index terms — Ultra-wideband, low-noise amplifier,
transformer, broadband matching, CMOS, RFIC.
VBIAS
II. DESIGN AND ANALYSIS
The proposed UWB LNA topology is shown in Fig. 1.
To achieve high gain and good reverse isolation, a
cascode stage is used for the amplifier core. The source
degeneration inductor (Ls) is added to realize a 50-Ω real
impedance for input match. One drawback of this
topology is that the gate-source capacitance (Cgs) of the
input device (M1) is usually quite small such that a large
series inductance at the gate of M1 is required to achieve
the desired 50-Ω impedance. To resolve this issue, a
capacitor (Cd) can be added between the gate and source
of M1 as depicted in Fig. 1. Furthermore, by optimizing
the value of Cd, the noise due to M1 can be reduced [4].
1-4244-1360-5/07/$25.00
M2
V out'
Cc
Vin
k
I. INTRODUCTION
A critical component in an ultra-wideband (UWB)
system is a wideband low-noise amplifier (LNA). It
needs to provide low noise figure, stable gain, and good
input matching over the entire bandwidth with low power
consumption. Several 3−5-GHz CMOS UWB LNA
topologies utilizing various input matching networks
have been reported recently such as LC band-pass filter
(BPF) [1], resistive shunt feedback [2], and miller effect
[3]. The BPF matching network-based topology achieves
wideband characteristics with low power consumption.
However, it tends to occupy large die area due to the need
of multiple on-chip LC components. The resistive shunt
feedback LNA also has wideband characteristics, but it
tends to degrade noise performance due to the feedback
resistor. To further push the performance for CMOS
wideband LNA, this work explores the concept of
utilizing a transformer as a wideband input matching
network which occupies small die area and provides good
noise performance.
M3
M1
Vgs1
Rs
Cp
Vs
L1
L2
Zin
Zg
Ls
Cd
Fig. 1. Simplified schematic of the proposed UWB LNA.
A. Input Matching Network
Figure 2 shows the simplified equivalent circuit for the
proposed transformer-based input matching network.
I1
I2
k
L1
Cp
Zin
Zt
L2
Zp
Fig. 2. A simplified equivalent circuit of the proposed transformerbased input matching network.
With the secondary coil (L2) terminated with arbitrary
load impedance (Zt), the impedance, Zp, looking into the
positive node of the primary coil (L1), is given by
Z p ( s ) = sL1 −
s 2M 2
,
sL2 + Z t
(1)
where L1 and L2 are the self inductance of the primary
and secondary coil, respectively [6]. M is the mutual
inductance, which is equal to k ⋅ L1 ⋅ L2 . The overall
input impedance of the equivalent circuit, Zin, can be
expressed as
Z in ( s ) =
Z p( s )
1 + sC p Z p ( s )
.
(2)
The parasitic resistance and capacitance of the
transformer are not explicitly included in Eq. (1) and (2)
2007 IEEE
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95
in order to simplify the derivation. Nevertheless, the
frequency response characteristics of Zin are still well
captured because the parasitic RC has similar effects as Zt
and Cp. However, for noise analysis, the contribution due
to the parasitic resistance must be considered. The input
impedance of the amplifier in Fig. 1 can then be derived
based on Eq. (1) and (2) by substituting Zt with the series
RLC circuit looking into the gate of M1. The final
expression is shown at the bottom of the page as Eq. (3).
In Eq. (3), Ct is the sum of Cgs1 and Cd, and Rt is equal to
ωTLs [5]. Equation (3) reveals that Zin has a zero at the
origin, a complex zero, and two complex poles for the
practical RLC values that can be realized on chip. The
solution for the complex zero is
2
( ( ( )
) )
2
− Rt Ct ± Rt Ct − 4 Ct L2 1 − k 2 + Ls
)) .
desired bandwidth. The output impedance, Zload, can be
expressed as
Z load ( s ) =
C. Gain and Noise Analyses
The proposed amplifier can be divided into two parts to
derive its voltage gain: the input matching network and
the cascode stage with an inductive load. The transfer
function of the input matching network is
v gs1 ( s )
For practical on-chip transformer and capacitance values,
it turns out that the z23 is a complex conjugate, since the
first term in the square root is much smaller than the
second term. Although a closed-form solution for fourthorder polynomial exists, it is complicated. To get the
desired wideband input match, one can set the complex
zero frequency in between the two complex pole
frequencies whose values can be solved numerically
using Matlab. For the targeted bandwidth of 3–5 GHz,
the complex zero is set to 4 GHz, and the two complex
poles are placed at 2.5 and 7 GHz as shown in Fig. 3(a).
The corresponding S11 is shown in Fig. 3(b). For design
margin, the bandwidth of the input match is designed to
be from 2.5–7 GHz.
vin ( s )
( (
2Ct L2 1 − k 2 + Ls
=
Av ( s ) =
v gs1( s )
vin ( s )
-5
S11 [dB]
Zin [ Ω]
-15
-25
Imaginary
-75
-100
1
-20
Real
-50
2
3
(6)
⋅ g m1 ⋅ Z load ( s ) ,
(7)
s2 M 2

Rs
R1 + sL1 + 
 1 + sR s C p





,
(8)
where R1 and R2 are series resistances of primary and
secondary coils, respectively, and Rs is the source
resistance.
-10
0
,
where gm1 is the effective transconductance of the
cascade stage including the effect of Ls.
For the noise figure derivation of the proposed LNA, it
is convenient to use the equivalent noise models shown in
Fig. 4, which refer the drain and gate noise currents to
output. The impedance (Zg) looking into the secondary
terminal of the transformer is
50
25
)
where vgs1 is the voltage across the gate and source nodes
of M1. Because the output voltage at the drain of M2 is
gm1 vgs1 Zload, the overall voltage gain of the amplifier
shown in Fig. 1 can be calculated by
0
75
k L1 L2
(
s 2 L1Ct ( L2 1 − k 2 + Ls ) + sRt Ls Ct + L1
Z g ( s ) = R2 + sL2 −
100
(5)
where Cout is the total output capacitance at the drain
node of M2. A source follower buffer stage with a current
source load is added at the output to drive an off-chip 50Ω load during testing.
(4)
z 23 =
sRload Lload
,
s 2 (Lload Cout ) + sRload Cout + 1
-25
4 5 6 7 8
Frequency [GHz]
-30
1
9 10
2
3
4 5 6 7 8
Frequency [GHz]
iout
9 10
(a)
(b)
Fig. 3. Simulated responses for input matching network using Eq. (3)
with L1 = 2.5nH, L2 =4.7nH, k =0.85, Cp=600fF, Ls=0.6nH, Ct=820fF,
Rt=50. (a) Zin, (b) S11 in dB.
iout
gm vgs
ing
Ct
vgs
gmvgs
ind
Zg
Zgs vgs
Ct
indg
Zg
B. Output Stage
To achieve high gain under low voltage headroom, an
inductor with a series resistor is adopted as the output
load to implement a low-Q, tuned load to cover the
Z in ( s ) =
(
( (
(a)
(b)
Fig. 4. Equivalent noise model for the proposed LNA: (a) noise model
with two noise current sources, (b) equivalent noise model referring
drain and gate noise sources to the output.
)
)
)
sL1 s 2 Ct L2 1 − k 2 + Ls + sRt Ct + 1
(3)
s L1Ct C p ( L2 1 − k + Ls ) + s 3 Rt L1Ct C p + s 2 ( Ct ( L2 + Ls ) + L1C p ) + sRt Ct + 1
4
(
2
)
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Following the derivation in [7], the total output noise
current can be found as


 2
 2
i 2 ng

 i ng
2
i 2 ndg = i 2 nd  η + 2 ⋅ Re c ⋅
⋅ g m ⋅ η ⋅ Z gs  +
⋅ g m Z gs
2
i 2 nd


 i nd

2





values of the input matching network are different from
the initial design listed in Fig. 3. For the output load, a 4nH inductor (Lload) is used in series with a 28-Ω resistor
(Rload).
(9)
where c is the correlation coefficient between the drain
and induced gate noises, and Zgs, η are expressed as
Z gs ( s ) =
1  Z g + sLs
|| 
sC t  1 + g m ⋅ sLs

,


 g ⋅ sL s 
Z .
η( s ) = 1 −  m
 sLs + Z g  gs


F =1+
i
i
2
ndg
nout ( source
,
(12)
)
where i 2 nout ( source ) is the output noise current due to the
source and is given by
2
i 2 nout ( source) = g m ⋅ A2 gain( s ) ⋅ 4k BTRs ∆f .
(13)
Note that Again is the voltage gain between vs and vgs1 as
defined in Fig. 1 and can be found as follows.
Again ( s ) =
v gs1 ( s )
Z in ( s )
.
vin ( s ) Rs + Z in ( s )
⋅
0.8 mm
(11)
By using Eq. (9), the total LNA noise factor can be
expressed as
2
0.4 mm
(10)
Fig. 5. Fabricated chip micrograph.
The on-chip transformer with poly-silicon patterned
ground shield (PGS) (see Fig. 6) is designed using a fullwave 3D simulator (Ansoft HFSS). The values of the
equivalent circuit model are extracted and summarized in
Table I. The transformer has a 3-to-4 turn ratio and an
outer dimension of 250 µm. The trace width and spacing
are 4 µm and 5.5 µm, respectively.
P1
(14)
where Zin is the total input impedance given in Eq. (2).
Although the results of the LNA noise derivation is quite
complicated, it can be shown from Eq. (6), (13), and (14)
that i 2 nout ( source ) increases with Again which in turn
increase with the transformer coupling coefficient k.
Therefore, the noise figure of the proposed LNA
decreases with increasing k. However, the operating
bandwidth of transformer decreases as k increases [8].
Therefore, the transformer design must balance the
tradeoff between noise and input matching bandwidth.
III. IMPLEMENTATION ISSUES AND MEASUREMENT
The proposed LNA is implemented in a 0.13-µm
CMOS process. The chip micrograph is shown in Fig. 5.
The size of the common-source transistor (M1) is
optimized for the noise performance at 4 GHz [5] and is
set to be 256 µm/0.12 µm. The width of the cascode
transistor (M2) is chosen to be 128 µm/0.12 µm after
considering the tradeoff between gain and bandwidth.
The lager size of M2 is better to achieve a higher gain, but
has a potential to decrease overall bandwidth because Cout
is increased as shown Eq. (5). The value of the source
degeneration inductor, Ls is chosen to be as small as
possible to minimize its effect on the gain. With Ls set
equal to 300 pH, a 300-fF shunt capacitor (Cd) is used to
generate a 50-Ω input impedance. It should be noted that
due to gain and noise considerations, the component
P1
S2
P2
S1
Cp1
Cc
Cp2
L1
k
L2
Cs1
R1
P2
Cp1
(a)
S2
Cs2
R2
Cc
Cp2
S1
(b)
Fig. 6. (a) The 3-to-4 transformer with poly-silicon patterned ground
shield, (b) equivalent circuit of the transformer.
TABLE I
EQUIVALENT CIRCUIT VALUES FOR TRANSFORMER
R1 R2 Cc Cp1 Cp2 Cs1 Cs2
L1 L2
k
nH
nH
2.7
3.5
0.83
Ω
Ω
fF
fF
fF
fF
fF
7
8
99
70
128
1
1
Figure 7 shows power gain (S21) and noise figure of the
designed UWB LNA for both simulated and measured
results. The maximum power gain is 16.2 dB at 3.4 GHz.
The −3-dB gain bandwidth is between 2.3–5.0 GHz,
which covers the targeted lower UWB band. The
minimum noise figure is 2.8 dB at 2.8 GHz and is less
than 5.2 dB across the lower UWB band. Noise analyses
based on simulations show that the insertion loss
associated with the input transformer and the noise of the
input device (M1 in Fig. 1) contribute 57% and 18%,
respectively, to the noise factor excluding the noise due
to the source resistance (F−1).
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TABLE II
PERFORMANCE COMPARISON OF RECENTLY REPORTED 3−5-GHZ CMOS UWB LNA
References
FOM
[1] MWCL, 2006
[2] JSSC, 2005
[3] ISSCC, 2006
This work
0.1 ~ 0.4
0.1 ~ 0.2
0.8 ~ 1.2
0.2 ~ 1.0
S11
(dB)
< −10.0
< −9.0
< −10.5
Gain
(dB)
6.4 ~ 9.5
6.7 ~ 9.8
15.0 ~ 16.0
13.7 ~ 16.2
< −11.0
NF
(dB)
3.5 ~ 5.5
2.3 ~ 4.0*
1.8 ~ 2.2
2.8 ~ 5.2
IIP3
(dBm)
−0.8
−7.0
−9.0
PDC
(mW)
16.5**
12.6**
7.7
−8.5**
6.7**
Area***
(mm2)
~ 1.08
~ 0.90
~ 0.63
~ 0.60
Technology
0.13 µm
0.18 µm
0.18 µm
0.13 µm
* With external inductors, ** Excluding output buffer, *** Including I/O pads
Under a 1.2-V supply, the LNA dissipates 6.7 mW
excluding the output buffer. The reverse isolation, S12, is
measured to be less than −45 dB across the lower UWB
band. The measured S11 and S22, are shown in Fig. 8. The
S11 is less than −11.0 dB, and the S22 is less than −13.4 dB
for the lower UWB band. Good agreement is obtained
between the measured and simulated results for gain,
return loss, and noise figure by using pre-characterized
RF sub-circuits cells as described in [9]. Based on
measurement and simulation results using two-tone
inputs at 4.0 and 4.02 GHz, the estimated IIP3 with and
without the output buffer is −14.0 dBm and −8.5 dBm,
respectively.
30
30
Measured
20
20
Simulated
0
15
NF [dB]
S21 [dB]
10
25
Measured
-10
FOM =
5
1
2
3
4
5
Frequency [GHz]
6
7
0
8 9 10
REFERENCES
[1]
[3]
[4]
0
Measured
-5
-5
[5]
Simulated
-10
-15
-15
Measured
-20
-25
-30
1
2
3
4
5
Frequency [GHz]
6
7
[6]
-20
[7]
-25
[8]
-30
8 9 10
Fig. 8. Input and output match of the designed UWB LNA.
S22 [dB]
S11 [dB]
-10
(15)
The design of a 3−5-GHz CMOS UWB LNA with onchip transformer matching technique is reported.
Experimental results demonstrated the advantage of this
technique in reducing chip area and power consumption
in comparison to other broadband input matching
schemes such as resistive-shunt feedback or LC ladder
filters.
Fig. 7. Measured vs. simulated power gain and noise figure.
0
.
IV. CONCLUSIONS
[2]
Simulated
G ⋅ IIP 3
( NF − 1 ) ⋅ PDC
Our design achieves the lowest power consumption and
chip area while attaining comparable performance in
gain, matching, NF and linearity to other recently
reported low-band UWB LNA.
10
-20
-30
The performance comparison of the designed 3−5-GHz
UWB LNA is shown in Table II with in-band figure of
merit (FOM) that is defined as
[9]
A. Bevilacqua, et al., “A Fully Integrated Differential CMOS
LNA for 3−5-GHz Ultrawideband Wireless Receivers,” IEEE
Microwave and Wireless Components Letters, vol. 16, no. 3, pp.
134-136, March 2006.
C.-W. Kim et al., “An Ultra-Wideband CMOS Low Noise
Amplifier for 3-5-GHz UWB System,” IEEE Journal of SolidState Circuits, vol. 40, no. 2, pp. 554-547, February 2005.
H.-J. Lee, et al., “A 3 to 5GHz CMOS UWB LNA with Input
Matching Using Miller Effect,” IEEE International Solid-State
Circuits Conference, pp 731-740, Feb. 2006.
P. Andreani and H. Sjöland, “Noise Optimization of an
Inductively Degenerated CMOS Low Noise Amplifier,” IEEE
Trans. on CAS– II: Analog and Digital Signal Processing, vol. 48,
no. 9, pp. 835–841, Sept. 2001.
D.K. Shaeffer and T.H. Lee, “A 1.5-v, 1.5-GHz CMOS Low
Noise Amplifier,” IEEE Journal of Solid-State Circuits, vol. 32,
no. 5, pp. 745-759, May 1997.
C.P. Yue and S.S. Wong, “On-Chip Spiral Inductors with
Patterned Ground Shields for Si-Based RF IC’s,” IEEE Journal of
Solid-State Circuits, vol. 33, no. 5, pp. 743-752, May 1998.
MIT Open Course Wave, M. Perrott, “High Speed Communication
Circuits and Systems,” <http://ocw.mit.edu/OcwWeb/index.htm>.
J. R. Long, “Monolithic Transformers for silicon RF IC Design,”
IEEE Journal of Solid-State Circuits, vol. 35, no. 9, pp. 13681382, September 2000.
D.H. Shin and C.P. Yue, “A Unified Modeling and Design
Methodology for RFICs Using Parameterized Sub-Circuit Cells,”
IEEE RFIC Symposium Digest, pp. 415-418, June 2006.
98
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