EE214
Autumn, 2003
Simulations of OP AMPs
1. Offset Voltages
OP Amps have very high differential gains and any small offset voltage can saturate an OP Amp
to the positive or negative supply rails. OP Amp simulation in SPICE can be difficult especially
in the open loop as you have to find the exact offset voltage before any kind of open loop test can
be performed.
Offset voltage is an external voltage applied at the OP Amp input which keeps the DC level of
the output at the nominal common mode value. If we do not apply proper offset voltage at the
input terminals, the OP Amp devices may not biased correctly and any AC analysis will use
models extracted in the wrong device operation regions.
There are many different simulation methods to find offset vo ltage. Fig. 1. shows one of them,
which will be used for grading. Apply differential voltage sources at the OP Amp inputs and
sweep their DC values until your output voltage becomes exactly the common mode output
voltage (2 V in our case). Note that you should sweep your DC sources with enough resolutions
since the offset voltages are in milli/micro volt ranges. This method is not practical for lab use,
however, it works well for simulations.
Vdd
Vos/2
Vcm
•1V
•2V
• 3.5 V
+
_
Rs
+ _
+
_
_
+
Vos/2
Vout
CL
Rs
Fig. 1. Offset Measurement
Do not forget that every design change, no matter how simple it may be, can change your
offset voltage completely. Try to develop a script that can extract your offset voltage quickly,
and make sure that you find your offset voltage after every single design change.
You have to satisfy the gain requirement for a range of input common mode range (1 V to 3.5 V).
Extract three offset voltages, one for the nominal input common voltage (Vcm = 2 V), and one
each for two extremes (Vcm =1 V and 3.5 V). Also keep in mind that DC value of output voltage
should be 2 V (nominal common mode value) for the whole range of input common mode.
2. Open-Loop Differential Gain
Fig. 2. shows the test circuit for the open- loop differential gain measurement. Vos is the offset
voltage which you have already measured for this particular OP Amp design. Make sure that
your circuit has a correct Vos applied before you can get any meaningful results of this test.
We will extract your low frequency gain for three values of input common mode (Vcm = 1V, 2V,
3.5V). In all the three cases, yo ur gain should be greater than 2000, though it does not need to be
constant over the whole range.
Vdd
Vos/2 Vin/2
+
Vcm
_
_ +
•1V +
_
•2V
• 3.5 V
_
Rs
+
+
_
+ _
Vos/2 Vin/2
Vout
CL
Rs
Fig. 2. Open- loop Differential Gain Measurement
3. Small-Signal Bandwidth and Phase Margin
Vdd
Vin
+ _
Vcm
=2V
+
_
Rs
+
Vout
_
CL
Fig. 3. The Follower Configuration for Small-Signal Bandwidth and
Phase Margin Measurement
In the design problem, you are asked to find both the small-signal bandwidth and the phase
margin under the follower configuration. The follower configuration required is shown in Fig. 3.
Note that you do not need to add any offset voltage sources for the follower configuration, as it
will automatically balance itself due to the feedback. The output DC level will not be exactly 2V
(the nominal output common mode voltage), instead the input offset voltage will be added to it
(<200 µV).
The small signal bandwidth (-3dB bandwidth) in the follower configuration will turn out to be
pretty close to the unity-gain frequency, fT . (Recall that the gain of the follower is ~1.) One of
the common mistakes is that you might choose the positive and the negative inputs incorrectly,
such that you create a limiter circuit rather than a buffer (follower) circuit. There is an easy way
to find out the correct input polarities: if you increase the input voltage at the positive input node,
then the output voltage should also increase, so you could test it by applying a small DC twist at
the inputs.
As for the phase margin, you have to evaluate the ‘loop transmission’ of the follower circuit by
the definition of the phase margin, which leads yo u to cut the loop at a good place and to
measure the gain and phase characteristics. With some considerations on the (-) sign, you will
have to have the phase start off from 0 degrees at low frequencies (not from +180 degrees).
4. Output Swing
Our specification of output swing is based on the change in the small signal gain in the DC
output level. Define the small signal gain as the gain when the output DC level is 2 V. The
output swing specification requires you to guarantee that your small signal gain does not
decrease below the gain spec (>100 V/V) even when the output DC level is just within 250 mV
of the rails.
One easy test setup will be similar to the one in Fig. 2. All that you need to find out are the two
offset voltages require to make your output DC level equal to 3.25V and 0.25V. Adjust the
output DC level using these offset voltages and find the small signal gain using AC analysis.
Another method to test your output swing is shown in Fig. 4. The OP Amp under test is forced to
maintain its output at a desired DC level (3.25V or 0.25V) by an external (and ideal) amplifier.
There is an RC filter at the output of the external amplifier which has a very large time constant
(~zero bandwidth). This filter basically feeds back only DC and blocks any AC signals such that
the OP Amp is an open circuit for an ac signal. The source Vin is the input signal of a low
frequency (<~10 Hz). This method will give you results almost similar to the method described
earlier, but the absence of offset measurement makes it easier to use. We will be using this setup
in the grading.
Another method to test your output swing is shown in Fig. 4. The OP Amp under test is forced to
maintain its output at a desired DC level (3.25V or 0.25V) by an external (and ideal) amplifier.
There is an RC filter at the output of the external amplifier which has a very large time constant
(~zero bandwidth). This filter basically feeds back only DC and blocks any AC signals such that
the OP Amp is an open circuit for an ac signal. The source Vin is the input signal of a low
frequency (<~10 Hz). This method will give you results almost similar to the method described
earlier, but the absence of offset measurement makes it easier to use. We will be using this setup
in the grading.
Vdd
Vin
Vcm
+
=2V
Rs
_
+
Vout
_
+
_
CL
+
R=1G
_
Vref
C=1F
Ideal Amp
• 3.25V
• 0.25V
(E-element)
Fig. 4. Output Swing Measurement
5. Power
Power can be directly read from the SPICE output file. Make sure that you include .OP in your
input file to perform DC operating point analysis. .OP analysis will give you DC voltages,
currents, and power. Also do not forget to set the temperature correctly to 25 °C using .TEMP 25
since it greatly affects your power consumptions.
6. Rise- and Fall-times
Fig. 5. shows the simulation setup to measure the follower rise-time and fall-time. The OP Amp
is wired in a follower configuration. A step source of 1 V to 3 V and of 3 V to 1 V is realized by
PULSE or PWL function in transient analysis. We recommend you to have finite rise- and falltimes for the input source (e.g. 10 ns). At the output, you should measure the time which the
output takes to change from 10% to 90% of the final value.
Vdd
Rs
+
Vin
+
_
Vout
_
CL
Fig. 5. Rise and Fall Time Measurement
7. Common-mode Gain and CMRR
The test circuit in Fig. 6. can be used to find the common mode gain of your circuit with an AC
analysis. Knowing your differential gain and the common mode gain, you can calculate your
CMRR.
Vdd
Vos/2 Rs
Vin
+ _
Vcm
=2V
+
_
+ _
+
_
_
+
Vos/2 Rs
Vout
CL
Fig. 6. Common Mode Gain Measurement
8. SPICE Input Deck Format
Please strictly follow the guidelines given in the accompanied handout on Project Submission
Procedure.
9. Non-Minimum Length Transistors
Level 3 models that we are providing are good enough only for 0.5um long devices. If you want
to use a longer device, you would need to stack up minimum size (0.5um) devices to make the
long one. To ease your job, we have provided the subcircuits that represent longer transistors:
transistors.lib at our class web page. You should copy these files toy our own directory and
include them with your SPICE deck using .include command. Make sure that you only use our
provided subcircuit names.
10. Some Additional Important Points
1) Always measure any quantity using .measure statement if you need accuracy (e.g. offset
voltages.) Mwaves can only give you a rough idea if you are not careful enough. Always
measure values exactly at the point where you performed your analysis, otherwise you
will get interpolated results.
2) .AC performs an analysis on the extracted AC model, it does not perform an analysis on
the original circuit. You can easily see voltage swings beyond Vdd because .AC analysis
forgets about original circuit and works only on the AC models. Do not get confused by
this. On the other hand, .TRAN performs analyses on the original circuit.
3) If you are using wrong offset voltages, some of your transistors may be in triode or cut
off region completely. .AC analysis will extract their AC models in respective regions
and will perform an AC analysis on that model, which will give you completely wrong
answers. BE CAREFUL that you use the right offsets.
Before you look at your analysis results, always make sure that your Vout = Vcm,out =
2V in the SPICE output to verify that you used the correct offset voltages.
4) If your OP Amp is “oscillating” rather than amplifying, yo u will get 0 points for the
project – an oscillator is not acceptable at all. There are some ways to catch this:
- Any kind of oscillations in the output should eventually die out in .TRAN analysis.
If the sustains, then your OP Amp is oscillating.
- Watch out for “internal timestep too small” warnings which indicates oscillations
in most of the cases.
5) Solving the convergence problem
- First of all, check if your SPICE input file has any significant error. One of the
common errors that lead to the convergence problem is to connect the substrate of
PMOS to GND !!
- If you are sure that your circuit does not have any netlist error (including the
typos), then run your SPICE input file to get the initial conditions for each node
voltages. This can be done with the following lines:
.op
.save
In this run, you should not have any .dc, .ac, .tran analyses. If your input file
name is my_input.sp, the .save command will save the initial conditions in the file
my_input.ic. To invoke these initial conditions, you may use the following
command at the beginning of the SPICE input files where you actually
run .dc, .ac, and .tran analyses:
.load ‘my_input.ic’