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FDBL0260N100
N-Channel PowerTrench® MOSFET
100 V, 200 A, 2.6 mΩ
„ Max RDS(on) = 2.6 mΩ at VGS = 10 V, ID = 80 A
Applications
„ Max Qg(tot) = 116 nC at VGS = 10 V, ID = 80 A
„ Industrial Motor Drive
„ UIS Capability
„ Industrial Power Supply
„ RoHS Compliant
„ Industrial Automation
„ Battery Operated tools
„ Battery Protection
„ Solar Inverters
„ UPS and Energy Inverters
„ Energy Storage
„ Load Switch
D
D
S
SS
S
S
G
SS
TOP
G
S
BOTTOM
MO-299A
MOSFET Maximum Ratings TC = 25 °C unless otherwise noted.
Symbol
VDS
Drain to Source Voltage
Parameter
VGS
Gate to Source Voltage
Drain Current -Continuous
-Continuous
ID
TJ, TSTG
±20
V
(Note 5)
TC = 100°C
(Note 5)
140
(Note 4)
1000
Single Pulse Avalanche Energy
PD
Units
V
TC = 25°C
-Pulsed
EAS
Ratings
100
(Note 3)
Power Dissipation
TC = 25°C
Power Dissipation
TA = 25°C
200
866
250
(Note 1a)
Operating and Storage Junction Temperature Range
3.5
-55 to +150
A
mJ
W
°C
Thermal Characteristics
RθJC
Thermal Resistance, Junction to Case
RθJA
Thermal Resistance, Junction to Ambient
(Note 1)
0.6
(Note 1a)
43
°C/W
Package Marking and Ordering Information
Device Marking
FDBL0260N100
Device
FDBL0260N100
©2015 Fairchild Semiconductor Corporation
FDBL0260N100 Rev.1.0
Package
MO-299A
1
Reel Size
-
Tape Width
-
Quantity
-
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FDBL0260N100 N-Channel PowerTrench® MOSFET
November 2015
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
Off Characteristics
BVDSS
ΔBVDSS
ΔTJ
IDSS
IGSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
ID = 250 μA, VGS = 0 V
100
ID = 250 μA, referenced to 25 °C
V
53
VDS = 80 V, VGS = 0 V
VGS = ±20 V, VDS = 0 V
mV/°C
1
±100
μA
nA
4
2.6
V
mΩ
On Characteristics
VGS(th)
rDS(on)
ΔVGS(th)
ΔTJ
gFS
Gate to Source Threshold Voltage
Static Drain to Source On Resistance
Gate to Source Threshold Voltage
Temperature Coefficient
Forward Transconductance
VGS = VDS, ID = 250 μA
VGS = 10 V, ID = 80 A
2
2.7
2.1
ID = 250 μA, referenced to 25 °C
-13
mV/°C
VDS = 10 V, ID = 80 A
170
S
Dynamic Characteristics
Ciss
Coss
Crss
Rg
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
VDS = 50 V, VGS = 0 V,
f = 1 MHz
VGS = 0.5V, f = 1MHz
6175
1330
40
2.6
9265
1995
60
pF
pF
pF
Ω
26
34
47
19
83
11
28
16
42
54
75
34
116
16
ns
ns
ns
ns
nC
nC
nC
nC
0.8
0.8
71
121
200
1000
1.3
1.2
113
194
A
A
Switching Characteristics
td(on)
tr
td(off)
tf
Qg(TOT)
Qg(th)
Qgs
Qgd
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Threshold Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
VDD = 50 V, ID = 80 A,
VGS = 10 V, RGEN = 6 Ω
VGS = 0 to 10 V
VGS = 0 to 2 V
VDD = 50 V,
ID = 80 A
Drain-Source Diode Characteristics
IS
ISM
VSD
trr
Qrr
Maximum Continuous Drain to Source Diode Forward Current
Maximum Pulsed Drain to Source Diode Forward Current
(Note 2)
VGS = 0 V, IS = 80 A
Source to Drain Diode Forward Voltage
VGS = 0 V, IS = 40 A
(Note 2)
Reverse Recovery Time
IF = 80 A, di/dt = 100 A/μs
Reverse Recovery Charge
-
V
ns
nC
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.
RθJC is guaranteed by design while RθCA is determined by the user's board design.
a) 43 °C/W when mounted on a 1 in2 pad of 2 oz copper.
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0 %.
3. EAS of 866 mJ is based on starting TJ = 25 °C, L = 0.3 mH, IAS = 76 A, VDD = 90 V, VGS = 10 V. 100% test at L = 0.1 mH, IAS = 110 A.
4. Pulsed Id please refer to Figure “Forward Bias Safe Operating Area” for more details.
5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design.
©2015 Fairchild Semiconductor Corporation
FDBL0260N100 Rev.1.0
2
www.fairchildsemi.com
FDBL0260N100 N-Channel PowerTrench® MOSFET
Electrical Characteristics TJ = 25 °C unless otherwise noted.
VGS = 10 V
3
VGS = 8 V
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
ID, DRAIN CURRENT (A)
300
VGS = 7 V
200
VGS = 6.5 V
VGS = 6 V
100
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0
0.0
0.5
1.0
1.5
2.0
VGS = 6 V
2
VGS = 6.5 V
1
0
2.5
0
100
rDS(on), DRAIN TO
2.0
1.8
1.6
1.4
1.2
1.0
0.8
SOURCE ON-RESISTANCE (mΩ)
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
20
ID = 80 A
VGS = 10 V
0.6
-75 -50 -25 0 25 50 75 100 125 150 175
TJ, JUNCTION TEMPERATURE (oC)
IS, REVERSE DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
VDS = 5 V
150
TJ = 175 oC
TJ = 25 oC
TJ = -55 oC
2
3
4
5
6
ID = 80 A
10
TJ = 150 oC
5
TJ = 25 oC
4
5
6
7
8
9
300
100
VGS = 0 V
10
TJ = 175 oC
1
TJ = 25 oC
0.1
0.01
TJ = -55 oC
0.001
0.0
7
0.2
0.4
0.6
0.8
1.0
VGS, GATE TO SOURCE VOLTAGE (V)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure 6. Source to Drain Diode
Forward Voltage vs. Source Current
©2015 Fairchild Semiconductor Corporation
FDBL0260N100 Rev.1.0
10
Figure 4. On-Resistance vs. Gate to
Source Voltage
200
0
15
VGS, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
50
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0
Figure 3. Normalized On Resistance
vs. Junction Temperature
100
300
Figure 2. Normalized On-Resistance
vs. Drain Current and Gate Voltage
2.4
250
200
ID, DRAIN CURRENT (A)
Figure 1. On Region Characteristics
300
VGS = 10 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VDS, DRAIN TO SOURCE VOLTAGE (V)
2.2
VGS = 8 V
VGS = 7 V
3
1.2
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FDBL0260N100 N-Channel PowerTrench® MOSFET
Typical Characteristics TJ = 25 °C unless otherwise noted.
VGS, GATE TO SOURCE VOLTAGE (V)
10
10000
ID = 80 A
Ciss
VDD = 25 V
8
6
CAPACITANCE (pF)
VDD = 50 V
VDD = 75 V
4
1000
Coss
100
2
0
f = 1 MHz
VGS = 0 V
0
20
40
60
80
10
0.1
100
1
10
100
VDS, DRAIN TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics
Figure 8. Capacitance vs. Drain
to Source Voltage
1000
2000
1000
ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
Crss
100
TJ = 25 oC
10
TJ
1
0.001
0.01
0.1
= 150 oC
1
10
100
10 μs
100
10
THIS AREA IS
LIMITED BY rDS(on)
100 μs
SINGLE PULSE
TJ = MAX RATED
1 ms
RθJC = 0.6 oC/W
1
TC = 25 oC
0.1
0.1
1000 10000
tAV, TIME IN AVALANCHE (ms)
10 ms
100 ms/DC
CURVE BENT TO
MEASURED DATA
1
10
100
1000
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 10. Forward Bias Safe
Operating Area
Figure 9. Unclamped Inductive
Switching Capability
100000
P(PK), PEAK TRANSIENT POWER (W)
SINGLE PULSE
o
RθJC = 0.6 C/W
o
TC = 25 C
10000
1000
100
10
-5
10
-4
10
-3
-2
10
10
-1
10
1
t, PULSE WIDTH (sec)
Figure 11. Single Pulse Maximum Power Dissipation
©2015 Fairchild Semiconductor Corporation
FDBL0260N100 Rev.1.0
4
www.fairchildsemi.com
FDBL0260N100 N-Channel PowerTrench® MOSFET
Typical Characteristics TJ = 25 °C unless otherwise noted.
r(t), NORMALIZED EFFECTIVE TRANSIENT
THERMAL RESISTANCE
2
1
0.1
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
PDM
t1
t2
0.01
NOTES:
ZθJC(t) = r(t) x RθJC
RθJC = 0.6 oC/W
Peak TJ = PDM x ZθJC(t) + TC
Duty Cycle, D = t1 / t2
SINGLE PULSE
0.001
-5
10
-4
10
-3
-2
10
10
-1
10
1
t, RECTANGULAR PULSE DURATION (sec)
Figure 12. Junction-to-Case Transient Thermal Response Curve
©2015 Fairchild Semiconductor Corporation
FDBL0260N100 Rev.1.0
5
www.fairchildsemi.com
FDBL0260N100 N-Channel PowerTrench® MOSFET
Typical Characteristics TJ = 25 °C unless otherwise noted.
9.70
9.90
DETAIL "A"
0.60
0.80
B
0.40
0.60
(0.40)
11.58
11.78
10°
(3.30) (2X)
0.50
0.70
1
0.60
0.80
10.28
10.48
0.20
C A B
DETAIL "A"
8
0.60
0.70
0.90
1.20
(0.35)
(8X)
0.25
0.20
7X
C A B
C
8.40
10.20
TOP VIEW
5.10
4.45
DETAIL "B"
6.64
0.20 C
0.40
0.60
2.20
2.40
2.95
8.10
4.99
2.04
0.10 C
2.90
1.46
C
6.64
SIDE VIEW
0.86
13.28
0.60
2.80
1
A
9.80
10.00
0.20
C A B
0.80
8
1.20
LAND PATTERN
RECOMMENDATION
(8.00)
1.90
2.10
5.19
4.73
0.10
(2X)
(7.15) 6.55
6.75
2.60
(2X)
3.30
(2X)
5.89
1.20
3X
3.75
0.65
2X
7.40
7.60
(8.30)
BOTTOM VIEW
10°
(0.35)
DETAIL "B"
NOTES: UNLESS OTHERWISE SPECIFIED
A) PACKAGE STANDARD REFERENCE:
JEDEC MO-299, ISSUE A, DATED NOVEMBER
2009.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH. MOLD FLASH OR
BURRS DOES NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-1994.
E) DRAWING FILE NAME: MKT-PSOF08AREV3
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intended to be an exhaustive list of all such trademarks.
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SuperSOT-3
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Sync-Lock™
®*
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仙童®
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Advance Information
Formative / In Design
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
Definition
Datasheet contains the design specifications for product development. Specifications may change
in any manner without notice.
Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild
Semiconductor reserves the right to make changes at any time without notice to improve design.
Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make
changes at any time without notice to improve the design.
Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor.
The datasheet is for reference information only.
Rev. I77
© Fairchild Semiconductor Corporation
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FDBL0260N100