IDT74LVCH16245A
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
IDT74LVCH16245A
3.3V CMOS 16-BIT
BUS TRANSCEIVER
WITH 3-STATE OUTPUTS,
5 VOLT TOLERANT I/O AND BUS-HOLD
FEATURES:
DESCRIPTION:
–
–
Typical tSK(0) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– 0.635mm pitch SSOP, 0.50mm pitch TSSOP
and 0.40mm pitch TVSOP packages
– Extended commercial range of -40°C to +85°C
– VCC = 3.3V ±0.3V, Normal Range
– VCC = 2.7V to 3.6V, Extended Range
– CMOS power levels (0.4µ W typ. static)
– All inputs, outputs and I/O are 5 Volt tolerant
– Supports hot insertion
Drive Features for LVCH16245A:
– High Output Drivers: ±24 mA
– Reduced system switching noise
This 16-bit bus transceiver is built using advanced dual metal CMOS
technology. This high-speed, low power transceiver is ideal for asynchronous communication between two busses (A and B). The Direction and
Output Enable controls are designed to operate this device as either two
independent 8-bit transceivers or one 16-bit transceiver. The direction
control pin (DIR) controls the direction of data flow. The output enable pin
(OE) overrides the direction control and disables both ports. All inputs are
designed with hysteresis for improved noise margin.
All pins can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V supply system.
The LVCH16245A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
APPLICATIONS:
The LVCH16245A has “bus-hold” which retains the inputs' last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
Functional Block Diagram
1 DIR
24
1
2 DIR
25
48
1 OE
1A 1
2 OE
47
2A 1
2
36
13
1B 1
1A 2
2A 2
3
14
1B 2
1A 3
2B 2
33
44
2A 3
16
5
1B 3
1A 4
2B 3
32
43
2A 4
6
17
1B 4
2B 4
41
30
1A 5
2A 5
8
19
1B 5
40
2A 6
9
20
1B 6
38
2A 7
2B 6
27
11
22
1B 7
1A 8
2B 5
29
1A 6
1A 7
2B 1
35
46
2B 7
37
2A 8
26
23
12
1B 8
2B 8
EXTENDED COMMERCIAL TEMPERATURE RANGE
MARCH 1999
1
c
1999 Integrated Device Technology, Inc.
DSC-4596/-
IDT74LVCH16245A
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(1)
Symbol
VTERM(2)
Description
Terminal Voltage with Respect to GND
Max.
– 0.5 to +6.5
Unit
V
VTERM(3)
Terminal Voltage with Respect to GND
– 0.5 to +6.5
V
1 DIR
1
48
1 OE
TSTG
Storage Temperature
– 65 to +150
°C
1B 1
2
47
1A 1
IOUT
DC Output Current
– 50 to +50
mA
IIK
IOK
ICC
Continuous Clamp Current,
VI < 0 or VO < 0
Continuous Current through
– 50
mA
±100
mA
ISS
each VCC or GND
1B 2
3
46
GND
4
45
1B 3
5
1B 4
44
6
1A 2
GND
1A 3
43
1A 4
V CC
7
42
V CC
1B 5
8
41
1A 5
1B 6
9
40
1A 6
GND
10
39
GND
1B 7
11
38
1A 7
1B 8
12
1A 8
2B 1
13
SO48-1 37
SO48-2
SO48-3 36
2B 2
14
GND
LVC Link
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.
CAPACITANCE (TA = +25OC, f = 1.0MHz)
2A 1
Symbol
CIN
Parameter(1)
Input Capacitance
Conditions
VIN = 0V
Typ.
4.5
Max.
6
Unit
pF
35
2A 2
COUT
VOUT = 0V
6.5
8
pF
15
34
GND
VIN = 0V
6.5
8
pF
2B 3
16
33
2A 3
Output
Capacitance
I/O Port
Capacitance
2B 4
17
32
2A 4
V CC
18
31
V CC
2B 5
19
30
2A 5
2B 6
20
29
2A 6
GND
21
28
GND
2B 7
22
27
2A 7
2B 8
23
26
2A 8
2 DIR
24
25
2 OE
CI/O
LVC Link
NOTE:
1. As applicable to the device type.
PIN DESCRIPTION
Pin Names
xOE
Description
Output Enable Input (Active LOW)
xDIR
Direction Control Input
xAx
Side A Inputs or 3-State Outputs (1)
xBx
Side B Inputs or 3-State Outputs (1)
NOTE:
1. These pins have “Bus-hold”. All other pins are standard inputs,
outputs, or I/Os.
SSOP/ TSSOP/ TVSOP
TOP VIEW
FUNCTION TABLE (each 8-bit section) (1)
Inputs
xOE
xDIR
L
L
B Data to A Bus
L
H
A Data to B Bus
H
X
Isolation
Outputs
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
c 1998 Integrated Device Technology, Inc.
2
DSC-123456
IDT74LVCH16245A
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = –40OC to +85OC
Symbol
VIH
VIL
Parameter
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
Min.
1.7
Typ.(1)
—
Max.
—
VCC = 2.7V to 3.6V
2
—
—
VCC = 2.3V to 2.7V
—
—
0.7
VCC = 2.7V to 3.6V
—
—
0.8
Test Conditions
Input LOW Voltage Level
Unit
V
V
IIH
IIL
IOZH
Input Leakage Current
VCC = 3.6V
VI = 0 to 5.5V
—
—
±5
µA
High Impedance Output Current
VCC = 3.6V
VO = 0 to 5.5V
—
—
±10
µA
IOZL
(3-State Output pins)
IOFF
Input/Output Power Off Leakage
VCC = 0V, VIN or VO ≤ 5.5V
—
—
±50
µA
VIK
Clamp Diode Voltage
VCC = 2.3V, IIN = – 18mA
—
– 0.7
– 1.2
V
VH
Input Hysteresis
VCC = 3.3V
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = 3.6V
∆ICC
Quiescent Power Supply
Current Variation
—
100
—
mV
VIN = GND or VCC
—
—
10
µA
3.6 ≤ VIN ≤ 5.5V(2)
—
—
10
—
—
500
One input at VCC - 0.6V
other inputs at VCC or GND
µA
LVC Link
NOTES:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2. This applies in the disabled state only.
BUS-HOLD CHARACTERISTICS
Symbol
IBHH
Parameter(1)
Bus-Hold Input Sustain Current
VCC = 3.0V
Test Conditions
VI = 2.0V
Min.
– 75
Typ.(2)
—
Max.
—
VI = 0.8V
75
—
—
VI = 1.7V
—
—
—
VI = 0.7V
—
—
—
VI = 0 to 3.6V
—
—
± 500
IBHL
IBHH
Bus-Hold Input Sustain Current
VCC = 2.3V
IBHL
IBHHO
Bus-Hold Input Overdrive Current
VCC = 3.6V
Unit
µA
µA
µA
IBHLO
LVC Link
NOTES:
1. Pins with Bus-hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3
IDT74LVCH16245A
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
VOH
Parameter
Output HIGH Voltage
VCC
Test Conditions(1)
= 2.3V to 3.6V
IOH = – 0.1mA
IOH = – 6mA
2
—
VCC = 2.3V
IOH = – 12mA
1.7
—
2.2
—
VCC = 3.0V
Output LOW Voltage
Max.
—
VCC = 2.3V
VCC = 2.7V
VOL
Min.
VCC – 0.2
2.4
—
VCC = 3.0V
IOH = – 24mA
2.2
—
VCC = 2.3V to 3.6V
IOL = 0.1mA
—
0.2
VCC = 2.3V
IOL = 6mA
—
0.4
IOL = 12mA
—
0.7
VCC = 2.7V
IOL = 12mA
—
0.4
VCC = 3.0V
IOL = 24mA
—
0.55
Unit
V
V
LVC Link
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate VCC range. TA = – 40°C to +85°C.
OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C
Symbol
CPD
Parameter
Power Dissipation Capacitance per Transceiver Outputs enabled
CPD
Power Dissipation Capacitance per Transceiver Outputs disabled
SWITCHING CHARACTERISTICS
Test Conditions
CL = 0, f = 10Mhz
Parameter
Propagation Delay
xAx to xBx, xBx to xAx
Output Enable Time
xOE to xAx or xBx
Output Disable Time
xOE to xAx or xBx
Output Skew(2)
Unit
pF
4
pF
(1)
VCC = 2.7V
Symbol
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSK(o)
Typical
40
VCC = 3.3V±0.3V
Min.
—
Max.
4.7
Min.
1
Max.
4
—
6.7
1.5
5.5
—
7.1
1.5
6.6
—
—
—
1
NOTES:
1. See test circuits and waveforms. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
Unit
ns
ns
ns
ns
IDT74LVCH16245A
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
PROPAGATION DELAY
Symbol
VLOAD
VCC(1)= 3.3V ±0.3V
VCC(1) = 2.7V
VCC(2)= 2.5V ±0.2V Unit
2 x Vcc
V
6
6
VIH
2.7
2.7
Vcc
V
VT
1.5
1.5
VCC / 2
V
VLZ
300
300
150
mV
VHZ
300
300
150
CL
50
50
30
V IH
VT
0V
SAME PHASE
INPUT TRANSITION
tPLH
t PHL
tPLH
t PHL
V OH
VT
V OL
OUTPUT
V IH
VT
0V
OPPOSITE PHASE
INPUT TRANSITION
mV
pF
LVC Link
LVC Link
TEST CIRCUITS FOR ALL OUTPUTS
ENABLE AND DISABLE TIMES
Pulse (1, 2)
Generator
V IN
t PZL
GND
V OUT
OUTPUT
SW ITCH
NORMALLY
CLO SED
LOW
tPZH
OUTPUT SW ITCH
NORMALLY
OPEN
HIGH
D.U.T.
500 Ω
RT
CL
LVC Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
INPUT
DATA
INPUT
GND
ASYNCHRONOUS
CONTROL
Open
SYNCHRONOUS
CONTROL
LVC Link
tPHZ
V OH
V HZ
VT
0V
0V
tS U
V IH
VT
0V
V IH
VT
0V
V IH
VT
0V
V IH
VT
0V
tH
tR EM
t SU
tH
LVC Link
V IH
PULSE WIDTH
VT
0V
t PHL1
t SK (x)
V LZ
V OL
TIM ING
INPUT
V OH
OUTPUT 1
V LOAD/2
SET-UP, HOLD, AND RELEASE TIMES
Switch
VLOAD
tPLH1
V LOAD/2
VT
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
SWITCH POSITION
OUTPUT SKEW - tsk (x)
0V
t PLZ
LVC Link
NOTE:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
V IH
VT
CONTROL
INPUT
Open
500 Ω
DISABLE
ENABLE
V LOAD
V CC
t SK (x)
LOW -HIGH-LOW
PULSE
VT
V OL
tW
V OH
HIGH-LOW -HIGH
PULSE
VT
V OL
OUTPUT 2
VT
VT
LVC Link
t PLH2
tPHL2
t SK (x) = tPLH2 - tPLH1 or tPHL2 - tP HL1
LVC Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74LVCH16245A
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
XX
LVC
Tem p. R ange
X
XX
XXXX
XX
Bus-Hold
Fam ily
Device Type
Package
PV
PA
PF
Shrink Sm all Outline Package (SO48-1)
Thin Shrink Sm all Outline Package (SO48-2)
Thin Very Sm all Outline Package (SO48-3)
245A
16-Bit Bus Transceiver with 3-State Outputs
16
Double-Density with Resistors, ±24m A
H
Bus-hold
74
-40°C to +85 °C
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6