PROBLEMS
For each of the following problems assume the transistors are 2N3904 (NPN) and 2N3906 (PNP)
respectively as appropriate. Use a nominal ß of 120 and VBE = 0.7v. In each case calculate the DC
operating conditions using the PWL ‘flag’ transistor model, and apply the simplified incremental
parameter model to calculate the voltage gain for a 1KHz sinusoidal signal input. Compare calculated
values to those obtained from a computer simulation.
IncParam Problem # 1
VS
1 0 AC 1
RS
1 2
1K
CIN
2 3
50U
RB11 6 3
68K
RB12 3 0
33K
Q1
5 3 4 Q2N3904
RE1
4 0
2.2K
CE1
4 0
50U
RC1 6 5
3.9K
CC
5 7
50U
RB22 6 7
68K
RB21
7 0
33K
Q2
9 7 8 Q2N3904
RE2
8 0
2.2K
CE2
8 0
50U
RC2 6 9
3.9K
VCC 6 0 DC 10
.PROBE
.LIB EVAL.LIB
.OP
.AC LIN 1 1K 1K
.PRINT AC VDB(9)
.END
1) Answer
The capacitor coupling of the two stages means the DC bias calculations for each of the two identical
stages is distinct.
Note: PSpice computes the current as 1.09 ma, and rbe as 3.8KΩ. Node voltages computed are:
(1) 0.0000
(5) 5.7327
(9) 5.7327
( 2) 0.0000 ( 3) 3.0918
( 6) 10.0000 ( 7) 3.0918
( 4) 2.4246
( 8) 2.4246
The incremental circuit of the amplifier is as shown below. As described in the notes the capacitance
values are large enough to make reactances negligible compared to other circuit resistances. A ladder
expansion is perhaps the simplest analysis to apply.
Introductory Electronics Notes
The University of Michigan-Dearborn
50-1
Copyright © M H Miller: 2000
revised
PSpice computes a value of 78.5 db for the voltage gain.
IncPar Prob #2
VS
1
0
AC
1
RS
1
2
10K
CIN
2
3
100U
RB1
6
3
33K
RB2
3
0
10K
Q1
435
Q2N3904
RE1
5
0
2.2K
CE1
5
0
100U
RC1
6
4
3.3K
Q2
847
Q2N3906
RE2
6
7
1.5K
CE2
7
0
100U
RC2
8
0
2.2K
VCC
6
0
DC
12
.OP
.LIB EVAL.LIB
.AC LIN 1 1K 1K
.PRINT AC
VDB(4) VDB(8)
.END
Assume (to be verified) as discussed before that the Q2 base current can be neglected compared to the Q1
collector current. Calculate the Q1 emitter current, use this to estimate the voltage across the Q2 emitter
resistor, and so the Q2 emitter current. The PSpice computed currents are shown to the right of the
estimates. and computed node voltages are shown below.
(1) 0.0000
(5) 2.0778
Introductory Electronics Notes
The University of Michigan-Dearborn
NODE VOLTAGES
(2) 0.0000
(3) 2.7398
(6) 12.0000
(7) 9.6389
50-2
(4) 8.9277
(8) 3.4479
Copyright © M H Miller: 2000
revised
The incremental equivalent circuit is drawn below and a 'ladder' analysis used to compute the voltage gain.
The computed voltage gain at 1KHz is 1570 (63.9 db).
IncPar Prob #3
VS 1
0
RS 1
2
RB1
6
Q1 3 2 4
RE1A
4
RE1B
5
CE1
5
RC1
6
AC
1
10K
2
Q2N3904
5
0
0
3
Q2 9 3 8
Q2N3906
RE2A
6
7
RE2B
7
8
CE2
7
0
RC2
9
0
VCC
6
0
DC
.OP
.LIB EVAL.LIB
.AC LIN 1 1K 1K
.PRINT AC
V(9) VDB(9)
.END
39K
100
2.2K
100U
3.9K
3.3K
100
100U
6.8K
12
This is a modest modification of Problem #2, in which for reasons considered elsewhere only part of the
emitter resistance in each stage is bypassed. The DC bias calculations are shown below., together with
PSpice computations.
Introductory Electronics Notes
The University of Michigan-Dearborn
50-3
Copyright © M H Miller: 2000
revised
(1) 0.0000
(5) 1.6732
(9) 4.4679
NODE VOLTAGES
(2) 2.4054
(3) 9.0666
(6) 12.0000
(7) 9.8220
(4) 1.7493
(8) 9.7561
The incremental equivalent circuit is drawn next; the essential difference in this problem from the last is the
inclusion of a small emitter resistor. Note that the current through an emitter resistor is 121i, producing
exactly the same voltage drop as a resistance 121 larger in the base branch. Making this transformation
simplifies the analysis.
PSpice computes a gain of 664 or 56.4 db.
IncPar Prob #4
VS 1
0
AC
1
RS 1
2
1K
CIN
2
3
Q1 5 3 0
Q2N3904
RC1
7
5
Q2 6 5 4
Q2N3904
RC2
7
6
RE2
4
0
RB4
3
47K
VCC
7
0
DC
.OP
.LIB EVAL.LIB
.AC LIN 1 1K 1K
.PRINT AC
V(6) VDB(6)
.END
100U
3.3K
2.2K
1K
9
This is a shunt-series pair. As described before neglect the base current of Q2 relative to the collector
current of Q1, and write a loop equation as shown below. From the estimated Q1 collector current
determine an estimate for the Q2 emitter voltage, and from this the Q2 emitter current. The calculations
and the PSpice computed values are shown below.
Introductory Electronics Notes
The University of Michigan-Dearborn
50-4
Copyright © M H Miller: 2000
revised
The incremental parameter circuit is drawn below. The analysis of the circuit is straightforward, e.g., a
nodal analysis. Alternatively use PSpice to analyze the circuit. In either case determine the output
voltage (which for a unit input voltage is the voltage gain) to be 79.3 (38 dB). The gain computed with
PSpice is 80.18 (38.08 dB).
IncPar Problem #5
VS
1
0
AC
1
RS
1
2
1K
CIN
2
3
100U
Q1
430
Q2N3904
RC1
5
4
6.8K
Q2
649
Q2N3904
RC2
5
6
3.9K
CO
6
7
100U
RL
7
0
10K
RE2
9
0
2.5K
RB1
3
8
150K
RB2
8
9
150K
CBP
8
0
100U
VCC
5
0
DC
10
.OP
.LIB EVAL.LIB
.AC LIN 1 1K 1K
.PRINT AC
V(7) VDB(7)
.END
This problem illustrates a circuit configuration which is different for the DC biasing from that for the
incremental circuit. The DC circuit is a shunt-series pair as in the preceding two problems and the DC
calculations are formally the same as before.
Introductory Electronics Notes
The University of Michigan-Dearborn
50-5
Copyright © M H Miller: 2000
revised
(1) 0.0000
(5) 10.0000
(9) 2.7692
NODE VOLTAGE
(2) 0.0000
(3) .6637
(6) 5.6840
(7) 0.0000
(4) 3.4369
(8) 1.7164
The capacitor at node 8 is effectively an AC ground, so that the incremental parameter circuit is as shown
below. The gain calculation then is straightforward. The gain computed with PSpice is 203.1 (46.1db).
6) Calculate the voltage gain of the amplifier
circuit drawn on the right, omitting the 22 KΩ
resistor connected with dashed lines. Then assume,
as an approximation, that this non inverting
amplifier can be considered to be an idealized
opamp. i.e., the voltage gain is ‘high’, the input
resistance is ‘high’, etc.. Apply feedback as
shown, and compare the computed voltage gain
with the idealized opamp expectation of a voltage
gain of 11. Note: The capacitor is used to block
involvement of the feedback resistor in the DC
biasing.
Introductory Electronics Notes
The University of Michigan-Dearborn
50-6
Copyright © M H Miller: 2000
revised
IncPar Problem #6
VS 1
0
AC
1
RS 1
2
1K
CIN 2
3
100U
RB11 4
3
68K
RB12 3
0
33K
Q1 5 3 6
Q2N3904
RC1 4
5
3.9K
RE1 6
0
2.2K
C12 5
7
100U
RB21 4
7
68K
RB22 7
0
33K
Q2 8 7 9
Q2N3904
RC2 4
8
3.9K
RE2 9
0
2.2K
CE2 9
0
100U
CFB 8
10
100U
RFB 10
0
22K
VCC 4
0
DC
10
.OP
.LIB EVAL.LIB
.AC LIN 1 1K 1K
.PRINT
AC
V(8) VDB(8)
.END
The netlist above assumes the 22KΩ feedback resistor RFB is connected to ground to approximate the
disconnected state. The DC biasing of the two stages is disjoint because of the interstage coupling
capacitor, and
The incremental parameter equivalent circuit is drawn below, and the voltage gain calculated.
Introductory Electronics Notes
The University of Michigan-Dearborn
50-7
Copyright © M H Miller: 2000
revised
If the non-inverting amplifier is approximated by an
idealized amplifier, and the feedback added(see
figure) the voltage gain is 11 (20.8db). PSpice
computes a smaller gain (as is to be expected) of 9.6
(19,65 db).
Introductory Electronics Notes
The University of Michigan-Dearborn
50-8
Copyright © M H Miller: 2000
revised