STPAC02F2
IPAD™
RF Detector for power amplifier control with internal temperature compensation
Main product characteristics
■
0.8 to 2.5 GHz frequency range
■
Detection diode voltage drop compensation
■
Temperature compensation
■
Fast response time
■
Low Power consumption
■
Chip Scale device
■
Low parasitic impedance
■
Lead free package
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Description
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Order code
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Benefits
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Flip-Chip package
(8 Bumps)
The STPAC02F2 is an integrated RF detector for
power control chain. It has been developed to
convert the RF signal coming from the external
coupler into a DC signal usable by the mobile
digital stage. It is based on the use of two similar
diodes, one assuming the signal detection while
the second one is used to compensate the
ambient temperature effect. A biasing stage
suppresses the detection diode drop voltage
effect. The use of the IPAD technology allows the
RF front-end designer to save PCB area and to
drastically suppress the parasitic inductances of
the package.
Target applications are cellular phones and PDA
using GSM, DCS, PCS, AMPS, TDMA, CDMA
and 800 MHz to 2100 MHz frequency ranges.
■
3
2
1
OUT
Not
used
GND
GND
GND
B
RFin
GND
VBias
C
A
Part number
Marking
STPAC02F2
RB
The use of IPAD technology allows the RF
front-end designer to save PCB area and to
drastically suppress the parasitic inductances.
May 2006
Rev 1
1/7
www.st.com
7
Characteristics
1
STPAC02F2
Characteristics
Figure 1.
Functional diagram
Antenna
Coupler
Bias voltage
VBIAS
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r characteristics (T = 25° C)
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RF input
DC output
OUT
Low pass
filter
RF detector
Thermal
compensation
STPAC02F2
GND
Table 1.
Symbol
Absolute ratings (Tamb = 25° C)
Value
Unit
Bias voltage
5
V
PRF
RF power at the RF input
20
dbm
FOP
Operating frequency range
0.8 to 2.5
GHz
VPP
ESD level as per MIL-STD 883E method 3015.7
notice 8 (HBM)
250
V
TOP
Operating temperature range
- 30 to + 85
°C
TSTG
Storage temperature range
- 55 to 150
°C
VBIAS
Parameter and test conditions
amb
Table 2.
Symbol
2/7
Parameters related to bias voltage
Parameter
VBIAS
Operating bias voltage
IBIAS
Bias current
Test conditions
VBIAS = 3.3 V
Min.
Typ.
Max.
Unit
2.3
2.8
3.3
V
1.1
1.6
mA
STPAC02F2
Table 3.
Characteristics
Parameters related to detection function (VBIAS = 2.8 V,
DC output load = 200 kΩ)
Symbol
VDCout
∆VDCout
Parameter
Test conditions
DC output voltage
(see Figure 2.)
DC output voltage variation
(see Figure 2.)
Min
Typ
Max
F = 1.75 GHz, PRF = 10 dbm
0.63
0.69
0.75
F = 1.75 GHz, PRF = - 20 dbm
0.20
0.22
0.24
F = 0.9 GHz, PRF = 10 dbm
0.69
0.75
0.83
F = 0.9 GHz, PRF = - 20 dbm
0.20
0.22
0.24
Unit
V
2.3 V < VBIAS < 3.3 V,
F = 1.85 GHz, PRF =10 dbm
100
mV
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Table 4.
Parameters related to response time (VBIAS = 2.8 V,
DC output load = 200 kΩ)
Symbol
Parameter
Test conditions
Min.
Typ.
tVBIAS
Delay at VBIAS ON
(see Figure 4.)
VBIAS from 0 to 3 V
tRFon
Delay at RF ON
(see Figure 3.)
PRF from 0 to 20 dbm
0.2
tRFoff
Delay at RF OFF
(see Figure 3.)
PRF from 20 to 0 dbm
0.2
Figure 2.
VDC output measurement circuit
and temperature compensation
measurement
Figure 3.
RF Power ON/OFF response time
set-up
RF power amplifier
RF
Generator
STPAC02
RF in
STPAC02
OUT
OUT
DC out
voltage
Power
supply
V
Bias
voltage
RF power amplifier
RF in
Unit
1
Climatic Chamber
-30ºC < T amb < +85°C
RF
Generator
Max.
RF in
RF scope
Bias voltage
RLOAD
Out
3/7
Characteristics
Figure 4.
STPAC02F2
Power supply turn ON
response time
Figure 5.
RF power amplifier
Delta VOUT (mV/° C)
0.3
OUT
RF in
RF
Generator
Temperature sensitivity versus RF
Power in (VBIAS = 2.8 V,
Freq. = 900 MHz)
STPAC02
0.2
Bias voltage
RF scope
0.1
OUT
t Pon
Figure 6.
0.0
-15
Bias
voltage
Figure 7.
Vout @ 25° C (Vdc)
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1.2
80
1
0.8
0.6
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0.2
Pin (dbm)
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0
-10
-5
0
5
10
d
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Figure 8.
STPAC02 Output voltage
at low RF power
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0.4
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1750MHz
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0.3
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20
(s)
od
900MHz
0.35
15
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Vout @ 25° C (Vdc)
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60
40
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-20
-15
-10
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Pin (dbm)
0
Figure 9.
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-5
0
5
10
15
20
Power detector sensitivity
at low RF power
Sensitivity ( mV/db)
22
17
12
0.25
7
Pin (dbm)
Pin (dbm)
0.2
4/7
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120
1.4
-15
5
Power detector sensitivity
at wide RF power range
140
900MHz
1750MHz
-20
0
Sensitivity (mV/db)
2
1.6
-5
Pin (dbm)
STPAC02 Output voltage
at wide RF power range
1.8
-10
2
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
-10
-8
-6
-4
-2
0
STPAC02F2
2
Packaging information
Packaging information
Figure 10. Flip-Chip dimensions
500 µm ± 50
650 µm ± 65
1.57 mm ± 50 µm
500 µm ± 50
315 µm ± 50
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1.57 mm ± 50 µm
Figure 11. Foot print recommendations Figure 12. Marking
Dot, ST logo
xx = marking
z = manufacturing location
yww = datecode
(y = year
ww = week)
Copper pad Diameter:
250 µm recommended, 300 µm max
Solder stencil opening: 330 µm
Solder mask opening recommendation:
340 µm min for 300 µm copper pad diameter
Figure 13. Flip-Chip tape and reel specification
Dot identifying Pin A1 location
3.5 +/- 0.1
ST
xxx
yww
xxx
yww
ST
xxx
yww
All dimensions in mm
ST
8 +/- 0.3
0.73 +/- 0.05
1.75 +/- 0.1
Ø 1.5 +/- 0.1
4 +/- 0.1
4 +/- 0.1
User direction of unreeling
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available
at: www.st.com.
5/7
Ordering information
3
Note:
STPAC02F2
Ordering information
Ordering code
Marking
Package
Weight
Base qty
Delivery mode
STPAC02F1
RB
Flip-Chip
3.3 mg
5000
Tape and reel
More packing informations are available in the application notes:
AN1235: ''Flip-Chip: Package description and recommendations for use''
AN1751: "EMI Filters: Recommendations and measurements"
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Revision history
Date
Revision
16-May-2006
1
Changes
Initial release.
STPAC02F2
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