NXP DisplayPort-to-DVI/
HDMI level shifters
PTN3300/3300A/
3300B/3301
Signal translation from PCIe and
DisplayPort to DVI and HDMI
To support the new, high-speed motherboard graphics chipsets from Intel, AMD/ATI, nVidia, and
others, these devices provide electrical-level translation from DisplayPort signals to the currentmode outputs required to drive DVI and HDMI displays.
Key features
4High-speed TMDS level shifting up
to 2.25 Gbps per lane (225-MHz
character clock)
4DDC level shifting from 3.3 V (source)
to 5 V (sink) with clock frequency
from 0 to 400 kHz
4DDC active buffering and rise-time
accelerator (PTN3301 only)
4DDC dongle-detect feature
(PTN3301 only)
4HPD level shifting from 0 to 5 V (sink)
to 0 to 3.3 V (source)
4HPD inverting level shifting to 1.1 V
(source; PTN3300A only)
4Integrated 50-Ω termination resistors
for AC-coupled differential inputs
4Single power supply voltage of 3.3 V
±10%
4High ESD resilience to 3.5 kV HBM,
1 kV CDM
4Pin-programmable power-saving
mode disabling TMDS and DDC
channels
4Automatic power-saving mode upon
Hot Plug Detect (HPD) going LOW
4Back-current-safe design on all sinkside terminals
Applications
4Intel and AMD motherboards with
reconfigurable I/O for display
interfaces
4AMD/ATI and nVidia graphics cards
with reconfigurable I/O for display
interfaces
4DisplayPort-to-DVI and -HDMI
dongles and cable assemblies
4Desktop and notebook
motherboards with reconfigurable
display interfaces
These high-speed level shifters translate
from DisplayPort electrical signals to
DVI and HDMI signals. The PTN3300
supports DVI and HDMI for motherboard
and dongle applications up to 1.65
Gbps. The PTN3300A adds an inverting
HPD channel and supports speeds
up to 2.25 Gbps. The PTN3300B is a
high-speed version of the PTN3300,
supporting speeds up to 2.25 Gbps. The
PTN3301 adds active DDC buffering and
rise-time acceleration, plus the HDMI
dongle-detect feature.
The level shifters let chipset vendors
implement reconfigurable I/O on
multimode display sources, and thereby
support multiple display standards while
keeping the number of chipset I/O pins
low. When the chipset is configured to
DVI or HDMI, it outputs TMDS-coded
signals, while the chipset I/O pins
employ AC-coupled PCI Express or
DisplayPort electrical levels. Translation
of the electrical levels is necessary
because DVI and HDMI use DC-coupled,
3.3-V differential signaling.
PTN3300/A/B
The PTN3300/A/B converts four lanes of low-swing, AC-coupled, differential
input signals to DVI-compliant, open-drain, current-steering differential
output signals. It provides level shifting for each differential lane, and
equips each differential output with advanced wave-shaping for optimal
performance. The PTN3300 operates at up to 1.65 Gbps, the PTN3300A
and B versions operate at up to 2.25 Gbps.
OE_N
PTN3300A
input bias
enable
50 Ω
OUT_D4+
OUT_D4−
50 Ω
IN_D4+
IN_D4−
enable
input bias
enable
The PTN3300A is identical to PTN3300B, with the exception that its HPD
channel is a logic-inverter function, and level shifts, on the source side, to a
1.1-V level instead of a 3.3-V logic level.
50 Ω
IN_D3+
IN_D3−
A DDC channel (clock and data lines) level shifts between 3.3 V on the
source side and 5 V on the sink side. The DDC channel uses pass-gate
technology, so it can level-shift and disable the clock and data lines,
isolating the source from the sink. The DDC level shifting is back-power
safe, to disallow back-drive current when the power is off
or when DDC is not enabled.
enable
input bias
enable
50 Ω
The PTN3300/A/B also supplies a single-ended, active buffer for voltage
translation of the HPD signal, from 5 V on the sink side to 3.3 V on the
source side. An integrated 200-kΩ pull-down resistor on the HPD sink
input guarantees “input LOW” when no display is plugged in.
OUT_D3+
OUT_D3−
50 Ω
OUT_D2+
OUT_D2−
50 Ω
IN_D2+
IN_D2−
enable
input bias
enable
50 Ω
OUT_D1+
OUT_D1−
50 Ω
IN_D1+
IN_D1−
enable
HPD level shifter
HPD_SOURCE_N
(0 V to 1.1 V)
200 kΩ
DDC_EN (0 V to 3.3 V)
HPD_SINK
(0 V to 5 V)
DDC level shifter
SCL_SINK
SCL_SOURCE
SDA_SINK
SDA_SOURCE
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PTN3300A block diagram
MULTI-MODE DISPLAY SOURCE
OE_N
PTN3300/A/B
reconfigurable I/Os
OE_N
PCIe PHY ELECTRICAL
TX
FF
PCIe
output buffer
AC-coupled
differential pair
TMDS data
DATA LANE
TX
TMDS
coded
data
TX
FF
PCIe
output buffer
AC-coupled
differential pair
TMDS data
DATA LANE
TX
TMDS
coded
data
TX
FF
PCIe
output buffer
DATA LANE
TX
TMDS
clock
pattern
TX
FF
PCIe
output buffer
enable
IN_D4+
IN_D4-
50 Ω
AC-coupled
differential pair
clock
CLOCK LANE
TX
0 V to 3.3 V
3.3 V
enable
IN_D3-
IN_D2+
IN_D2OUT_D1+
OUT_D1IN_D1+
IN_D1-
HPD_SINK
IN_D2+
IN_D2−
SDA_SOURCE
SDA_SINK
enable
input bias
enable
OUT_D1+
OUT_D1−
50 Ω
5V
SCL_SINK
OUT_D2+
OUT_D2−
50 Ω
IN_D1+
IN_D1−
HPD_SOURCE
(0 V to 3.3 V)
enable
HPD level shifter
200 kΩ
5V
DDC I/O
(I2C-bus)
CONFIGURATION
enable
50 Ω
DDC_EN
(0 V to 3.3 V)
SCL_SOURCE
enable
input bias
50 Ω
0 V to 5 V
OUT_D3+
OUT_D3−
50 Ω
IN_D3+
IN_D3−
OUT_D2+
OUT_D2-
3.3 V
3.3 V
enable
input bias
IN_D3+
HPD_SOURCE
OUT_D4+
OUT_D4−
50 Ω
IN_D4+
IN_D4−
OUT_D3+
OUT_D3-
50 Ω
AC-coupled
differential pair
TMDS data
PTN3300B
input bias
OUT_D4+
OUT_D4-
DVI/HDMI CONNECTOR
TMDS
coded
data
DDC_EN (0 V to 3.3 V)
DDC level shifter
SCL_SINK
SCL_SOURCE
SDA_SINK
SDA_SOURCE
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Application example, (except in case of PTN3300A, HPD_SOURCE is inverted and level
shifted to 1.1 V)
PTN3300B block diagram
HPD_SINK
(0 V to 5 V)
IN_D1−
GND
37
IN_D2−
41
38
IN_D2+
42
VDD
GND
43
IN_D1+
IN_D3−
44
39
VDD
40
IN_D3+
45
IN_D4−
47
46
IN_D4+
48
terminal 1
index area
GND
1
36
GND
VDD
2
35
n.c.
n.c.
3
34
n.c.
n.c.
4
33
VDD
GND
5
REXT
6
HPD_SOURCE_N
7
SDA_SOURCE
32
DDC_EN
31
GND
30
HPD_SINK
8
29
SDA_SINK
SCL_SOURCE
9
28
SCL_SINK
n.c.
10
27
GND
VDD
11
26
12
25
23
24
21
VDD
GND
20
OUT_D2−
OUT_D1−
19
OUT_D2+
22
18
GND
OUT_D1+
17
OUT_D3−
15
VDD
16
14
OUT_D4−
OUT_D3+
13
OUT_D4+
GND
PTN3300AHF
VDD
OE_N
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Transparent top view
IN_D4+
IN_D4−
VDD
IN_D3+
IN_D3−
GND
IN_D2+
IN_D2−
VDD
IN_D1+
IN_D1−
GND
47
46
45
44
43
42
41
40
39
38
37
terminal 1
index area
48
PTN3300A pinout diagram (HWQFN48R and HWQFN48)
GND
VDD
2
35
n.c.
n.c.
3
34
n.c.
VDD
n.c.
4
33
GND
5
32
REXT
6
HPD_SOURCE
7
SDA_SOURCE
SCL_SOURCE
GND
30
HPD_SINK
8
29
SDA_SINK
9
28
SCL_SINK
n.c.
10
27
GND
VDD
11
26
12
25
VDD
24
GND
21
VDD
23
20
OUT_D2−
OUT_D1−
19
22
18
GND
OUT_D2+
OUT_D1+
17
OUT_D3−
15
VDD
16
14
OUT_D3+
13
OUT_D4−
50 Ω
IN_D4+
IN_D4−
enable
50 Ω
enable
50 Ω
enable
50 Ω
IN_D1+
IN_D1−
IN_D4+
IN_D4−
VDD
IN_D3+
IN_D3−
GND
IN_D2+
IN_D2−
VDD
IN_D1+
IN_D1−
GND
48
47
46
45
44
43
42
41
40
39
38
37
SCL_SOURCE
36
GND
VDD
2
35
n.c.
n.c.
3
34
n.c.
DDET
4
33
GND
5
32
VDD
DCC_EN
31
GND
30
HPD_SINK
8
29
SDA_SINK
SCL_SOURCE
9
28
SCL_SINK
n.c.
10
27
GND
VDD
11
26
12
25
VDD
24
VDD
GND
21
OUT_D2−
23
20
22
19
OUT_D2+
OUT_D1−
18
GND
OUT_D1+
17
OUT_D3−
15
VDD
OUT_D3+
14
OUT_D4−
16
13
OUT_D4+
GND
PTN3301HF
OUT_D1+
OUT_D1−
50 Ω
enable
HPD level shifter
200 kΩ
HPD_SINK
(0 V to 5 V)
DDC_EN (0 V to 3.3 V)
1
SDA_SOURCE
enable
input bias
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OUT_D2+
OUT_D2−
50 Ω
IN_D2+
IN_D2−
GND
7
enable
input bias
HPD_SOURCE
(0 V to 3.3 V)
6
OUT_D3+
OUT_D3−
50 Ω
IN_D3+
IN_D3−
OE_N
PTN3300B pinout diagram (HWQFN48R and HWQFN48)
REXT
enable
input bias
Transparent top view
HPD_SOURCE
OUT_D4+
OUT_D4−
50 Ω
DDC_EN
31
terminal 1
index area
PTN3301
enable
36
OUT_D4+
For more information visit www.nxp.com/displayport
input bias
1
GND
All the level shifters are available in a very thin, 48-pin HWQFNR (7 x 7
x 0.7 mm) or a 48-pin HWQFN (7 x 7 x 0.65 mm) package. All operate
from a 3.3-V power supply, and save power by using active pin control
and automatic control via hot-plug detection. When there is no monitor
actively connected to the device, the device automatically goes into idle
mode and consumes only a negligible amount of supply current.
OE_N
GND
PTN3300BHF
PTN3301
The PTN3301 is the same as the PTN3300B, but with additional features
for HDMI applications. It has actively buffered DDC lines that meet
HDMI’s more stringent specifications for capacitive loading, and, in
accordance with the DisplayPort interoperability guidelines, is capable of
responding to an I2C-based query to detect an HDMI dongle via the DDC
channel.
OE_N
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Transparent top view
PTN3301 pinout diagram (HWQFN48R and HWQFN48)
SDA_SOURCE
I2C-BUS
SLAVE
ROM
DDC BUFFER
AND
LEVEL SHIFTER
DDET
002aad345
PTN3301 block diagram
SCL_SINK
SDA_SINK
Selection guide
Feature
PTN3300
PTN3300A
PTN3300B
PTN3301
Data rate per lane
1.65 Gbps
2.25 Gbps
2.25 Gbps
2.25 Gbps
TMDS level shifters
•
•
•
•
DDC active buffer / level shifter
•
DDC passive level shifter
HPD level shifter
•
•
•
3.3-V, non-inverting
1.1-V, inverting
3.3-V, non-inverting
3.3-V, non-inverting
Automatic standby mode upon
HPD_SINK = LOW
•
•
•
•
Interchangeable TMDS data and clock lanes
•
•
•
•
Responds to I C-bus HDMI dongle detection
Optional
2
Applications
DVI motherboard,
dongle
DVI, HDMI
motherboard
DVI, HDMI
motherboard, dongle
DVI, HDMI
motherboard, dongle
Ordering information
Type number
Package type
Dimensions
Package feature
PTN3300HF
HWQFN48R
7 x 7 x 0.7 mm
Non-wraparound terminals
PTN3300AHF
HWQFN48R
7 x 7 x 0.7 mm
Non-wraparound terminals
PTN3300BHF
HWQFN48R
7 x 7 x 0.7 mm
Non-wraparound terminals
PTN3301HF
HWQFN48R
7 x 7 x 0.7 mm
Non-wraparound terminals
PTN3300AHF2
HWQFN48
7 x 7 x 0.65 mm
Wrap-around terminals
PTN3300BHF2
HWQFN48
7 x 7 x 0.65 mm
Wrap-around terminals
PTN3301HF2
HWQFN48
7 x 7 x 0.65 mm
Wrap-around terminals
www.nxp.com
© 2008 NXP B.V.
All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The
Date of release: March 2008
information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and
Document order number: 9397 750 16192
may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof
Printed in the USA
does not convey nor imply any license under patent or other industrial or intellectual property rights.
