Discontinuous Conduction Mode Analysis of Phase
Modulated Series Resonant Converter
Utsab Kundu, Parthasarathi Sensarma
Department of Electrical Engineering
IIT Kanpur, India
Email: utsab@iitk.ac.in, sensarma@iitk.ac.in
Abstract—This paper proposes an analytical approach
to derive voltage gain for phase modulated (PM) dc-dc
series resonant converter (SRC) operating in discontinuous conduction mode (DCM). Conventional fundamental
harmonic approximation (FHA) technique is extended
for non-ideal series resonant tank. The DCM analysis
is presented in a normalized form defining appropriate
base quantities. The converter is analyzed both in time
and frequency domain to derive a non-linear algebraic
function of diode rectifier extinction angle. The root of this
function is numerically determined using MATLAB and
used to predict the dc bus voltage. Experimental results
are presented to validate the analysis.
inductor current. Time domain analysis of DCMSRC for above-resonance operation is reported in
[5]. But this approach cannot be directly adopted to
determine voltage conversion ratio (Av ) for steady
state DCM operation while switching at resonant
frequency.
This paper presents DCM analysis of phase modulated SRC, switched at resonant frequency, using
time and frequency domain representations. Structured derivation of Av is presented, which requires
numerical solution of a single well-defined nonlinear algebraic equation.
I. I NTRODUCTION
II. FHA A NALYSIS OF N ON - IDEAL SRC
The complete circuit diagram of series resonant
boost dc-dc converter is shown in fig. 1a. The
full-bridge (FB) switch network is switched using
phase modulation approach [6]. It produces a high
frequency square/quasi-square wave to excite the
resonant tank. The tank comprises series resonating
elements, L and C, and terminated at the primary
of a step-up high-frequency transformer (HFT). Secondary of the HFT is connected to a diode bridge
rectifier (DBR), followed by a filter capacitor, Cf ,
to attenuate the switching harmonics.
The following assumptions are considered for
subsequent analysis.
1) Primary side MOSFETs and rectifier diodes
are ideal.
2) Dead-time between the gating signals of FB
MOSFETs are neglected.
3) The HFT does not contain any air-gap and
thus offers very high magnetizing inductance.
So, the parallel magnetizing branch is excluded from analysis of the tank network,
shown in fig. 1b.
Phase modulated (PM) dc-dc series resonant converters (SRCs) are traditionally operated in continuous conduction mode (CCM) [1], typically above
resonant frequency to achieve zero voltage switching (ZVS) of full-bridge (FB) switches. This approach compromises converter voltage gain significantly while ensuring ZVS in entire modulation
range. On the other hand, discontinuous conduction
mode (DCM) of SRC (DCMSRC) implies zero current switching (ZCS) of FB switches while retaining
the ZCS property of rectifier diodes [2]. Load and
modulation independent soft-switching, while operating at tank resonant frequency, makes DCMSRC
superior compared to its CCM counterpart. But
absence of an analytical formulation of the voltage
gain complicates the DCMSRC converter design
process, requiring repeated circuit simulations for
design convergence.
Conventional fundamental harmonic approximation (FHA) method [3] and extended describing
function (EDF) technique [4] are not applicable for
DCMSRC due to the discontinuous nature of series
(a)
(b)
Fig. 1. (a) Series resonant dc-dc converter, (b) Non-ideal tank network.
4) The only non-ideality, r, comprises winding
resistances of both inductor and transformer
and the effective series resistance (ESR) of
capacitor.
5) The leakage inductance of HFT is included in
the tank inductance, L.
III. DCM ANALYSIS OF SRC
All the parameters and state variables are referred
to the primary side of HFT and normalized using
the base quantities defined as follows.
For a given HFT turns ratio, 1 : N , voltage
transfer characteristic of the tank network is normalized with respect to its natural frequency, ω0 ,
and expressed as
where, Vgmin denotes minimum input voltage. Per
unit (p.u.) definitions of different parameters, state
variables, input and output voltages are listed as
follows.
r
RL
is
rpu =
, RLpu = 2 , ispu =
,
ZB
N ZB
IB
Vp (s)
s0 Q0
s
= 2
, s0 = ,
Vt (s)
s0 + s0 (Q0 + Qr ) + 1
ω0
√
Q0 = R
vCpu =
√
C
C
8RL
, Qr = r
, R = 2 2.
L
L
π N
√
VB = Vgmin , ZB =
(1)
L/C, IB = VB /ZB ,
(4)
vC
Vg
Vdc
, Vgpu =
, Vdcpu =
,
VB
VB
N VB
vppu = vp /VB , iRpu = (N iR )/IB .
(5)
To extract maximum gain, the switching frequency
(fs ) is decided to be
A. Time domain analysis
√
Considering the half-wave symmetry of tank varifs = ω0 /2π = 1/(2π LC).
(2) ables, the analysis is presented for a half cycle of
DCM switching period. This half-cycle is further
Using FHA analysis [3], the voltage gain expression divided into three sub-intervals. Equivalent circuits
for the entire power train is derived as
of each sub-interval are shown in fig. 2. Fig. 3
illustrates ideal waveforms of state variables for
< Vt > < Vp > < Vs > < Vdc >
< Vdc >
steady-state DCM operation of SRC, where θ = ω0 t
=
,
< Vg >
< Vg > < Vt > < Vp > < Vs >
and β denotes extinction angle of DBR.
√
2 2
α
R
π
1) Interval-I (0 ≤ θ ≤ α): This mode begins
=
sin( ) ·
·N · √ ,
when the diagonal pair M1 -M4 of FB switch netπ
2 R+r
2 2
work
is turned on. Due to discontinuous nature of
α R
= N sin( )
,
(3) the inductor current, is , secondary side DBR also
2 R+r
turns on at the beginning of this mode. Switching
where, ‘<>’ denotes respective rms quantities and function, S, of DBR is shown in fig. 3. During this
α is the modulation angle as shown in fig. 3.
interval, tank capacitor voltage, vC , rises from its
(a) Interval-I
(b) Interval-II
(c) Interval-III
Fig. 2. Equivalent circuits during three intervals of DCM.
initial value VC0 and is builds up from zero. This
ensures ZCS turn-on of FB MOSFETs M1 and M4
and secondary diodes D1 and D4 . This mode ends
when is reaches its peak, Is1 , and vC rises to VC1 .
The normalized state equations for this interval are
derived as
(dispu /dθ) + rpu ispu + vCpu = K,
(6)
(dvCpu /dθ) = ispu , K = Vgpu − Vdcpu .
(7)
The boundary conditions of Interval-I are normalized using respective base quantities and given by
ispu (0) = 0, vCpu (0) = VC0pu ,
(8)
ispu (α) = Is1pu , vCpu (α) = VC1pu ,
(9)
The state equations (6) and (7) are solved using
these mode boundaries as follows.
Is1pu = −A1 ex (p + E) sin γ
(10)
x
VC1pu = A1 e (cos γ + 2E sin γ) + K (11)
All parameters of (10) and (11) are listed in Appendix A.
2) Interval-II (α ≤ θ ≤ β): ZVS turn-on of M3
and hard turn-off of M4 define the beginning of
this mode. The source Vg remains disconnected thus
forcing is to fall. But vC further rises and reaches
VC2 at the end of this interval. This mode ends when
the DBR cease to conduct ensuring ZCS turn-off of
diodes D1 and D4 .
(dispu /dθ1 ) + rpu ispu + vCpu = −Vdcpu ,
Fig. 3. Ideal waveforms of SRC operating in DCM.
The state equations are solved using (9) and (14) as
follows.
0 = ey [Is1pu cos δ − F sin δ],
(15)
y
VC2pu = e [A2 cos δ + B2 sin δ] − Vdcpu . (16)
(12) All parameters of (15) and (16) are presented in
Appendix A.
(dvCpu /dθ1 ) = ispu , θ1 = (θ − α)
(13)
3) Interval-III (β ≤ θ ≤ π): During this mode,
Noting that is becomes zero at the end of this the DBR is in off state and thus is remains zero. The
capacitor holds the charge and vC remains constant
interval, the mode boundaries are presented as
at VC2 . ZCS turn-off of M1 and ZCS turn-on of
ispu (β) = 0, vCpu (β) = VC2pu .
(14) M2 defines the end of this interval. Considering the
steady state of capacitor voltage, vC , the following B. Frequency domain analysis
expression is derived.
Frequency domain analysis of SRC is performed
using multi-order decomposition technique [7].
VC2pu = −VC0pu .
(17)
Large-signal model of the converter is considered as
These simultaneous algebraic mode equations are a superposition of n-subsystems. Each of these opersimplified to derive an expression for Vdcpu by elimi- ates at different steady-state frequencies, as shown
nating intermediate variables as follows. Noting that in fig. 4a. Due to the non-linear nature of DBR,
ey ̸= 0, the expression for Is1pu is derived from (15) n-th order harmonic of is generates the following
components of rectified current, iR .
as
Is1pu = A2 J, J =
2
2p2 + (rpu
/2)
.
2p cot δ − rpu
(n−m)
(18)
(m)
= iRpu
i(n)
spu × S
(n+m)
+ iRpu ,
(23)
where, m is the harmonic order of switching function, S. It is obvious that n = m constructs the
(0)
dc component of iR , IR and n ̸= m results in
higher order switching harmonics. Since the conVC1pu = M (K − VC0pu ) − Vdcpu ,
verter operates at resonant frequency, the higher
M = [ex (p + E) sin γ]/J.
(19) order harmonics are adequately attenuated. With this
simplified, yet realistic, assumption a reduced order
Rearranging (11) and (19),
model is realized using n = m = 1 and depicted in
fig. 4b.
VC0pu = [1 − (1/(M + U ))]Vgpu − Vdcpu ,
The fundamental components of tank input voltx
U = e [cos γ + 2E sin γ].
(20) age, vt and transformer primary voltage, vp is normalized using base voltage, VB and expressed as
From (16) and (17), another expression for VC0pu is follows.
derived as
2Vgpu
(1)
[sin ϕ cos θ + (1 − cos ϕ) sin θ], (24)
vtpu =
π
VC0pu = [GVgpu − (G + 1)Vdcpu ]/(G − 1),
(1)
G = M Dey ,
vppu
= (2/π)[Ap cos θ + Bp sin θ],
(25)
D = cos δ + [(J/p) + (rpu /2p)] sin δ. (21)
Ap = (Vdcpu + VC0pu ) sin β,
(26)
Equating (20) and (21), the converter voltage gain,
Bp = Vdcpu (1 − cos β) − VC0pu (1 + cos β). (27)
Avt , is expressed as a function of α, RLpu and β
and given by
Assuming tuned operation of SRC, the p.u. fundaEquating (10) and (18), the expression for VC1pu is
simplified as
[
Vdcpu
1
G−1
Avt =
=
1+
Vgpu
2
M +U
(a)
]
mental component of is is derived as
(22)
(1)
(1)
i(1)
spu = (vtpu − vppu )/rpu .
(b)
Fig. 4. (a) Large-signal and (b) Reduced order model of SRC.
(28)
The fundamental component of S is given by
For a given set of (RLpu , α), the root of f (β) is
numerically determined. Subsequently, Av is calcuS (1) = (2/π)[sin β cos θ + (1 − cos β) sin θ]. (29) lated from either (22) or (33).
(0)
Using (23), (28) and (29), IRpu is derived as
IV. R ESULTS AND D ISCUSSIONS
2
(0)
IRpu =
[Vgpu λ − 2Vdcpu (1 − cos β)], (30)
rpu π 2
An experimental prototype of series resonant dcdc boost converter is fabricated and shown in fig. 5aλ = cos(α − β) − cos α − cos β + 1.
(31)
5b. It comprises the FB switch network along with
Assuming the double frequency switching har- the gate drivers, series resonant tank network, high
(2)
monic, iRpu is completely bypassed through Cf , the frequency transformer, the diode bridge rectifier and
output filter capacitor. Analog phase shift controller
normalized dc bus voltage, Vdcpu is expressed as
is used to switch the FB MOSFETs [6]. All the
(0)
Vdcpu = IRpu RLpu .
(32) parameters of experimental hardware and operating
conditions are listed in Table I. Considering these
Rearranging (32), the voltage gain expression (Avf )
data, β is numerically determined using (34) in
from frequency domain analysis is derived.
MATLAB. The dc bus voltage, Vdc is calculated
2λRLpu
Vdcpu
from (3) and (33) for CCM and DCM operations,
Avf =
= 2
. (33)
respectively and tabulated in Table II.
Vgpu
π rpu + 4RLpu (1 − cos β)
CCM operation of SRC is depicted in fig. 5c-5d,
Using (22) and (33), a non-linear algebraic function
where
continuous nature of secondary side current,
of β is defined as follows.
isec , is evident. Peak value of tank capacitor voltage,
f (β) = Avt − Avf .
(34) vC , is greater than the transformer primary voltage,
TABLE I
S YSTEM SPECIFICATIONS .
C
165 nF
r
100 mΩ
Lm
700 µH
(a)
fs
200 kHz
N
20
Cf
1 µF
Vgmin
10 V
(b)
Vg
20 V
α
32◦
(c)
130
105
analytical
experimental
analytical
experimental
Vdc (V)
110
100
1
(f)
RL (DCM)
6.4 kΩ
(d)
120
(e)
RL (CCM)
1.4 kΩ
100
β (deg.)
L
3.84 µH
95
2
3
4
5
RL (kΩ)
(g)
6
7
90
4
5 R (kΩ) 6
L
7
(h)
Fig. 5. Experimental prototype: (a) Top view, (b) Bottom view. Output dc bus voltage and electrical variables of tank network: (c)-(d)
CCM operation, (e)-(f) DCM operation. Analytical and experimental plots of (g) Vdc and (h) β at different loads. Scale: vt (20 V/div), Vdc
(50 V/div), isec - CCM (200 mA/div), DCM (100 mA/div), is (2 A/div), vC (5 V/div), vp (5 V/div). X-axis: (Time - 1 µs/div).
vp . This ensures the rectifier diodes remain in onstate for the entire switching cycle which confirms
CCM operation. The spikes in vt indicates that
the leading leg of FB network (M1 -M2 ) does not
experience soft turn-on and thus increases voltage
stress on switches.
But DCM operation (figs. 5e & 5f) ensures ZCS
turn-on of leading leg MOSFETs which reduces
voltage stress. When the DBR turns-off, isec does
not become zero in practice due to the presence of
body capacitance across rectifier diodes. The series
LC branch resonates with diode capacitances and
oscillations are experimentally observed not only in
is and isec , but in vc also. Moreover, finite magnetizing inductance (Lm ) of HFT acts as a resonating
element during DCM operation. This causes slow
transition at the edges of vp during off-state of
DBR. Obviously, reflection of capacitor voltage in
transformer primary does not appear, as shown in
fig. 3. However, the rectifier extinction angle, β,
is measured as shown in fig. 5f and presented in
Table II. Variation of Vdc and β with varying load
conditions are shown in fig. 5g and 5h, respectively.
The following error quantities are defined,
eV dc = | Vdc (anl) − Vdc (exp) | /Vdc (anl),(35)
eβ = | β(anl) − β(exp) | /β(anl),
(36)
where, ‘(anl)’ and ‘(exp)’ denotes analytical and experimental values, respectively. These errors are expressed in percentage and shown in fig. 6 at different
loads. Close agreements of experimentally obtained
Vdc and β with analytical predictions indicate that
TABLE II
A NALYTICAL AND EXPERIMENTAL RESULTS .
Results
Analytical
Experimental
β
97◦
92◦
Vdc (DCM)
122.5 V
124 V
Vdc (CCM)
106.5 V
106 V
4
eVdc
Error (%)
3
eβ
2
1
0
1
2
3
RL4(kΩ) 5
6
7
Fig. 6. Plots of eV dc and eβ at different loads.
the effects of finite Lm and body capacitances are
negligible.
V. C ONCLUSION
Time and frequency domain analysis for phase
modulated series resonant dc-dc converter operating
in DCM is presented. Advantages of operating SRC
in DCM is discussed. Limitations of conventional
approaches are noted for DCM analysis. The analysis is presented in a normalized form considering
ESR in resonant tank. Voltage gain expressions are
derived both in time and frequency domain. The rectifier extinction angle is determined by numerically
solving a non-linear algebraic equation, which is
analytically derived. Analytical prediction for output
dc bus voltage is experimentally validated. This
normalized analytical approach provides a definite
design guideline for phase modulated SRC operating in DCM.
A PPENDIX A
PARAMETERS OF MODE EQUATIONS
2
p = 1 − (rpu
/4), A1 = VC0pu − K,
E = rpu /4p, x = −(rpu α)/2, γ = pα
F = (pA2 + (B2 rpu /2)), A2 = VC1pu + Vdcpu ,
B2 = (1/p)[Is1pu + (rpu A2 /2)],
y = rpu (α − β)/2, δ = p(β − α)
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