Copyright © 2009 Year IEEE. Reprinted from IEEE ELECTRON DEVICE LETTER. Such permission of the IEEE does not in any way imply IEEE endorsement of any of Institute of Microelectronics’ products or services. Internal of personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to [email protected] 754 IEEE ELECTRON DEVICE LETTERS, VOL. 30, NO. 7, JULY 2009 Demonstration of Tunneling FETs Based on Highly Scalable Vertical Silicon Nanowires Z. X. Chen, H. Y. Yu, N. Singh, N. S. Shen, R. D. Sayanthan, G. Q. Lo, and D.-L. Kwong Abstract—This letter demonstrates a vertical silicon-nanowire (SiNW)-based tunneling field-effect transistor (TFET) using CMOS-compatible technology. With a Si p+ −i−n+ tunneling junction, the TFET with a gate length of ∼200 nm exhibits good subthreshold swing of ∼70 mV/dec, superior drain-inducedbarrier-lowering of ∼17 mV/V, and excellent Ion −Ioﬀ ratio of ∼107 with a low Ioﬀ (∼7 pA/μm). The obtained 53 μA/μm Ion can be further enhanced with heterostructures at the tunneling interface. The vertical SiNW-based TFET is proposed to be an excellent candidate for ultralow power and high-density applications. Index Terms—Gate-all-around (GAA), top-down, tunneling field-effect transistor (TFET), vertical silicon nanowire (SiNW). I. I NTRODUCTION T HE TUNNELING field-effect transistor (TFET) has emerged as a promising device candidate for ultralow power applications –, as it can offer a low leakage current (Ioﬀ ), weak temperature dependence, and, more importantly, a subthreshold swing (SS) not limited to kT /q. On the other hand, silicon nanowires (SiNWs) with a gate-all-around (GAA) structure provide volume inversion of the thin silicon body and excellent gate electrostatic control, resulting in immunity to short-channel effects and high transconductance . In addition, vertical GAA SiNW MOSFETs, where the SiNW was fabricated by either chemical synthesis  or using fully CMOS-compatible technology , have been demonstrated. In this letter, by marrying these two technologies, a highly scalable vertical SiNW TFET is fabricated for low-power and high-device-density applications. The vertical SiNW platform is ideal for TFET fabrication, as source and drain implants can be independently controlled without lithography. It is interesting to note that the carbon-nanotube TFET with GAA has also been reported mainly by simulation to provide high Ion and low SS , . In this letter, with Si p+ −i−n+ tunneling junction, the TFET with a gate length of ∼200 nm exhibits a good SS of ∼70 mV/dec, superior drain-induced barrierlowering (DIBL) of ∼17 mV/V, and excellent Ion −Ioﬀ ratio Manuscript received February 3, 2009; revised March 23, 2009. First published May 27, 2009; current version published June 26, 2009. The review of this letter was arranged by Editor B.-G. Park. Z. X. Chen and H. Y. Yu are with the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798, and also with the Institute of Microelectronics, A∗ STAR, Singapore 117685 (e-mail: [email protected]). N. Singh, N. S. Shen, R. D. Sayanthan, G. Q. Lo, and D.-L. Kwong are with the Institute of Microelectronics, A*STAR, Singapore 117685 (e-mail: [email protected]). Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2009.2021079 Fig. 1. Vertical SiNW TFET process flow. (a) Nitride hard-mask definition on p-substrate. (b) Nanowire etch using deep RIE. (c) Vertical implant to define n+ region. (d) HDP oxide nonconformal deposition and (e) DHF etch-back. (f) Gate oxide growth, poly-Si gate deposition, and patterning. (g) HDP oxide deposition and DHF etch-back. (h) Isotropic etch of poly-Si tip. (i) Nanowiretip implantation. (j) Aluminum contact formation. Fig. 2. TEM image of a vertical SiNW TFET with large diameter (∼750 nm) showing a gate length of 200 nm and a bottom HDP oxide thickness of 80 nm. The inset shows a SEM image of a vertical SiNW TFET after nanowire etching (diameter of ∼70 nm). of ∼107 with a low Ioﬀ (∼ 7 pA/μm). Given the smaller band gap of Ge, the Ion of 53 μA/μm can be further enhanced with heterostructures (e.g., SiGe) at the tunneling interface, as shown in simulation – and experimental  data. II. D EVICE F ABRICATION The fabrication process is schematically shown in Fig. 1. A nitride hard mask was first patterned on 8-in bulk Si wafers 0741-3106/$25.00 © 2009 IEEE Authorized licensed use limited to: ASTAR. Downloaded on July 9, 2009 at 02:01 from IEEE Xplore. Restrictions apply. CHEN et al.: DEMONSTRATION OF TUNNELING FETs 755 Fig. 3. (a) Device characteristics obtained from MEDICI simulations with varying diffusion characteristic length, Y.CHAR, of the p+ doping profile at the p+ −i junction. (b) Id –Vg and (c) Id –Vn+ characteristics of a vertical SiNW TFET with diameter of 70 nm, gate length of 200 nm, and gate oxide thickness of 4.5 nm. (d) n-TFET transfer characteristics with Vn+ = 0 and Vp+ < 0, showing a Vt shift with Vp+ . (p-type, ∼1015 cm−3 ) by nanodots defined lithographically using a 248-nm KrF scanner. This was followed by SiN etch [Fig. 1(a)] and 400-nm Si etch using deep RIE [Fig. 1(b)]. Thermal oxidation at 1000 ◦ C and DHF etch-back was done to smooth the wire surface and to reduce the nanowire diameter. Vertical nanowires with diameters of 30–800 nm were obtained. A vertical As implant and activation was done to dope the substrate and the bottom 80 nm of the nanowire n+ [Fig. 1(c)]. Nonconformal high-density plasma (HDP) oxide deposition [Fig. 1(d)] followed by DHF etch-back [Fig. 1(e)] was performed to cover only the bottom 80 nm of the wire (up to the n+ −p junction) before a 4.5-nm gate oxide was grown and poly-Si was deposited, implanted with BF2 (∼1019 cm−3 ), and patterned to form a gate extension pad [Fig. 1(f)]. HDP oxide deposition and DHF etch-back was once again used to expose only the top of the wire covered with poly-Si [Fig. 1(g)]. The oxide thickness would determine the resulting gate length as the exposed poly-Si was then isotropically etched using RIE to expose the nanowire tip [Fig. 1(h)]. A BF2 implant at a tilt of 45◦ was done from four orthogonal directions to form the p+ region [Fig. 1(i)]. To prevent counterdoping of the poly-Si gate, the same dopant type is used for the gate and top region. Finally, a layer of HDP oxide is added before contact and metal formation using aluminum [Fig. 1(j)]. The TEM image of the fabricated device shown in Fig. 2 was taken on a wider nanowire (diameter of ∼750 nm) for ease of sample preparation, showing the well-defined gate length of 200 nm. The inset of Fig. 2 shows a vertical SiNW with diameter of ∼70 nm. III. R ESULTS AND D ISCUSSION TFETs are essentially gated p+ −i−n+ diodes working under reverse bias and can operate as n- or p-TFETs. By controlling the i region with a gate, a tunneling barrier can be created either at the p+ −i (n-TFET, Vg > 0) or n+ −i (p-TFET, Vg < 0) junctions where carriers are able to tunnel through . The reverse-biased p–i–n diode gives the TFET a low OFF-state diffusion current. The TFET fabricated in this letter was found to have poor p-TFET characteristics, largely due to the more graded junction at the bottom tunneling (n+ −i) interface, compared to the top interface (p+ −i), which is caused by the larger thermal budget applied after the vertical implant. This results in a much wider depletion region at the tunneling junction. MEDICI simulations of the vertical SiNW TFET were performed to study the effects of junction abruptness on device performance. The characteristic length of the doping profile at the p+ −i junction, modeled as a Gaussian function, is varied. In MEDICI, the characteristic length parameter, or Y.CHAR, is defined as the length where the dopant concentration decreases by 1/e. Based on the MEDICI simulations [Fig. 3(a)], the device performs poorer, with high Vt , SS, and low Ion , as the doping profile of the tunneling junction is more graded, i.e., Y.CHAR is larger. The results agree with that of . Therefore, the focus in this letter will be on the n-TFET performance. Shown in Fig. 3(b) and (c) are the n-TFET Id –Vg and Id –Vn+ curves, respectively. These characteristics were obtained from a vertical SiNW TFET with diameter of ∼70 nm, gate oxide thickness of 4.5 nm, and gate length of 200 nm. Excellent Ion −Ioﬀ ratio at Vn+ = 1.2 V is observed (∼107 ), with an Ioﬀ (at Vg = 0 V) of ∼ 7 pA/μm and Ion (at Vg = 1.2 V) of ∼53 μA/μm (normalized with the wire circumference). The resulting high Ion and low DIBL (∼17 mV/V) for this Si TFET is a result of the excellent gate control of the GAA nanowire structure. From simulation – and experimental  data, it is believed that having an Si–SiGe interface at the tunneling Authorized licensed use limited to: ASTAR. Downloaded on July 9, 2009 at 02:01 from IEEE Xplore. Restrictions apply. 756 IEEE ELECTRON DEVICE LETTERS, VOL. 30, NO. 7, JULY 2009 R EFERENCES Fig. 4. Band diagrams of a TFET under (a) zero bias, and n-TFET operation with (b) |Vp+ | = 1 V and (c) |Vp+ | = 1.5 V, illustrating the Vt shift with |Vp+ |. Not to scale. junction can further improve the drive current. The obtained SS of 70 mV/dec is beyond the limit of kT /q (≈60 mV/dec), which is likely due to the tunneling junction (p+ −i) not being perfectly abrupt. The n-TFET Id –Vg characteristics with Vn+ = 0 and Vp+ < 0, as shown in Fig. 3(d), shows a Vt shift with Vp+ . This can be explained using Fig. 4. Since the p+ −i−n+ diode is always kept reverse-biased, i.e., Vn+ > Vp+ , an n-TFET (Vg > 0) can operate at Vn+ > 0 or Vp+ < 0, with the other terminal grounded. An n-TFET operating with a |Vp+ | of 1 V, for example, requires a Vg of 1 V to form a tunneling barrier with a certain barrier width [Fig. 4(b)]. If |Vp+ | is increased to 1.5 V, a Vg of only 0.5 V is required to form a tunneling barrier with the same barrier width [Fig. 4(c)], effectively reducing Vt by 0.5 V. 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