Manufacturability and
Reliability of 0.3mm Pitch Chip
Scale Packages and QFNs
Greg Caswell
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December 6, 2011
Focus on Quality/Reliability/Durability of Electronics
Tech
Insertion
Warranty
Test
All levels
of the supply chain
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Design
Supply
Chain
Reliability and Next Generation Technologies
o
One of the most common drivers for failure is
inappropriate adoption of new technologies
o
o
Obtaining relevant information
can be difficult
o
o
o
Information is often segmented
Focus on opportunity, not risks
Can be especially true for
component packaging
o
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The path from consumer (high volume, short lifetime) to high rel is
not always clear
Fine pitch CSP (Chip Scale Packages)
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Solder Wearout
o
o
Design change: More silicon, less plastic
Increases mismatch in coefficient of thermal expansion
(CTE)
BOARD LEVEL ASSEMBLY AND RELIABILITY
CONSIDERATIONS FOR LNCSP TYPE
PACKAGES, Ahmer Syed and WonJoon Kang,
Amkor Technology.
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Solder Wearout (cont.)
o
Hotter devices
o
Increases change in temperature (∆T)
tf = ∆Tn
n = 2 (SnPb)
n = 2.3 (SnNiCu)
n = 2.7 (SnAgCu)
Characteristic Life (Cycles to Failure)
10000
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
0
50
100
150
200
o
Change in Temperature ( C)
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.3 mm CSP: Why Not?
o
.3 mm CSP is a ‘next generation’ technology for nonconsumer electronic OEMs due to concerns with
o
o
o
o
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Manufacturability
Compatibility with other OEM processes
Reliability
Acceptance of this package, especially in long-life, severe
environment, high-reliability applications, is currently
limited as a result
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Chip Scale Packages
Lead Frame Chip Scale Package
Wafer Level CSP
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Design and Fab Thoughts?
o
Board Fabricators
o
A first step in adapting to .3 mm pitch(12 mil)
o 2 mil traces and spaces
o Why? Bond pad will be .15mm
o
o
o
2 mil trace is only size that will fit between
Most likely use via in pad
Copper Thickness
o
Board fabricators introducing a reduction in copper foil thickness
to work with these smaller components
o Going down to .25 ounce copper – good for lateral etching,
trace width control, uniform trace width.
ISSUE IS REDUCED RELIABILITY DUE TO POTENTIAL FOR TRACE
CRACKING
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Fine Pitch CSP Manufacturability: Bond Pads
o
Non Solder Mask Defined Pads Preferred (NSMD)
o
o
o
Copper etch process has tighter process control than solder mask process
Makes for more consistent, strong solder joints since solder bonds to both tops and sides of pads
Use solder mask defined pads (SMD) with care
o
o
Can be used to avoid bridging between pads, especially between thermal and signal pads.
Pads can significantly grow in size based on PCB manufacturer capabilities
NSMD
Images courtesy of Screaming Circuits
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Solder Paste
o
o
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Continued reduction in apertures and bond pad dimensions are
driving toward Types 5 or 6 shown in the chart to facilitate
.3mm pitch components
While changes in the solder paste is expected – this move
toward “nanosolder” - the increasing ratio of surface area to
volume in these small particle systems may start to influence
coalescence behavior and storage times as well.
Stencils
o
The actual minimum area ratio tends to change for different
solder paste types.
o
o
o
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For standard Type 3, the number tends to be 0.66, while pastes
with even smaller powder have minimum area ratios closer to 0.5.
Regardless, for a 0.15 mm (6 mil) bond pad, maintaining either of
these ratios would require stencil thicknesses of less than 4 mil.
These stencil requirements can be problematic for larger or
non-fine pitch components, which can potentially experience
solder starvation or solder bridging or solder balls (if the
stencil aperture is widened to introduce more paste on pad).
All of these challenges are, of course, before attempting to
select the type of stencil technology (electroformed or laser cut)
or the process parameters (pressure, speed, etc.).
Manufacturability: Stencil Design
Datasheet says solder paste coverage should be 40-80%
Drawing supplied in same datasheet is for 26% coverage
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Reliability
o
o
o
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As usual, reliability is often the last issue to be considered.
While minimum modeling or testing has been performed,
the relatively small volume of solder and the nonuniformity of the interconnect geometry (0.15 mm bond
pads on board and 0.075 mm bond pads on package)
could create unique scenarios in regards to solder joint
response to the application of stresses.
This is in addition to the increasing introduction of mixed
mode (shear and tensile stresses) that are greatly
accelerating creep and fatigue damage accumulation.
.3mm CSP Reliability Conclusions
o
While the move to 0.3 mm pitch CSPs will be challenging, there
is significant opportunity for leveraging the experiences of
other portions of the supply chain.
o
o
o
Examples include wafer-level bumping, which has been stencil
printing 0.15mm pitch solder bumps for some time period,
BGA substrates, which has been using 2 mil width and spacing on
advanced packages, and
01005s, which have bond pads only 7 mil wide.
Success will be ensured through adopting the information gained
from these other processes, being aware of the potential gaps in this
knowledge, and implementing industry best practices and physics of
failure to understand margins and interconnect robustness.
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LFCSP Manufacturability: Bond Pads
o
Can lose solder volume and standoff height through vias in thermal pads
o
May need to tent, plug, or cap vias to keep sufficient paste volume
o
Reduced standoff height reduces cleanability and pathways for flux outgassing
o
Increased potential for contamination related failures
o
Tenting and plugging vias is often not well controlled and can lead to placement
and chemical entrapment issues
o
Exercise care with devices placed on opposing side of LFCSP
o
Can create placement issues if solder “bumps” are created in vias
o
Can create solder short conditions on the opposing device
o
Capping is a more robust, more expensive process that eliminates these concerns
Thermal
vias capped
with solder
mask
Images courtesy of Screaming Circuits
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Bond Pads
o
Extend bond pad 0.2 – 0.3 mm
beyond package footprint
o
o
o
Need X-ray for best results
o
o
o
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May or may not solder to cut edge
Allows for better visual inspection
Allows for verification of bridging,
adequate solder coverage and
void percentage
Cannot detect head in pillow or
fractures
Note: Lack of good criteria
for acceptable voiding of the thermal
pad. Depends upon thermal needs.
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Manufacturability: Reflow & Moisture
o
LFCSP solder joints are more susceptible to dimensional changes
o
Case Study: Military supplier experienced solder separation under LFCSP
o
LFCSP supplier admitted that the package was more susceptible to moisture
absorption that initially expected
o
o
o
Was not popcorning
o
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Resulted in transient swelling during reflow soldering
Induced vertical lift, causing solder separation
No evidence of cracking or delamination in component package
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Corrective Actions: Manufacturing
•
•
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Verify good MSL (moisture sensitivity level) handling and
procedure procedures
Reflow Profile: Specify and confirm
o
• Room temperature to preheat: maximum 2-3 C/sec
o
• Preheat to at least 150 C
o
• Preheat to maximum temperature: maximum 4-5 C/sec
o
• Cooling: maximum 2-3 C/sec
• In conflict with profile from J-STD-020C which allows
up to 6oC/sec
• Make sure assembly is less than 60oC before any
cleaning processes
Manufacturability: LFCSP Joint Inspection
Goal is 2-3 mils of post-reflow
solder thickness
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Manufacturability: LFCSP Joint Inspection
Convex or absence of fillet highly likely
•Etching of leadframe can prevent
pad from reaching edge of package
•Edge of bond pad is not plated for
solderability
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Manufacturability: Board Flexure
o
Area array devices are known to have board flexure
limitations
o
o
o
.3mm CSPs and LFCSPs have an even lower level of compliance
o
o
o
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In circuit testing (ICT), board depanelization, connector insertion,
manual assembly operations, shock and vibration, etc. are
common causes.
For SAC attachment, maximum microstrain can be as low as 500
υε
o Use IPC-JEDEC 9701 and 9704 specifications
Limited quantifiable knowledge in this area
Must be conservative during board build
IPC is working on a specification similar to BGAs
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Pad Cratering
Intel (2006)
o
Drivers
o
o
o
o
o
Difficult to detect using
standard procedures
o
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Finer pitch components
More brittle laminates
Stiffer solders (SAC vs. SnPb)
Presence of a large heat sink
X-ray, dye-n-pry, ball shear, and
ball pull
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Solutions to Pad Cratering
o
Board Redesign
o
o
Limitations on board flexure
o
o
o
Intel-led industry effort
Attempting to characterize laminate material using high-speed
ball pull and shear testing, Results inconclusive to-date
Alternative approach
o
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SAC305 is relatively rigid, SAC105 and SNC are possible
alternatives
New acceptance criteria for laminate materials
o
o
750 to 500 microstrain, Component dependent
More compliant solder
o
o
Solder mask defined vs. non-solder mask defined
Require reporting of fracture toughness and elastic modulus
2323
Reliability: Thermal Cycling
o
o
o
o
Order of magnitude reduction in time to
failure from QFP
o
3X reduction from BGA
QFP: >10,000
Driven by die / package ratio
o
40% die; tf = 8K cycles (-40 / 125C)
o
75% die; tf = 800 cycles (-40 / 125C)
Driven by size and I/O#
o
44 I/O; tf = 1500 cycles (-40 / 125C)
o
56 I/O; tf = 1000 cycles (-40 / 125C)
BGA: 3,000 to 8,000
Very dependent upon solder bond with
thermal pad
LFCSP: 1,000 to 3,000
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Reliability: Bend Cycling
o
o
Low degree of compliance
and large footprint can
also result in issues during
cyclic flexure events
Example: IR tested a
5 x 6mm LFCSP to
JEDEC JESD22-B113
o
o
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Very low beta (~1)
Suggests brittle fracture, possible along the interface
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Electro-Chemical Migration: Details
o
Insidious failure mechanism
o
o
o
Due to the presence of contaminants
on the surface of the board
o
o
o
Strongest drivers are halides (chlorides and bromides)
Weak organic acids (WOAs) and polyglycols can also lead to drops in the
surface insulation resistance
Primarily controlled through controls on cleanliness
o
o
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Self-healing: leads to large number
of no-trouble-found (NTF)
Can occur at nominal voltages (5 V)
and room conditions (25C, 60%RH)
elapsed time
12 sec.
Minimal differentiation between existing Pb-free solders, SAC and SnCu,
and SnPb
Other Pb-free alloys may be more susceptible (e.g., SnZn)
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Reliability: Dendritic Growth / Electrochemical Migration
o
o
Large area, multi-I/O and low standoff can trap flux
under the LFCSP
Processes using no-clean flux should be requalified
o
o
Aqueous Cleaning processes will likely experience
dendritic growth without modifications like:
o
o
o
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Particular configuration could result in weak organic acid
concentrations above maximum (150 – 200 ug/in2)
Increase in water temperature
Additions of saponifiers or solvents
Changes to number and angle of impingement jets
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Cleanliness Controls: Ion Chromatography
Contamination tends to be controlled through industrial specifications (IPC6012, J-STD-001)
o
o
o
o
o
Primarily based on original military specification
10 µg/in2 of NaCl ‘equivalent’
Calculated to result in 2 megaohm surface insulation resistance (SIR)
Not necessarily best practice
Best practice is contamination controlled through ion chromatography (IC)
testing
o
o
IPC-TM-650, Method 2.3.28A
Pauls
General
Electric
NDCEE
DoD*
IPC*
ACI
Chloride (µ
µ g/in2)
2
3.5
4.5
6.1
6.1
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Bromide (µ
µ g/in2)
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10
15
7.8
7.8
15
*Based on R/O/I testing
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Thank you!
Any Questions?
Contact me:
gcaswell@dfrsolutions.com
www.dfrsolutions.com
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