Carnegie Mellon University
CARNEGIE INSTITUTE OF TECHNOLOGY
THESIS
SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS
FOR THE DEGREE OF MASTEROF SCIENCE
POWER SUPPLY NOISE REDUCTION USING
ACTIVE RESISTORS
GOK(~E KESKiN
ACCEPTED BY THE DEPARTMENTOF
ELECTRICAL AND COMPUTERENGINEERING
REVIEWED BY
DATE
DATE
Acknowledgements
I am thankful to mythesis advisor, Larry Pileggi, for providing megreat guidance during the course
of this project. His full support and encouragementhave madethis work possible. He has been a
constant inspiration for meduringthe difficult times of the project.
I wouldalso like to thank KenMaiand Patrick Yuefor their help during the fabrication of the test
chip and excellent advice on the problemsI encountered. I amparticularly grateful to Xin Li for his
extremelyvaluable contributions starting from the first day of this project. I have learnt a lot from
him, including identifying problemsand finding waysto solve them. Contributions of Marija Ilic and
Aleksandar Veselinovic during the early exploration stages of this project have also been very
valuable. I owe manythanks to Jaejin Park, KihwaChoi and Hasan Akyol, who have helped me in
various stages of the project.
I have to acknowledgethe great moral support of myfriends at Carnegie Mellon. UmutArslan, Hasan
Akyol, Rohan Batra, Ahmet Gtirkan l~epni, Volkan Ediz, Thiago Hersan, WessamHassanein,
Koushik Niyogi, Jonathan Proesel and Aleksandar Veselinovic have mademy stay enjoyable during
this time.
Most importantly, I owe great thanks to my family. Without them, I would not be here today. I am
grateful to mygrandmother, mother, father, sister and brother-in-law for being the meaningof my
life.
2
Table of contents
Abstract
.....................................................................................................................................
4
1. Introduction
..........................................................................................................................
5
2. Background
..........................................................................................................................
8
2.1Decoupling
Capacitance
.............................................................................................................
8
2.2Resistive
Damping
....................................................................................................................
11
2.3Analysis
......................................................................................................................................
12
3. ActiveResistorsfor NoiseReduction
................................................................................
16
3.1Concept
......................................................................................................................................
16
3.2Simulation
Setup
andResults
..................................................................................................
21
3.3Testing
.......................................................................................................................................
27
4. Conclusions
........................................................................................................................
30
5. References
..........................................................................................................................
31
Abstract
Withthe reduction of supply voltages in today’s integrated circuits, maintaining the powersupply voltage
integrity within the required range of operation has becomea critical design problem. Furthermore,if clock
gating techniques are used to reduce the overall powerconsumption,a large portion of the circuits can be
turned on or off simultaneously, thereby introducing substantial transient switchingnoise on the powergrid.
Thetraditional solution for this problemis to include both on- and off-chip decouplingcapacitors to reduce
transient peaks; however, there is a point of diminishing returns for adding more on-chip capacitance in
terms of area and leakage power in modern technologies. In this thesis, we propose the use of active
resistors
for damping the typically underdampedpower grid distribution
network to reduce both the
amplitudeand the duration of transient oscillations in the powerand groundrails. Initial simulation results
in 130nmCMOStechnology demonstrate more than a 40%reduction in oscillation
amplitude and a
significant reduction of the oscillation settling time over a conventional design with the same amountof
decoupling. A test chip has been built in the same technology and it is currently under test at Carnegie
Mellon.
4
1. Introduction
Continual scaling in integrated circuit technology has made it possible to achieve higher transistor
density
in a given die area. Even with the lowering of the power supply voltage for newer process nodes, the
maximumpower consumption of high-end microprocessors
has been projected
to continue to increase
for
the foreseeable future (Fig. 1) [1].
Power Consumption Projection for High Performance
Microprocessors, ITRS 2004 Update
220
200
180
180
16o
140
~40
12o
lOO
2005
2006
2007
2008
2009
Power
Currentj
Figure I. Power consumption trend in microprocessors [1].
Manyprocessors today include clock gating schemes that turn off unused portions of the chip to reduce
power consumption [2]. However, when the idle regions are switched back on as required under normal
operation,
the current demand increases
rapidly in a short period of time (at most a few nanoseconds).
Ultimately,
this current has to be supplied by the main board to the chip through the inductive bonding
connections
between the chip, package, and the board. Since the voltage drop across an inductor
is
proportional to the rate of change of current through it, the voltage on the chip level decreases below the
5
nominal value during switching. This type of noise is commonlycalled Ldi/dt noise, or simultaneous
switching noise. An analogous situation occurs whenlarge active blocks are turned off whenthey are not
needed. (Figure 2)
dV=L.dl/dt
Vdd
Current
Demand
I
Decap
Chip
_.L
Figure 2. Simplemodeldescribing L.di/dt noise.
There are two ways to decrease the voltage drop across the parasitic inductors: decreasing L or decreasing
di/dt through the L. The L can be decreased by using a large numberof Vda/Gndconnections, since the
effective inductance of two parallel connections is half that of a single one. In fact, in high performance
processors, it is not uncommon
to use two thirds of the available I/Os for power supply connections.
Advanced packaging techniques can further reduce the parasitic
inductance of the connections. For
example, flip-chip packaging replaces bondwires used in peripheral wire bonding with lower inductance
solder bumps.
Thetraditional approachto reducing di/dt is to place decouplingcapacitors on the chip, package, and board
levels (Figure 3). Decouplingcapacitors function as local charge reservoirs that supply (or absorb)
portion of the required (excessive) charge during switching so that di/dt through the parasitic inductors
reduced. On-chip decoupling is generally provided by MOSdevice capacitors
that might consume
significant die area [3]. However,there are diminishing returns for adding moredecoupling capacitance onchip, especially with the high gate leakage of the MOS
decoupling capacitors in advancedtechnologies due
6
to thinner gate oxides. Moreover, the resonance caused by the parallel LCtank formed by the parasitic
inductors and the decoupling capacitors result in an underdampedsystem and cause oscillations in the
powergrid that can last for a significant numberof clock cycles in a high performancemicroprocessor.
Package
Decaps
Chip
Package
S
.
Decaps
Board
Figure 3. Placing decouplingcapacitors on board, packageand chip level.
In this thesis, we investigate an alternative wayof reducing power supply noise by using on-chip active
devices together with decouplingcapacitors. By implementingactive resistors on the chip, weincrease the
power grid damping and, thereby, reduce the power supply noise. Although the resistive
damping has
previously been applied [6-8], the maincontribution of this thesis is to propose two novel active resistor
circuits that provide better noise reduction while consumingless power.
7
2. Background
2.1 Decoupling Capacitance
The traditional solution to reducing noise on the power supply is to use on-chip decoupling capacitors,
along with on-package and on-board capacitors. However,several resonances formed by these capacitors
and parasitic inductors can cause undesired, underdampedoscillations in the powersupply voltage across
the chip [4].
Figure 4 shows the frequency response of a typical chip power grid where impedance value is chosen
arbitrarily
for demonstration. At certain frequencies, the impedanceof the grid shows resonance peaks.
Thesepeaks cause oscillations in the transient response whenthe powergrid is excited with a step response,
like a clock gating signal. The frequency of those peaks depends on the value of decoupling capacitors
placed across the board/package/chipand the parasitic inductors through whichthe current is carried to the
chip.
5.0
4.0
l~ower Grid ImpedanceProfile
Ill
’
+
Package
~
Figure 4. Resonancesformedin the powerdistribution network.
The parasitic inductance of the board connections and the inductance of the package-boardconnections are
considerably higher than that of package-chip connection, and since larger decoupling capacitors can be
afforded on package and board levels, the resonances for those two cases are at a lower frequency.
Furthermore, the peaks are lower due to better noise suppression of those large capacitors. The resonance
due to the parasitic inductance of package-chipconnections and on-chip decouplingcapacitors are generally
at a higher frequency with a higher peak value, causing the primary noise problem in the distribution
network.
In Fig. 4, peak 3 denotes the resonance caused by the board connections and board decaps. Peak 2 denotes
the resonance caused by board-package connections and package decaps, Peak 1 denotes the resonance of
package-chip connections and on-chip decaps. In this work, mainly the noise due to peak 1 is investigated
since it dominatesthe other two in most cases. Note that it is possible to observe a muchhigher frequency
resonancedue to on-chip inductive connections and capacitors, but these are limited to local disturbances in
the power supply noise across the chip and can be alleviated by better placement of on-chip capacitors.
Since the frequencyof that resonanceis generally pretty far from the clock gating frequency(or, lbr a step
disturbance, the amplitudeof the Fourier transformof the step signal at that frequencyis sufficiently low),
the inducednoise is less. Since the duration of the noise is short as well, the effect on the chip operation is
less of a concern than that caused by the noise caused by peak 1. Fig. 5 shows the noise waveformin the
transient domainin response to a step disturbance, where high frequency noise due to on-chip decaps and
package-chip connections cause the mainresonant noise.
As power supply voltages scale downand noise margins becometighter in new generation process nodes,
even more on-chip decoupling will be required for high-performance circuits.
Unfortunately, there are
diminishing returns for adding more decoupling capacitors on the chip (Figure 6). Doubling the on-chip
decoupling capacitance, for example, does not reduce the power supply noise by half. One other important
concern is the case for advanced technologies with 65nmand below when one considers not only the
9
increase in area, but also the associated exponential
increase in the leakage power for MOScapacitors
(Figure 7).
Transient
Noise on On-chip Power Supply
Voltage
Figure 5. Transient Noise on the Power Supply Network due to Resonances.
Decoupling Capacitance Area vs. Relative
Power Supply Noise
120000
100000
--*-- 90nm
80000
~,-- 65nm
40000
20000
0
0
0.2
0.4
0.6
0.8
Relative PowerSupplyNoise(Overshoot+Undershoot)/Vdd
Figure 6. Capacitance area vs. relative
power supply noise projected by using ITRS Roadmap[l].
10
Relative
0.8
0.7
Power Supply Noise vs.
Leakage
~ 90nm
-~- 65rim
Gate
K
0.6
0.5
0.4
0.3
0.2
0.1
0
0.001
0.01
0.1
1
10
100
1000
Gate Leakage Power (mW)
Figure 7. Relative power supply noise vs. gate leakage of decaps projected by using ITRS Roadmap[1].
2.2 Resistive
The oscillations
Damping
in the power supply voltage across the chip are due to the underdampednature of the power
grid distribution
network. Underdamped systems inherently
produce oscillations
when excited
by step
responses. Clock gating can be considered as a step disturbance on the power grid since it causes a sudden
change in the current demand of the chip. Additional damping may be provided by introducing dissipative
elements, such as resistors,
into the system. As described by Kundert [5], resistors
various ways to the network. They can be placed in series/parallel
series/parallel
with decoupling capacitors.
Resistance placed parallel
can be introduced in
with inductive
bondwires, or in
to bondwires reduces the decoupling
of different regions, so it is not preferred.
In 2003, Ji described a passive resistor
the efficiency
in series with the decoupling capacitors,
but this approach reduces
of the capacitors at high frequencies [6]. In the ideal case, one would like to get a fiat,
11
resonant free, very low impedanceacross all the frequencies in the powerdistribution network. Althoughan
ideal capacitor would provide a short circuit at sufficiently
impedanceof the power grid significantly,
high frequencies- that would lower the
the added series resistance limits the decoupling effect by
imposing a lower bound on the high frequency impedance. This fact causes inadequate suppression of the
high frequencynoise on the powersupply due to the switching of individual gates rather than clock gating.
Gabaraproposed the use of active devices in series with the inductive bonding to introduce resistance;
howeverthis is not applicable in high performance circuits where the IR drop would be significant [7].
Today’s microprocessors can consume more than 100A of peak current,
and even 1 milli-ohm series
resistance would cause a 100mVdrop in the on-chip power supply. With the power supply voltage on the
order of IV, this significant drop must be avoided.
Larsson discussed adding a passive resistance in parallel with the decoupling capacitors, but deemedit
infeasible due to excessive DCpower dissipation [8]. Anyresistance that needs to be added between
and Gndrails
in this case is comparable to the total impedance of the power grid, and this would
approximately double the powerdissipation. In this work, adding an active resistor in parallel with the
decoupling capacitors is proposed, thereby eliminating excessive DCpowerdissipation while achieving the
desired damping in ACdomain.
2.3 Analysis
For a secondorder parallel RLCcircuit as shownin Figure 8, the characteristic equation is given as:
s2 + 2(wos + w02 = 0
(1)
The transfer function Z(s) betweencurrent input I and voltage output V is given as:
Z(s) =
s/C
S 2 ~1"
2(WoS+ o
where:
12
2
(2)
1
(3)
I _1-
Vou
Figure 8. Parallel RLCcircuit.
For an overdampedsystem, the dampingratio ~ has to be greater than 1, resulting in the condition for the
resistor as:
(4)
R<I~V~2
A second order parallel RLCcircuit is a very simplified view of the powergrid. Here, C denotes total onchip decouplingcapacitance, R denotes the total resistance betweenthe rails, and L denotes the parasitic
inductance of package-chip connections. Onthe package level, Vddis assumedto be constant and thus acts
as small signal ground. IR drop due to inductive connections is ignored, so is any parasitic resistive
componentin C. The step disturbance I models the turn on/off of a number of blocks simultaneously,
possibly through clock gating. Vo,, is the output waveformon the on-chip supply voltage due to the step
disturbance. Althoughthis system is overly simplified, it provides valuable intuition about the effect of
dampingin the powergrid.
An overdampedsystem does not produce any oscillations in its step response. Furthermore, overshoots are
reduced as the dampingratio is increased. Thus, if we can achieve a low enough parallel resistance,
oscillations can be eliminated completely.
13
To look into the effect of dampingin the transient domain,wecan calculate the time domainstep response
of the systemas:
Vou,(t)2
1~_~.
The maximum/minimum
values of the step response Vout(t) occur at points where d Vo=t(t)/dt =0. After a
little bit of algebra, wecan find that the overshoot,the point wherethe first zero crossing for d V,,ut (t)/dt,
occursat:
t0 = w0
If weinsert t=to in (5), wecan find the overshootof the systemas a function of the dampingratio, ~ It turns
out that overshoot decreases as (increases. Figure 9 showsa plot of overshoot with respect to (, normalized
to the value where(=/(critically
dampedsystem).
FromFigure 9 it is evident that to achieve zero overshoot, the dampingratio has to be increased to infinity;
meaningthat we cannot avoid overshoots completely with resistive damping.Furthermore, one can see that
after (-3, the effect of additional dampingstarts leveling off. The settling time for zero-overshootwill be
quite large as well. For (>1, there are no oscillations in the output as seen in Figure 10, whereall plotted
step responses are overdamped.On the other hand, the settling times are significantly higher for large
dampingratios.
Thus, one should determine the amountof damping according to the desired overshoot,
settling time and the power budget. This will imposea lower bound on R, thus an upper bound on damping
ratio.
14
Relative Overshootvs. Damping
Ratio
2.5
2
1.5
1
0.5
O
"1
10
10e
2
101
10
Damping
Ratio
Figure9. Overshoot
vs. damping
ratio for a secondorderparallel RLC
circuit.
StepResponse
for Second
OrderIRLCCircuit
14......... . ................. . ......... : ..................................... . ..................
12
10
8
6
4
2
0
-2
0
~
0.1
J
0.2
0.3
0.4
0.5
Time
0,6
0.7
0.8
0.9
~
x 10
Figure10. Stepresponseof the parallelRLC
circuit for differentdamping
ratios.
15
3. Active Resistors for Noise Reduction
3.1 Concept
Havinganalyzed the second order parallel RLCcircuit, one can see that if minimum
overshoot is desired,
the dampingratio has to be as high as possible. This can be achieved by lowering R; however, since R is
between the Vdaand Gndrails,
low R will cause excessive power dissipation. If the passive resistor is
replaced with an equivalent active resistor that will act as a dissipative device at the frequency of
oscillations, one can achieve significant dampingwithout excessive powerdissipation.
Vdd (noisy}
0
/.,.--Rin
~
Vbias2
~3 I
~t l/(K.gm}
M1
M2~~~
Gain Stage
(Gain=KI
Figure 11. Active resistor implementation.
A simple active resistor implementationis given in Figure 11. In this circuit, M1acts as the small signal
resistor, whereastransistors M2-M4
form a gain stage that amplifies the noise in the on chip supply voltage.
Thesmall-signal input impedanceof this circuit, as looking into the drain of M1,can be found as:
Rin --
1
(7)
K.gm~
whereK is the gain of the first stage, and gin1 is the small signal transconductanceof M1.The small signal
gain from the node Vddto the gate of M1can be computedas:
K- gm,~
(18)
gm2
16
wheregin2 and g"4 are the small signal transconductancesof transistors M2and M4.M3is added to increase
gm4while keepingg,,2 at a lowervalue, to increase the gain.
M1must have a large enoughgm tO achieve smaller resistance and better damping.Thus, there is a trade-off
between howmuchdampingwe can provide and the allowable power consumptionof the active resistor.
If
the active resistor is to respond to both positive and negative peaks in Vad, M1has to be biased at a
sufficiently high voltage to be able to remain ONwhena negative peak occurs. However,it is possible to
decrease the static powerconsumptionof the resistor circuit in certain cases wherea clock gating signal can
be anticipated.
Whenthere is not any disturbance, the bias voltage Vbiasl can be tied to Vod via a
transmission gate, essentially placing the resistor block in sleep mode. Before gating signal is actually
applied, the resistor can be turned on to provide damping.After the powersupply voltage stabilizes, the active
resistor can be turned off again. Thus, the settling time of oscillations impacts the ONtime of the active
resistor.
For a given design, the amountof active resistance R to provide critical
dampingcan be found from Eq. 4,
where L is the total amountof parasitic inductance of the bondwires, and C is the on-chip decoupling
capacitance; this sets an upper boundR for a critically dampedsystem. Havingdetermined the target R, and
combiningequations 7 and 8, wehave the target impedanceas:
R - g,.2
g,,~ "g,.4
(9)
One of the most important considerations for the active resistor block is the power consumption,and M1is
the power bottleneck in the design due to its large size comparedto M2-M4.Given a DCpower consumption
budget P and assumingthat most of the consumptionis due to MI, wecan find:
Ir~,.~x.Ve~ = P
where la~l,,,~,
(10)
is the maximum
allowable DCcurrent through M1. The overdrive voltage of M1(~IVu~..M1
V~,~tl - Vth.t~) has to be chosenaccording to the expectednoise voltage on the Vd~.For positive peaks on Vd~,
17
increases and the current through M1increases; whereas in negative peaks, AV~sj decreases. To make
sure that M1remains saturation region in negative peaks, 3Vg~qhas to be greater than K.V,,, whereVnis the
expectednoise peakon the Vda.Wefirst analyze the effect of the gain, K, in the circuit.
Considerthe simplified circuit schematicin Fig. 12. Assumethat the stage betweenthe noisy Vdaline and the
gate of MIis an ideal gain stage of K. Assumethat the target resistance value is R, small signal conductance
of M1is gm and the current through M1is I. If the overdrive voltage of M1is chosen as K. V, as discussed
above, we can write:
gm --
21
(11)
K.V,,
R-
1 _
K.gr~
I
W
1 _V,,
K 2~I 2I
2
(12)
(13)
Vgs
Figure 12. Simplified Active Resistor Schematic
If weassumethat for a given R, the noise peak on the Vadline is independentof the gain; from Eq. 12 wesee
that the total current required through the active resistor is independentof the gain. However,the gain will
18
help reduce the total area for the given current through Eq. 13, whichwill help reduce leakage current of MI.
If weignore the powerand area overheadof the gain stage K, wesee that there is not an improvementin the
total power consumptionby increasing K, but there is an area saving. One must take into account that K
cannot be increased abovea certain limit because of the gain stage overheadand the possibility that positive
peaks might not be accommodated
by high K values due to the high overdrive required at the gate (namely,
K.V,).
Once the K value has been determined and the overdrive of M1has been set, and since we knowthe target R
from the total parasitic inductance/on-chip decouplingcapacitance as in Eq. 4, wecan determine IMI (current
through M1)by the given total powerbudget from Eq. 10. That sets gmJand (W/L)1 through the equations:
gin! --
2IM~
AV~1
¯
(14)
Wecan choose L1 to be the minimumlength provided by the technology to minimize area, and that sets Wj.
Oncegin1 is determined, wecan determinethe ratio of gin2 and gin4 using Eq. 9. Since wenowknowWIand L~,
we can estimate
the total
capacitance
between gate of M1 and ground, which is predominantly
C~.~=Wj.L~.Co~.For a given minimumslew rate requirement SR at that node, and knowingthat 1~2<1~,we
can find l~e from:
I,~ = C~,.~.SR
(15)
Since dVe,1=dVe~.2, and we know1~, we can determine (W/L)2, and once again choose L2 to be the minimum
length for the process for area minimization. Having determined 1~2 and z/Vg,~2, wenowknowgin2 and can
determine gm4from Eq. 9. Wehave to choose dVgs4according to V, to ensure M4is in saturation, and that
determinesI~4 by using a similar equation to Eq. 14. Thechoice of zJ Ves~and (W/L),~is not critical as long as
the current IM.~ is chosen so that 1~= IM4-- IM2. That is a step-by-step approachto the determination of the
sizes and bias voltages for the topology given in Fig. 11. In a real design, a few iterations for the design
parameters might be required dependingon V, and the total powerbudget to find an optimal point.
19
An alternative implementationis shownin Fig. 13 that uses a second, higher powersupply. This topology has
the potential to greatly reduce the static powerconsumptionwhenthe transistors M1and M5are biased at the
edge of conduction. In that case, the upper block (transistors M5-M8)
responds to negative peaks in the Vdd,
whereas the lower block (M1-M4)responds to the positive peaks. Moreover, there is no need for the
anticipation of a gating signal, since the resistors respondautomatically to any voltage swing in the rails.
However,in this case the determination of the sizes of the transistors and bias voltages are morecomplicated
since the two blocks are not acting in saturation region all the time. One waywouldbe to approximatethe
operation of the blocks in the mid range of their swings and assumeit is a linear system swingingaround this
midpoint and carry out a similar procedure as described for the previous topology. However,in the dual
supply case, the gain of the amplifier block has a certain advantage in powerconsumption,since transistors
M1and M5are not biased with overdrives K. V,. A more detailed analysis of the design tradeoffs in this case
is one of the future worksfor this project. The optimal point might again require a few iterations.
In our
design, wehave chosen the samedevice sizes for the two blocks, and those sizes along with the bias voltages
are given in Table1. Vddis set at 1.2V, and Vod2is set at 2.4V.
0 Vdd2
Vbias4 0
’,~IV8
Vbias20
Figure 13. Alternative active resistor implementation.
20
Device/Spec.
W/L (#m/#m)
M1/M5
720/0.12
M2/M6
9.6/0.12
M3/M7
4.8/0.12
M4/M8
192/0.12
Voltage V)
Vbiasl
0.82
Vbias2
0.75
Vbias3
0,9
Vbias4
O.82
Table 1. Transistor sizes and bias voltages used in the design
3.2 Simulation Setup and Results
To test the efficiency of the proposedactive resistors for powergrid damping,a test chip has been built in
UMC
130nmCMOS
technology based on the topology given in Fig. 13. A block diagram of the chip is given
in Fig. 14. The test circuit consists of two main blocks; the active resistors and the switching block. The
switching circuits include two types of ring oscillators with two different oscillation frequencies, namely
2.35GHzand 5MHz.The high frequency (I-IF) oscillators emulate the latches that are switched on and off
using the on-chip clock, typically around 2GHzto 4GHzfor a state-of-the-art
microprocessor design in
current technologies. These ring oscillators have an AND
gate in their feedbackloop, and one of the inputs of
the ANDgate is connected to the buffered output of the low frequency (LF) ring oscillator
(Fig. 15).
Therefore, the LFring oscillator provides the clock gating signal to the HFoscillators. The low frequency of
5MHzwas chosen to generate a step disturbance by turning on the HFoscillators to create noise in the power
21
grid, allowing enoughtime for the oscillations to die out, and perform another step disturbance. The total
current consumptionof the switching block whenall oscillators are on is 56 mAfrom a 1,2Vpowersupply.
Bondwires
Package
Vd~2
Active
Resistor
(Upper
Decoupling
Block)
Ca
Vbias4
Vbias3
Vdc
External Clock
Gating
Control
Signals
Vbias2
Vbias1
Ground
Figure 14. Block diagram of the test chip that has been built
I nverters
Buffer
Clock
Gater ~
(RingOsc.)
~
~
GatedRing
Oscillator
(High Freq.)
Figure 15o Switching block in the test chip
In the actual implementation,two instances of the block diagramin Fig. 14 have been included with different
amountof on-chip decoupling capacitance; one with 253pF, the other with 167pF and both implementedas
22
NMOS
capacitors. The powergrids of the two instances are separated but they share the same on-chip ground
(substrate). The simulation results that follow are with the 253 pF on-chip decoupling version. The power
carded through non-ideal bondwireswith 4nil parasitic inductance and 37 ohmsparallel resistance, providing
a quality factor (Q) of 15 at 100MHz.The value of the parasitic inductor is determined by assuming a lnH
inductance per millimeter of bondwire length and an approximate total length of 4mm.The Q factor is
approximated based on experience. The number of ring oscillators
have been determined along with the
amountof total on-chip decoupling so that there will be approximately +15%noise on the power supply as
well as a resonant frequency of around 100MHz.The resonant frequency is chosen close to the one in a real
design, and it is a function of the parasitic inductance and the on-chip decoupling capacitance. The current
draw of the oscillators is chosen so that there will be around +_15%powersupply noise with the determined
on-chip decoupling capacitance. Since those approximations are highly dependent on the packaging quality,
several packagepins for Vaa/Gndhave been allocated to try different values of total parasitic inductance by
selectively connecting them on the board level, and two instances with different on-chip decoupling have
been included. In a real microprocessor design, more on-chip decoupling is needed due to higher switching
currents, necessitating a higher amountof charge transfer from the capacitors to keep the power supply
voltage within a safe operation region (generally +_10%).However,due to better packaging techniques and
more power/groundpins, the parasitic inductance is reduced; and the resonant frequency does not generally
deviate far from 100MHz.For schematic simulations, on-chip inductance and IR drop were neglected. It is
very difficult to estimate the on-chip inductancewithout field solvers, and as discussed above, they are not the
maincontributors of the global powersupply noise. On-chipIR drop has been neglected because the parasitic
resistance of the power/groundlines in the chip are expected to be muchsmaller than the parasitic resistance
of the bondwireswith a good layout, and thus they are not expected to change the Q factor of the network.
Thebias voltages are assumedto be perfect voltage shifts with respect to ground(Vbiasl,
Vbias2)or
Vdd (Vbias3,
Vbi,~4). Amodeselector determines the numberof high frequencyoscillators that are active, allowing testing
at a numberof different current dissipations. Anexternal clock gating signal rather than the one generated on
the chip can also be used. The topology in Fig. 13 has been used for active resistors because of its better
23
power performance comparedto the implementation in Figure 11. The total area of the chip, including the
~, and the active resistors
active resistors is 0.115 mm
occupy 6%of this area. The total static power
dissipation of the resistors is less than 2%of the total powerdissipation of the chip. However;it should be
noted that due to the use of ring oscillators,
the average numberof transitions that makea powerconsuming
transition in the test design nodes (i.e., the activity factor) is significantly higher comparedto a real digital
circuit. Thus, the actual area penalty in a real design with comparabletotal powerdissipation wouldbe much
less than 6%.
The simulated power grid impedance, as seen between the Vad and Gndnodes on the chip schematic, is shown
in Fig. 16 as a function of frequency. In this simulation setup, we ignore all resonances other than the one
caused by on-chip decoupling capacitors and package-chip parasitic inductors. Ideally, the impedanceof the
powergrid should be as fiat and low as possible so that oscillations wouldnot occur in the transient domain.
Resonant oscillations
in the transient domaincorrespond to peaks in the ACdomain. Dampingwith active
resistors provides a significant decrease in the powergrid impedance,especially in the resonant frequencies
around 100MHz.The peak impedanceis reduced by almost 75%after the active resistors are added.
Response
~ith ,sn,d v,,ithout. Active Resist:ors
~¥ilh Act. Res.
,I
Figure 16. Impedanceof the powergrid vs. frequency.
24
The schematic simulation results for transient voltage betweenthe Vaaand Gndon the chip are shownin Fig.
17. The oscillations caused by turning off the clock gating signal, or the positive peaks, are significantly
reduced both in amplitude and duration. The peak voltage was decreased by more than 60%for positive
peaks, whereasthe negative peak improvementis approximately15%.This difference can be attributed to the
inherent dampingwhichoccurs whenmore of the digital circuit blocks are active, and thereby providing some
amountof decouplingthrough the capacitances at the gate output nodes.
Power Supply Noise with and without Active Resistors
1,50
With Resistor
.40
"~ 1,20
1.10
1,00
200n
250n
500n
time ( s
550n
Figure 17. Transient simulation results.
It should be noted that reducing positive peaks is very important for the long term reliability of the chip to
prevent breakdowns.Because positive oscillations last muchlonger, it is very important to return to safe
operation V~dlevels on the chip within a short period of time to avoid loss of processing time. This is
especially important whenwe consider that the dominantresonance frequency in the powergrid is at a much
lower frequency (around 100MHz)compared to the operating frequency of modern processors (around
3GHz). Without damping, a significant
amount of latency would be required.
The negative peaks are
especially important in the case of memoriesor latches, whereexcessive drop in V~dmight cause the loss of
the stored information. Both peaks affect the delay through gates and thus cause problemsin timing.
25
On-chip decoupling capacitors are generally implementedas large-area MOScapacitors, which can contribute
substantial leakage current to the system. Byusing active resistors, the sameamountof noise suppression can
be achieved with less decoupling capacitance, which results in muchless leakage power. Fig. 18 shows a
projection of the leakage powerof the test design projected to 45nm[1], with and without the use of active
resistors. For a relative noise ratio of 0.2, an approximatesaving of 25%is projected. For 130nmtechnology,
wedon’t have gate leakage models; howeverat this processing node gate leakage is not generally a significant
concern.
Leakage Power vs. Relative Power Supply
Noise
200
180
¯
160
140
120 __~
100
~
*- 45nm
with Active
Resistor
45nmNo Resistor
20
0.1
0.3
0.5
0.7
0.9
(Overshoot+Undershoot) / Vdd
Figure 18. Leakagepowervs. relative powersupply noise. Projection of the test design to 45nm,ITRS
Roadmap[11.
26
3.3 Testing
The die shot for the fabricated chip is given in Fig. 19. Twoversions of the same circuit with different
amountsof on-chip decouplingwere placed on the test chip, wherepowergrids are separated frorn each other.
The power grids consist of parallel power and ground lines in the upper three metal layers and they are
strapped with vias at each metal level.
Figure 19. Die shot of fabricated testchip.
The chip has been packaged in an open-cavity LQFP44-pin package. There are 8 Vod/Gndpads on the chip
that are wire-bondedto the packagepins, those pins can then be connected on the board level. This allows a
rough control of the total parasitic inductance going into the chip through bondwiresthat determines the total
powersupply noise on the chip. There are two pins to supply a high supply voltage, Vda2,for each instance of
the circuit. There are 3 control pins for each instance; two of themcontrol whichcircuits are on. Onecan turn
on the clock gating oscillator (-5MHz)only, the high frequency oscillators only (~2.35GHz),a third of
high-frequencyoscillators and the clock gating oscillator, or all circuits. Thethird control signal is used to
27
select if an external signal or the on-chiposcillator is to be used for the gating signal. Thereis one pin for the
external clock gating signal. There are four DCbias voltages for each instance that are generated by an
external voltage source and adjusted using potentiometers on the board for the active resistors. Those are
supplied through packagepins. The bondedpads can be seen in the perimeter of the chip in Fig. 19.
In addition to the bondedpads, there are 9 unbondedVdd/Gndpads for each instance. These are left for wafer
probing the chip through a high-impedancewafer probe to see the on-chip supply noise. The wafer probe that
is used for this purpose is Picoprobe Model10 with 5k~ input impedance and a bandwidth of DCto 5GHz,
whichis sufficient for our purposes. Giventhat the impedanceof the circuits is not expected to exceed 100~
in the resonant frequency,the loading of the probe is negligible.
Fig. 20 showsa photo of the populated PCBfor testing. The board has 4 layers, with two in the middle being
Vaaand Gndplanes. These planes are separated for the bias voltage inputs and the powersupply, but the Gnd
is connected on the chip level. The power supply connections are made through BNCconnectors. The
Vd~/Gndconnections are connected through jumpers on the PCBlevel to determine which package pins will
be connected. Each power/groundstrip on the PCBis decoupled with two c0805 surface mount capacitors
(10pF, 100nF)before it is connected to the board power/groundplanes just near the package pins to reduce
any parasitic inductive effect of the PCBconnections. The power/groundplanes on the board are decoupled
with four more c0805 capacitors (10pF, lnF, 100nFand 10#F) and a tantalum capacitor (10/~F, 2.9f2 ESR
100kHz). The power supplies and the external clock signal are connected through BNCconnectors.
The PCBis placed on a Cascade Microtech probe station, and the probe output is amplified by a wideband
amplifier (ZFL-500LN
by MiniCircuits). The necessity for this stage is because of 1/100 attenuation of the
high impedanceprobe. The amplifier has a gain of 24dB, with bandwidth 0.1-100MHz,and noise figure of
2.9dB. The amplifier output is connected to a widebandoscilloscope.
28
Figure 20. PCBphoto.
The initial tests have shownthat the current draw of the chip exceeds 800mA,whichis significantly larger
than the expected maximum
value of 56mA.It has been seen that the impedanceseen from the bias voltage
nodes is in the order of several ohms. Since these nodes are connected to the gates of the active resistor
transistors,
it is believed that ESDevents have caused the breakdownof the gates since there is no ESD
protection on the chip level. Currently the population of a second PCBwith a new packaged chip with ESD
protection on the board is being carried out.
29
4. Conclusions
In this thesis, a novel methodfor reducing the powersupply noise in integrated circuits was presented. By
using active devices, the dampingis increased in powergrid distribution networkand oscillations resulting
from the underdampednature of the supply distribution grid are reduced considerably. Simulations conducted
in a 130nmCMOS
process show a reduction of the oscillation
reduction in the duration of oscillations.
amplitude by more than 40%with significant
Moreover, the same amountof noise suppression can be achieved
with less decoupling capacitance, thus providing a promising way of reducing leakage power in newer
process generations. The test design has been submitted for manufacturing,and initial tests have been carried
out. However,due to ESDprotection problems, experimental results are not yet available.
30
5. References
[ 1]
International
Technology
Roadmap
for
Semiconductors,
2003
Ed.,
http://public.itrs.net/Files/2OO3ITRS/Home2OO3.htm,July 2005
[2] Jacobson, H. et. al.,
processors",
"Stretching
the limits
of clock-gating
High-Performance Computer Architecture,
efficiency
11th International
in server-class
Symposium on, Feb.
2005 Pages:238 - 242.
[3] Gronowski, P., et. al., "A 433-MHz64-b Quad-Issue RISCMicroprocessor", IEEEJournal of Solid
State Circuits, Vol. 31, No.l 1, Nov.1996, Pages: 1687-1696.
[4] Muhtaroglu, A., et. al., "On-Die Droop Detector for Analog Sensing of Power Supply Noise", IEEE
Journal of Solid State Circuits, Vol. 39, No.4, Apr. 2004, Pages: 651-660
[5] Kundert, K., "Power Supply Noise Reduction", http://www.designers-guide.org/Desigrfoypassing.pdf,
July 2005.
[6] Ji, G., et. al., "Design and Validation of a Power Supply Noise Reduction Technique", Electrical
Performanceof Electronic Packaging, Oct. 2003.
[7] Gabara, T. et. al., "FormingDampedLRCParasitic Circuits in Simultaneously Switched CMOS
Output
Buffers", IEEEJournal of Solid State Circuits, Vol.32, No.3, March1997, Pages: 407-418
[8] Larsson, P., "Resonance and Dampingin CMOS
Circuits with On-Chip Decoupling Capacitance", IEEE
Transactions on Circuits and Systems-I, Vol. 45, No.8, August1998, Pages: 849-858.
31