EE247 Lecture 19
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EE247 Lecture 19 ADC Converters • Sampling (continued) – Clock boosters (continued) – Sampling switch charge injection & clock feedthrough • Complementary switch • Use of dummy device • Bottom-plate switching – Track & hold circuits – T/H circuit incorporating gain & offset cancellation • Electro-Static Discharge (ESD) protection EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 1 Summary Last Lecture • DAC Converters (continued) – DAC reconstruction filter • ADC Converters – Sampling • Sampling network thermal noise • Acquisition bandwidth limitations – For example 1% accuracyÆ Ts /2>5RC • Sampling switch induced distortion – Sampling switch conductance dependence on input voltage – Complementary switch – Clock boosters EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 2 Boosted Clock Sampling Complete Circuit Clock Multiplier M7 & M13 for reliability Remaining issues: -VGS constant only for Vin <Vout -Nonlinearity due to Vth dependence of M11on bodysource voltage Switch Ref: A. Abo et al, “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” JSSC May 1999, pp. 599. EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 3 Advanced Clock Boosting Technique Ref: M. Waltari et al., "A self-calibrated pipeline ADC with 200MHz IFsampling frontend," ISSCC 2002, Dig. Tech. Papers, pp. 314 Sampling Switch EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 4 Advanced Clock Boosting Technique clkÆ low Sampling Switch • clkÆ low – Capacitors C1a & C1b Æ charged to VDD – MS Æ off – Hold mode EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 5 Advanced Clock Boosting Technique clkÆ high • clkÆ high – – – – Sampling Switch Top plate of C1a & C1b connected to gate of sampling switch Bottom plate of C1a connected to VIN Bottom plate of C1b connected to VOUT VGS & VGD of MS both @ VDD & ac signal on G of MS Æ average of VIN & VOUT EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 6 Advanced Clock Boosting Technique Ref: M. Waltari et al., "A self-calibrated pipeline ADC with 200MHz IFsampling frontend," ISSCC 2002, Dig. Tech. Papers, pp. 314 Sampling Switch • Gate tracks average of input and output, reduces effect of I·R drop at high frequencies • Bulk also tracks signal ⇒ reduced body effect (technology used allows connecting bulk to S) • Reported measured SFDR = 76.5dB at fin=200MHz EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 7 Constant Conductance Switch Ref: H. Pan et al., "A 3.3-V 12-b 50-MS/s A/D converter in 0.6um CMOS with over 80-dB SFDR," IEEE J. Solid-State Circuits, pp. 1769-1780, Dec. 2000 EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 8 Constant Conductance Switch OFF Ref: H. Pan et al., "A 3.3-V 12-b 50-MS/s A/D converter in 0.6um CMOS with over 80-dB SFDR," IEEE J. Solid-State Circuits, pp. 1769-1780, Dec. 2000 EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 9 Constant Conductance Switch M2Æ Constant current Æ constant gds M1Æ replica of M2 & same VGS as M2 Æ M1 also constant gds ON • Note: Authors report requirement of 280MHz GBW for the opamp for 12bit 50Ms/s ADC • Also, opamp common-mode compliance for full input range Ref: H. Pan et al., "A 3.3-V 12-b 50-MS/s A/D converter in 0.6um CMOS with over 80-dB SFDR," IEEE J. Solid-State Circuits, pp. 1769-1780, Dec. 2000 EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 10 Switch Off-Mode Feedthrough Cancellation Ref: M. Waltari et al., "A self-calibrated pipeline ADC with 200MHz IF-sampling frontend," ISSCC 2002, Dig. Techn. Papers, pp. 314 EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 11 Practical Sampling φ1 Vi Vo M1 C • Rsw = f(Vi) Æ distortion • Switch charge injection & clock feedthrough EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 12 Sampling Switch Charge Injection & Clock Feedthrough Switching from Track to Hold VG VG VH Vi +Vth Vi Vi VL M1 Cs t VO VO ΔV Vi t toff • First assume Vi is a DC voltage • When switch turns off Æ offset voltage induced on Cs • Why? EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 13 Sampling Switch Charge Injection Distributed channel resistance & gate & junction capacitances G Cov Cov MOS xtor operating in triode region Cross section view LD L S D CHOLD Cjdb Cjsb B • • • • Channel Æ distributed RC network formed between G,S, and D Channel to substrate junction capacitance Æ distributed & voltage dependant Drain/Source junction capacitors to substrate Æ voltage dependant Over-lap capacitance Cov = LDxWxCox’ associated with G-S & G-D overlap EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 14 Switch Charge Injection Slow Clock VH VG Device still conducting Vi +Vth Vi VL t t- toff • Slow clockÆ clock fall time >> device speed Æ During the period (t- to toff) current in channel discharges channel charge into low impedance signal source • Only source of error Æ Clock feedthrough from Cov to Cs EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 15 Switch Clock Feedthrough Slow Clock VG VG VH Cov Vi +Vth Vi D Cs VL t VO ΔV = − Cov Cov + Cs (Vi +Vth −VL ) Co v (Vi +Vth −VL ) Cs Vo = Vi + Δ V ⎛ C ⎞ C C Vo = Vi − o v (Vi + Vth −VL ) = Vi ⎜ 1 − o v ⎟ − o v (Vth −VL ) ⎜ Cs Cs ⎟⎠ Cs ⎝ Vo = Vi (1 + ε ) + Vos ≈− wh e re ε = − ΔV Vi Cov Cs ; Vo s = − Cov Cs t- toff t (Vth −VL ) EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 16 Switch Charge Injection & Clock Feedthrough Slow Clock- Example VG 10μ/0.18μ Vi M1 VG VO VH Cs=1pF Vi Vi +Vth VL t VO C' ov = 0.1 fF / μ Cox = 9 fF / μ 2 Vth = 0.4V VL = 0 ΔV Vi 10 μ x0.1 fF / μ =− = − .1% Cs 1pF Allowing ε = 1/ 2LSB → ADC r e solution <~ 9bit ε =− Cov Vos = − Cov Cs t- toff (Vth −VL ) = − 0.4mV t EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 17 Switch Charge Injection & Clock Feedthrough Fast Clock Qch VG Vi nQch n+m=1 VG M1 mQch VH Vi +Vth VO Vi Cs=1pF VL t VO ΔV Vi toff t • Sudden gate voltage drop Æ no gate voltage to establish current in channel Æ channel charge has no choice but to escape out towards S & D EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 18 Switch Charge Injection & Clock Feedthrough Fast Clock VG Clock Fall-Time << Device Speed: VH Δ Vo = − ≈− Co v Co v + Cs 1 (VH −VL ) − 2 Vi +Vth Q × ch Cs Vi 1 WCox L ( (VH −Vi −Vth ) ) Co v Co v + Cs (VH −VL ) − × 2 Cs VL Co v Cs ΔV Vi 1 WCo x L w he r e ε = × 2 Cs Vo s = − t VO Vo = Vi − Vo = Vi (1 + ε ) + Vo s 1 WCo x L (VH −Vth ) (VH −VL ) − × 2 Cs toff t • For simplicity it is assumed channel charge divided equally between S & D • Source of error Æ channel charge transfer + clock feedthrough via Cov to Cs EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 19 Switch Charge Injection & Clock Feedthrough Fast Clock- Example VG VG 10μ/0.18μ Vi VH Vi +Vth VO M1 VIN Cs=1pF VL t VO ΔV Vi Cov = 0 .1 fF / μ Co x = 9 fF / μ 2 Vt h = 0 .4V VD D = 1. 8V VL = 0 ε = 1/ 2 Vo s = − WLCo x Co v Cs Cs = 1 0μ x0.1 8 μ x9 fF / μ 2 1p F 1 WCo x L (VH −Vth ) (VH −VL ) − × 2 Cs = 1 .6% → ~ 5 − bit toff t = − 1. 8m V − 1 4 . 6mV = − 1 6.4m V EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 20 Switch Charge Injection & Clock Feedthrough Slow Clock versus Fast Clock Vo Vo ΔV ΔV Vi Vi Slow Clock Fast Clock EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 21 Switch Charge Injection & Clock Feedthrough Example-Summary ε VOS 1.6% 16mV .1% 0.4mV Clock fall time Clock fall time Error function of: Æ Clock fall time Æ Input voltage level Æ Source impedance Æ Sampling capacitance Æ Switch size Clock fall/rise should be controlled not be faster (sharper) than necessary ³ EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 22 Switch Charge Injection Error Reduction • How do we reduce the error? Æ Reduce switch size? Δ Vo = − 1 Qch 2 Cs τ = RON Cs = ↓ μCo x Cs W L (VGS −Vth ) ↑ ( note : Ts 2 = kτ ) Co nside r th e figu re of me rit ( F OM) : W μCox (VG S −Vth ) 1 Cs L ×2× ≈ FOM = τ × Δ Vo Cs WCox L ( (VH −Vi −Vth ) ) → FOM ≈ μ L2 Reducing switch size increases τ Æ increased distortionÆ not a viable solution Small τ and small ΔV Æ use minimum chanel length (mandated by technology) For a given technology τ x ΔV ~ constant EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 23 Sampling Switch Charge Injection & Clock Feedthrough Summary • Extra charge injected onto sampling capacitor @ switch device turn-off –Channel charge injection –Clock feedthrough to Cs via Cov • Issues: –DC offset –Input dependant error voltage Æ distortion • Solutions: –Complementary switch? –Addition of dummy switches? –Bottom-plate sampling? EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 24 Switch Charge Injection Complementary Switch VG φ1 VH φ1B φ1 Vi φ1B VL t φ1 φ1B • In slow clock case if area of n & p devices widths are equal (Wn=Wp)Æ effect of overlap capacitor for n & p devices to first order cancel (cancellation accuracy depends on matching of n & p width and ΔL) • Since in CMOS technologies μn~2.5μp choice of Wn=Wp not optimal from linearity perspective (Wp>Wn preferable) EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 25 Switch Charge Injection Complementary Switch Fast Clock Qc h − n = WnCo x Ln (VH −Vi − Vth − n ) Qc h − p = WpCox Lp (Vi −VL − Vth − p ) Qc h − p 1⎛ Q Δ Vo ≈ − ⎜ c h − n − ⎜ 2 ⎝ Cs Cs ⎞ ⎟⎟ ⎠ Vo = Vi (1 + ε ) + Vos 1 WnCo x Ln + WpCox Lp ε≈ × 2 VG VH Vi VL t φ1 Cs • In fast clock case To 1st order, offset due to overlap caps cancelled for equal device width Input voltage dependant error worse! EECS 247 Lecture 19: Data Converters φ1B © 2006 H.K. Page 26 Switch Charge Injection Dummy Switch VG VGB M2 M1 Vi Q1 VO VH VG VGB Vi Q2 Cs WM2=1/2WM1 VL t 1 Q1 ≈ QcMh 1 + QoMv 1 2 M2 Q2 ≈ QcMh 2 + 2Qov 1 F or WM 2 = WM 1 → Q2 = −Q1 2 EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 27 Switch Charge Injection Dummy Switch VG VGB M2 M1 Vi Q1 Q2 WM2=1/2WM1 VO VH VG VGB Vi Cs VL t • Dummy switch same L as main switch but half W • Main device clock goes low, dummy device gate goes high Æ dummy switch acquires same amount of channel charge main switch needs to lose • Effective only if exactly half of the charge transferred to M2 (depends on input/output node impedance) and requires good matching between clock fall/rise EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 28 Switch Charge Injection Dummy Switch Vi VG VGB WM2 M1 M2 =1/2WM1 R Cs VO Cs To guarantee half of charge goes to each sideÆ create the same environment on both sides Add capacitor equal to sampling capacitor to the other side of the switch + add fixed resistor to emulate input resistance of following circuit Æ Issues: Degrades sampling bandwidth EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 29 Dummy Switch Effectiveness Test • Dummy switch Æ W=1/2Wmain • As Vin is increased Vc1-Vin is decreased Æ channel charge decreasedÆ less charge injection • Note large Ls Ægood device area matching Ref: L. A. Bienstman et al, “ An Eight-Channel 8 13it Microprocessor Compatible NMOS D/A Converter with Programmable Scaling”, IEEE JSSC, VOL. SC-15, NO. 6, DECEMBER 1980 EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 30 Switch Charge Injection Differential Sampling φ VO+ Vi+ Vo + −Vo − = Vo d Vi + − Vi − = Vid Vo + + Vo − Vi + + Vi − Vo c = Vic = 2 Vo + = Vi + (1 + ε1 ) + Vos1 Cs 2 Vo − = Vi − (1 + ε 2 ) + Vos2 Vo d = Vi d + Vi d (ε1 + ε 2 ) + (ε − ε )V + V −V 1 2 ic os1 os2 2 VOVi- • To 1st order, offset terms cancel • Note gain error ε still about the same • Has the advantage of better immunity to noise coupling and cancellation of even order harmonics Cs EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 31 Switch Charge Injection Bottom Plate Sampling φ1a φ1b VH M1 VO Vi Cs φ1a VL φ1b M2 t • Switches M2 opened slightly earlier compared to M1 Æ Injected charge by the opening of M2 is constant & eliminated when used differentially • Since Cs bottom plate open when M1 openedÆ no charge injected on Cs EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 32 Flip-Around Track & Hold φ2 S2A φ1 φ1D φ1D φ2 φ1D vIN C φ2 S3 vOUT S2 S1A φ1 S1 • Concept based on bottomplate sampling vCM EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 33 Flip-Around T/H-Basic Operation φ1Æhigh φ2 S2A φ1 φ1D φ1D φ2 φ1D vIN C φ2 S3 vOUT S2 S1A φ1 Qφ1=VINxC S1 vCM EECS 247 Lecture 19: Data Converters Charging C Note: Opamp has to be stable in unity-gain configuration © 2006 H.K. Page 34 Flip-Around T/H-Basic Operation φ2Æhigh φ2 S2A φ1 φ1D φ1D φ2 φ1D vIN φ2 C S3 Holding vOUT S2 S1A φ1 S1 vCM Qφ2=VOUTxC Æ VOUT=VIN EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 35 Flip-Around T/H - Timing φ 2 S2A vIN φ1D C φ2 φ1 φ1D S3 φ1 S1 vCM EECS 247 Lecture 19: Data Converters φ2 vOUT S2 S1A φ1D S1 opens earlier than S1A No resistive path from C bottom plate to Gnd Æ charge can not change "Bottom Plate Sampling" © 2006 H.K. Page 36 Charge Injection • At the instant of transitioning from track to hold mode, some of the charge stored in sampling switch S1 is dumped onto C • With "Bottom Plate Sampling", only charge injection component due to opening of S1 and is to first-order independent of vIN – Only a dc offset is added This dc offset can be removed with a differential architecture EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 37 Flip-Around T/H φ2 Constant switch VGS to minimize distortion S2A φ1 φ1D φ1D φ2 φ1D vIN C φ2 S3 vOUT S2 S1A φ1 S1 vCM EECS 247 Lecture 19: Data Converters Note: Among all switches only S1A & S2A experience full input voltage swing © 2006 H.K. Page 38 Flip-Around T/H • S1 is chosen to be an n-channel MOSFET • Since it always switches the same voltage, it’s onresistance, RS1, is signal-independent (to first order) • Choosing RS1 >> RS1A minimizes the non-linear component of R = RS1A+ RS1 – S1A is a wide (much lower resistance than S1) & constant VGS switch – In practice size of S1A is limited by the (nonlinear) S/D capacitance that also adds distortion – If S1A’s resistance is negligible Æ delay depends only on S1 resistance – S1 resistance is independent of VIN Æ error due to finite time-constant Æ independent of VIN EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 39 Differential Flip-Around T/H S11 S12 Offset voltage associated with charge injection of S11 & S12 cancelled by differential nature of the circuit During input sampling phaseÆ amp outputs shorted together Ref: W. Yang, et al. “A 3-V 340-mW 14-b 75-Msample/s CMOS ADC With 85-dB SFDR at Nyquist Input,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 12, DECEMBER 2001 1931 EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 40 Differential Flip-Around T/H φ1’ φ1 φ2 • Gain=1 • Feedback factor=1 EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 41 Differential Flip-Around T/H Issues: Input Common-Mode Range • ΔVin-cm=Vout_com-Vsig_com Æ Amplifier needs to have large input common-mode compliance EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 42 Differential Flip-Around T/H Choice of Sampling Switch Size •THD simulated w/o sampling switch boosted clock Æ -45dB •THD simulated with sampling switch boosted clock (see figure) Ref: K. Vleugels et al, “A 2.5-V Sigma–Delta Modulator for Broadband Communications Applications “ IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 12, DECEMBER 2001, pp. 1887 EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 43 Input Common-Mode Cancellation •Shorting switches M4, M5 added Ref: R. Yen, et al. “A MOS Switched-Capacitor Instrumentation Amplifier,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-17, NO. 6,, DECEMBER 1982 1008 EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 44 Input Common-Mode Cancellation Track mode (φ high) VC1=VI1 , VC2=VI2 Vo1=Vo2=0 Hold mode (φ low) Vo1+Vo2 =0 Vo1-Vo2= -(VI1-VI2)(C1/(C1+C3)) Æ Input common-mode level removed EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 45 T/H + Charge Redistribution Amplifier Track mode: (S1, S3 Æon S2Æ off) VC1=Vos –VIN , VC2=0 Vo=Vos EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 46 T/H + Charge Redistribution Amplifier Hold Mode 22 1 Hold/amplify mode (S1, S3 Æoff S2Æ on) Æ Offset NOT cancelled, but not amplified Æ Input-referred offset =(C2/C1) x VOS, & C2<C1 EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 47 T/H & Input Difference Amplifier Sample mode (S1, S3 Æon S2Æ off) VC1=Vos –VI1 , VC2=0 Vo=Vos EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 48 Input Difference Amplifier Cont‘d Subtract/Amplify mode (S1, S3 Æoff S2Æ on) During previous phase: VC1=Vos –VI1 , VC2=0 Vo=Vos 1 ÆOffset NOT cancelled, but not amplified ÆInput-referred offset =(C2/C1)xVOS, & C2<C1 EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 49 T/H & Summing Amplifier EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 50 T/H & Summing Amplifier Cont‘d Sample mode (S1, S3, S5Æon S2, S4Æ off) VC1=Vos –VI1 , VC2=Vos-VI3, VC3=0 Vo=Vos EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 51 T/H & Summing Amplifier Cont‘d Amplify mode (S1, S3, S5Æoff, S2, S4Æ on) 3 EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 52 Differential T/H Combined with Gain Stage Employs the previously discussed technique to eliminate the problem associated with high common-mode voltage excursion at the input of the opamp Ref: S. H. Lewis, et al., “A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter” IEEE JSSC, VOL. SC-22,NO. 6, DECEMBER 1987 EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 53 Differential T/H Combined with Gain Stage φ1 Æ High Ref: S. H. Lewis, et al., “A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter” IEEE JSSC, VOL. SC-22,NO. 6, DECEMBER 1987 EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 54 Differential T/H Combined with Gain Stage • Gain=4C/C=4 • Input voltage common-mode level removed Æ opamp can have low CMRR • Amplifier offset NOT removed Ref: S. H. Lewis, et al., “A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter” IEEE JSSC, VOL. SC-22,NO. 6, DECEMBER 1987 EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 55 Differential T/H Including Offset Cancellation • Operation during offset cancellation phase shown • Auxilary inputs added with Amain/Aaux.=10 • During offset cancellation phase: •Aux. amp configured in unity-gain mode: Vout=Vosmain Æ offset stored on CAZ & canceled Ref: H. Ohara, et al., "A CMOS programmable self-calibrating 13-bit eight-channel data acquisition peripheral," IEEE Journal of Solid-State Circuits, vol. 22, pp. 930 - 938, December 1987. EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 56 Differential T/H Including Offset Cancellation Operational Amplifier • Operational amplifier Æ dual input folded-cascode opamp • M3,4 auxiliary input, M1,2 main input • To achieve 1/10 gain ratio WM3, 4 =1/10x WM1,2 & current sources are scaled by 1/10 • M5,6,7 Æ common-mode control • Output stage Æ dual cascode Æ high DC gain Vout=gm1roVin1 + gm2roVin2 Ref: H. Ohara, et al., "A CMOS programmable self-calibrating 13-bit eight-channel data acquisition peripheral," IEEE Journal of Solid-State Circuits, vol. 22, pp. 930 - 938, December 1987. EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 57 Differential T/H Including Offset Cancellation Phase + (VINAZ+ -VINAZ- )= -gm1/gm2 Voffset - Voffset • During offset cancellation phase AZ and S1 closed Æ main amplifier offset amplified by gm1/gm2 & stored on CAZ • Auxiliary amp chosen to have lower gain so that: Aux. amp offset & charge injection associated with opening of switch AZ Æ reduced by Aaux/Amain=1/10 Low increase in power dissipation resulting from addition of aux. inputs • Requires an extra auto-zero clock phase EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 58 ESD Protection ADC Architectures EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 59 What is ESD? • Electrostatic discharge • Example: Charge built up on human body while walking on carpet... • Charged objects near or touching IC pins can discharge through on-chip devices • Without dedicated protection circuitry, ESD events could be destructive EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 60 Model and Protection Circuit [http://www.idt.com/docs/AN_123.pdf] [http://www.ce-mag.com/archive/03/ARG/dunnihoo.html] EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 61 Equivalent Circuit • Nonlinear capacitance causes distortion • Distortion increases with frequency – Today's converters: High frequency, low distortion! Ref: I. E. Opris, "Bootstrapped pad protection structure," IEEE J.Solid-State Circuits, pp. 300, Feb. 1998 EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 62 ESD Circuit Distortion Ref: I. E. Opris, "Bootstrapped pad protection structure," IEEE J.Solid-State Circuits, pp. 300, Feb. 1998. C(Vin)= 2......4pF for Vin=2....0V EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 63 ESD Circuit Distortion • Analysis: – Volterra Series – Or SPICE simulations • Example: vi vo R Cj EECS 247 Lecture 19: Data Converters CL R=25Ω Cjo=1pF CL=5pF Vipeak=0.5V © 2006 H.K. Page 64 -60 3rd Order Harmonic Distortion [dBc] 2nd Order Harmonic Distortion [dBc] ESD Circuit Distortion -80 -100 -80 -100 -120 6 10 7 10 8 9 10 10 Input Frequency 10 10 6 10 7 8 9 10 10 10 Input Frequency 10 10 HD3(@ 37.5MHz) = -92dB HD3(@ 100MHz) = -84dB EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 65 ESD Circuit Distortion • Distortion from ESD circuits approaches state of-the-art ADC performance! • If you are working on a new, record breaking ADC, better think about ESD now... • Ref.: A. Wang, "Recent developments in ESD protection for RF IC," Proc. DAC Conference, Jan. 2003 • Solutions still pre-mature • Lots of company intellectual property! (IP) EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 66 ADC Architectures • • • • • • Slope Converters Successive approximation Flash Folding Time-interleaved / parallel converter Residue type ADCs – – – – Two-step Pipeline Algorithmic … • Oversampled ADCs EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 67 Single Slope ADC VRamp Ramp Generator VIN stop Counter start "0" VRamp Clock • Low complexity • Hard to generate precise ramp • Better: Dual Slope, Multi-Slope EECS 247 Lecture 19: Data Converters Time © 2006 H.K. Page 68 Dual Slope ADC http://www.maxim-ic.com/appnotes.cfm/appnote_number/1041 • Integrate Vin for fixed time, de-integrate with Vref applied Æ TDe-Int ~ Vin/Vref • Insensitive to most linear error sources EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 69 Successive Approximation ADC Reset DAC VIN VREF Set DAC[MSB]=1 DAC 1ÆMSB Y Control Logic VIN>VDAC? N 0ÆMSB Set DAC[MSB-1]=1 Clock 1Æ[MSB-1] Y VIN>VDAC? N 0Æ[MSB-1] .. .. 1Æ[LSB] • Binary search over DAC output EECS 247 Lecture 19: Data Converters Y VIN>VDAC? N 0Æ[LSB] DAC[Input]= ADC[Output] © 2006 H.K. Page 70 Successive Approximation ADC Example: 6-bit ADC & VIN=5/8VREF VDAC/VREF VIN VREF DAC Control Logic 1 3/4 5/8 1/2 1/2 3/4 5/8 11/16 21/32 41/64 VIN Clock Time / Clock Ticks ADCÆ101000 • High accuracy achievable (16+ Bits) • Moderate speed proportional to B (MHz range) EECS 247 Lecture 19: Data Converters © 2006 H.K. Page 71
