SESSION 111: SOLID-STATE DEVICES
Chairman:
Richard C. Jaeger
Auburn University
WAM 3.1-INVITED:
Circuit Scaling Limits for Ultra-Large-Scale Integration
James D. Meindl, K.
Auburn, A L
N. Ratnakumar, Levy Gerzberg and Krishna C. Saraswat
Stanford University
Stanford, CA
LIMITS ON INTEGRATED ELECTRONICS have been of keen
interest for more than a decade’ -6. Classifications of limits such
as fundamental, physical, electrical, technological, practical and
c o m p l e x i t y have often lacked consistency and coherence. This
discussion will propose a more codified view of basic limits, discuss
circuit limits, projecting minimum feature sizes for NMOS transistors, polysilicon resistors and interconnections, andsuggest future
levels of ULSI implied by these sizes.
ULSI is governed by a hierarchy of limits; Figure 1. Each of
the five levels of this hierarchy is constrained by all preceding
levels. Briefly, there are five limits, representing each level.
(I)-A fundamental limit derived from thermodynamics
requiring the energy expenditure per switching transition
__
‘Wallmark, J . T., “Basic Considerations in Microelectronics,’’
in McGraw-HillMicroelectronics,
E. Keonjian,ed.,P.
10-96;
1963.
‘Keyes, R. W., “Physical Problems and Limits in Computer
Logic,” IEEE Spectrum, Vol. 6, No. 5, p. 36-45;May, 1969.
3Hoeneisen, B. and Mead, C.,“FundamentalLimitations in
Microelectronics - I . MOS Technology,” Solid State Electronics,
Vol, 15, p. 819-829; 1972.
4Swanson, R. M. and Meindl, J. D., “Fundamental Performance Limits of MOS Integrated Circuits,” ISSCC DIGEST OF
T E C H N I C A L P A P E R S , p. 110-111;Feb., 1975.
’Keyes, R. W., “Physical
Limits
in
Digital
Electronics,”
Proc. IEEE, Vol. 63, No. 5, p. 740-767; May, 1975.
6Rideout, V. L.,“Physical
and ElectricalLimitations
to
Improvement of Silicon Integrated Circuits,” IEEETutorial,
Stanford University, Am., 1978.
and Expected
7Hart. P. A. H., et al, “Device Down Scaling
Vol.
Circuit Performance,” IEEETrans.onElectronDevices,
ED-26, No. 4, p. 421-429; Apr., 1 9 7 9 .
8Dennard, R. H., et al, “Design of Ion-Implanted
MOSFETs
With Very SmallDimensions,”
IEEE J. SolidStateCircuits,
Vol. SC-9, NO. 5, p. 256-267; Oct., 1974.
9Special Issue o n VLSI, IEEETrans.onElectronDevices,
Vol. ED-26, No. 4; Apr., 1979.
“Ratnakumar, K. N., Meindl, J. D.
and
Bartelink, D.,
“Performance Limits of E/D NMOS VLSI,” ISSCC DIGEST O F
T E C H N I C A L P A P E R S , P. 72-73; Feb., 1980.
l l I t o , T . , et al. “Thermal Nitride Gate FET Technology for
VLSI
Devices,”
ISSCCDIGEST
O F T E C H N I C A LP A P E R S ,
p. 74-75; Feb., 1980.
”Lu, N. C. C., Gerzberg, L., Lu, C. Y . and Meindl, J. D.,
“ANewConductionModelforPolycrystallineSiliconFilms,”
IEDM Technical Digest, P. 833-834, Dec., 1980.
13Moore, G. E., “Progress in Digital Electronics,” I E D M
Technical Digest, p. 11-13, Dec., 1975.
14Keyes, R . W., “The
Evolution
of Digital Electronics
Towards VLSI,” IEEE Trans. on Electron Devices,
Vol. ED-26,
No. 4 ; Apr., 1979.
>
in a digital system to be E,
4kT = 1.65 x lo-’’ joules.
(2)-A material limit for silicon requiring the transit time of
an electron (At) through a potential drop AV to be
At AV/V,E, = 0.416 ps for AV = 1V, vs the scattering
limitedvelocity andthe
criticalfield.
(3)-A device limit for an N-channel MOS transistor to avoid
punch-through requiring a sourfe-todrain spacing
] = 0.18pm for substrate
L 2 [2€Si (VD+ $ b i ) / q N ~ /z
doping NA = 1.5 x 10’ 7/cm3 and drainvoltage VD = 0.5V.
(4)-A circuit limit for a CMOS inverter requiring an average
power drain PAVE= CL Vdd’f where CL is the load capacitance, Vdd the drain supply voltage and f the frequency of
excitation.
(5)-The system level consists of a number of sublevels which
include both software and applications constraints. Consequently, system limits represent the most numerousand
nebulous group of the hierarchy albeit potentially the most
profoundly important.
Any level of the hierarchy can be split into two generic metalevels; Figure l. At the circuit level the conceptual metalevel is
intrinsic or independent of the fabrication equipmentor technology
used to produce a chip, while the practical metalevel depends, for
example, on whether photolithography or X-ray lithography is
used.
It is important to recognize three unique features of the circuit
level.
(])-It is the highest level of the hierarchy which retains a
complete description of the physical attributes of a monolithic structure.
(2)-Given an appropriate model, it describes the behavior of
a device not in sterile isolation, but rather in itsnatural
operating environment7.
(3)-It is therefore capable of providing more relevant descriptions of minimum featuresi8es for ULSI than the device
level per se.
Defining a device scaling factor S 1, thekey results of constant electric field scaling theory for MOS transistors are improvements in gate delay as l/S, packing density as S squared and
speed-power product as 1/S cubed’. Minimum feature size scaled
down linearly from 25pm in 1961 to2.5pm in 1980. Projecting
this rate of scaling to 1999 implies a minimum featuresize ( L
channel length of 0 25pm. So-called s e c o n d o r d e r MOS transistor
characteristics , whlch may prevent this additional 1 0 : l reduction,
include subthreshold current, short channel effects, narrow channel
effects, second gate effects of the drain, punch-through, avalanche
multiplication and hot electrons. To project the in circuit impact
of these and other characteristics, efficient MOS transistor models
are needed. Based on recent efforts”, a simple, but powerful,
circuit model has been defined. A key feature of the derivation
of this quasi-twodimensional charge-sharing model is a simple
analytic description of both the X and Y components of electric
field between source, drain andgate charges on the one hand and
channel depletion and inversion layer charges on the other. This
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4 :
model has been usedto analyze both statictransfer characteristics
and dynamic behavior and thent o project the performance limits
of enhancementdepletion NMOS NOR gate logic (Figure 2)
including the major effects of fabrication tolerances and operating
temperature range as well as onloff pass gates and silicon nitride
dielectrics’
Again defining a device scaling factorS 2 1,resistor scaling
theory calls for reducing all dimensions as well as resistivity by the
same factor l/S. Scaling polycrystalline silicon resistivity requires
an accurate electrical model”. To maintain adequate circuit
performance, sensitivity of resistance to applied voltage ISv 1k1
requires 1 / s scaling of supply voltage Vdd, number of silicon
grains per resistor Ng and overall resistor lengthL; Figure 3.
Both a device scaling factorS 2 1 (describing smaller device
dimensions) and a chipscaling faetor Sc 1 (describing larger
chip dimensions) are neededto elucidate interconnect scaling
theory. A minor problem associate with scalin local interconnections, within a gateor flip-flop fore x a m p l j , is that local
interconnect RC circuit response time remains fixed as gate delay
scales as 1/S. A major problem in chip design is that long distance
interconnections, from corner-to-corner of the chip for example,
exhibit an RC circuit response time that scales as (SSc)2 and thus
quickly tends t o dominate overall operating speed. This severe
problem manifests itself initially in thecase of first level polysilicon
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interconnections and laterwith silicide and then metal interconnections; Figure 4. To preserve intrinsic speed capability, long
distance interconnect delay time must not dominategate delay
thus suggesting limits on interconnect length.
In summary, circuit scaling limits suggest
that MOS transistor
and polysilicon resistor dimensions can be scaleddown by
approximately another factor of ten. However, unless long
distance interconnect response time is reduced throughincreasing
interconnect conductivity and decreasing average interconnect
length via new chip architectures, many potential advantages
(e.g., operating speed) of furtherdevice scaling will be compromised.
Observing that device dimensions scaled downfrom 25pm in
1961 to 2.5pm in 1980 and chip dimensions scaledup from
1.41.4mm
x
t o 8 8mm
x during
the
same
the
preceding scaling analysis suggeststhe possibility of ULSI of
approximate1 lo7 transistors per chip through device scaling
alone and 10 transistors per chip through device and chip
scaling combined about the year 2000.
si
Acknowledgments
The contributions of N. C. C. Lu and F. Mohammadi t o this
research are gratefully acknowledged.
.-.
FUNDAMENTAL
2 . MATERIAL
3. DEVICE
1.
DRAINSUPPLY VOLTAGE
VOLTAGE INCREMENT PER GRAIN
NUMBER OF GRAINS
LENGTH OF RESISTOR
CONCEPTUAL
4. [CIRCUIT
PRACTICAL
BEFORE
SCALING
AFTER
SCALING
5 volt
50.1 volt
250
25P
0 . 5 volt
5 0.1 volt
25
L 0.51~
5. SYSTEM
FIGURE 3-Polysilicon resistor scaling.
FIGURE l-Hierarchy of limits for ULSI.
I
-
I
1
/I
V
DEVICE
PARAMETER
ZERO FABRICATION
TOLERANCE,
TEMP. = 3OoC
v)
0
C
(D
C
v
CHANNEL
LENGTH L
0.22 pm
SUPPLY VOLTAGE
0.36 V
OXIDE THICKNESS
50 A
CHANNEL DOPING
POWER-DELAY
(OF INVERTER)
E
-
wl-
1.6 x lo1’ ~rn’~
0.02 fJ
I i’
..
GATE DELAY
1
30 ps
FAN-OUT
YEAR
FIGURE 2-Limits for NOR gate logic.
I
FIGURE 4-Delay times.
I