Front End Readout Electronics – for strips
OUTLINE
UK programme incorporates development of 130 nm readout chip for short strips
early thoughts were to develop digital APV type chip
have decided to go for a binary un-sparsified architecture
will go through arguments briefly again here
have also decided to go for full-size chip on first iteration
will explain reasoning and present preliminary specifications
Mark Raymond, Imperial College
1
digital APV architecture
FE amp
analog pipeline
pipe readout
analog
MUX
ADC
digital
digital
CM subtract
+
sparsify
digital
serialize
+ O/P
driver
off-chip
slow control,
bias
bias,
test pulse,
……
assumption has been that ADC on every channel (before pipeline) needs too much power
still valid? maybe not in future processes (90, 65 nm)
some new ADC architectures are beating previous power predictions *
but negligible power / channel still seems long way off
negligible power/channel is achievable if relatively high power ADC shared between all front end channels
but this architecture still brings some disadvantages
2
*see - A. Marchioro - http://indico.cern.ch/getFile.py/access?contribId=26&resId=0&materialId=slides&confId=41832
digital APV architecture disadvantages
FE amp
analog pipeline
pipe readout
analog
MUX
ADC
digital
digital
digital
CM subtract
+
sparsify
y
serialize
+ O/P
driver
off-chip
slow control,
bias,
test p
pulse,,
……
very complicated chip – all the complexity of APV + more
fast ADC required
sparsification necessary to keep data at manageable levels
on-chip CM subtraction probably necessary (analogue pipeline contributes)
off-detector
FED features in
existing system
analogue pipeline using gate capacitance may still be possible in 130nm –not in finer processes
analogue circuitry throughout chip – harder to achieve supply noise rejection
sparsification leads to on-detector system complexity
extra de-randomising buffering required (another chip) to cope with varying trigger-to-trigger data volume
front-end timestamping
3
loss of external emulation capability (like in present simple synchronous system)
binary architecture – un-sparsified
much simpler (than digital APV)
particularly for pipeline and readout side
d ffast front
f
end
d and
d comparator
need
=> more power here
but no ADC power and much simpler digital
f
functionality
ti
lit will
ill consume lless – this
thi
architecture will be lowest power
binary architecture also compatible with
“t
“two-in-one”
i
” & cluster-width
l t
idth di
discrimination
i i ti
approach to track triggering layers
can retain system features we like
FE amp
comp.
digital pipeline
digital
MUX
vth
vth
off-chip
vth
O/P
driver
vth
slow control,
bias,
test pulse,
……
digital
g
digital
g
simpler synchronous system
no FE timestamping
data volume known, occupancy independent (no trigger-to-trigger variation)
un-sparsified binary is the option we are currently planning to implement this year
but
less diagnostics (can measure front end pulse shape on every channel in present system)
l
loss
off position
iti resolution
l ti
common mode immunity
4
binary front end amplifier
preliminary specifications and assumptions
high R
n-on-p sensor (signal current flows out of amplifier)
needs
d tto be
b ffast,
t peaking
ki ti
time ~ 20 nsec
needs to sink leakage current up to ~ 1 μA
iSIG + ILEAK
current preferred architecture (130 nm)
-ve
CPF
CF
CC
CSENS
VREF
to
comp.
RPF
NMOS I/P device
1/f corner lo
low eno
enough
gh (sim
(simulation)
lation) – apparently
apparentl no noise penalty
penalt
better connection to sensor for PSR (sensor bias decoupling and I/P FET source both at GND)
preamp feedback uses real resistor (not FET)
low Rpf (200k) allows DC leakage to be accommodated (1 μA -> 200 mV)
uses highest resistance technology in process (1k7/square poly
poly, +/
+/-20%)
20%)
Rpf.Cpf = 200k.100fF = 20 ns decay time constant of preamp (no pile-up)
200k contributes ~ 220e (for this shaping)
postamp provides gain
risetime provides integrating time constant
AC coupled to preamp (DC shift due to leakage decoupled)
O/P DC level set by Vref – defines DC level at following comparator input
will show some simulated performance pictures – all results at preliminary stage
5
binary FE pulse shape
0.85
pulse shape tuned to keep risetime ~ constant as
CSENSOR varies by increasing current in input FET
0 80
0.80
~ 170
1 0 – 200 mV
V pulse
l h
height
i h ffor 4 fC (2
(25,000
000 e))
0.75
=> power scales linearly with CSENSOR
Csensor
simulations
i l ti
show
h
noise
i < ~1000e
1000 ffor power ~ 200 μW
W
for CSENSOR ~ 6 pF
2pF
4pF
6pF
8pF
10pF
0.70
0.65
0.60
0.55
40
80
120
160
200
time [nsec]
trade off between power and noise
trade-off
thin sensors, long strips will need more
power to get less noise
300
1000
250
800
200
600
150
400
noise
power
200
0
0
2
4
6
Csensor [ pF]
8
10
100
50
0
12 6
power [uW
W]
0
FE power and noise
d
dependence
d
on CSENSOR
1200
noise [rms electro
ons]
volts
s
4 fC pulse shapes
Effects of leakage current
postamp output unaffected
0.8
preamp output shows DC shift across RPF
leakage
0
200 nA
400 nA
600 nA
800 nA
1000 nA
volts
0.6
1 μA leakage contributes ~ 440e noise to be added
in quadrature to amplifier noise
(short shaping time helps with parallel noise)
e.g. 900 (total amplifier for CSENSOR ~ 6 pF)
+ 440 (leakage)
= ~1000e total
0.4
0.2
CPF
0
100
200
300x10
CF
CC
-9
iSIG + ILEAK
time
-ve
e
CSENS
VREF
to
comp.
RPF
7
response to overload
0.4
0.2
0.0
-0
0.2
2
-0.4
-0.6
1.2
volts
volts
overload behaviour well-controlled
preamp input
low RPF beneficial
front end recovers from 4 pC signal and
sensitive to normal signals within 2.5 μs
08
0.8
=> no “APV-like” hips effect
preamp output
0.4
0.0
1.2
postamp output
1.0
volts
0.8
0.6
0.4
4 fC injected
0.2
0.0
0.0
0.5
1.0
1.5
2.0
2.5
time [usec]
4 pC injected
8
power supply rejection
10
power supply rejection at postamp output
to swept frequency sinusoidal waveform
on p
positive supply
pp y rail
0
bare response
100 ns filter
1 us filter
dB
BV
-10
-20
0 dBV = unity gain
-20 dBV = factor 10 rejection
bare response shows good rejection at
low frequency, peaking at ~10 MHz
-30
-40
AC p
preamp/postamp
pp
p coupling
p g together
g
with
opamp postamp gives good low f behaviour
-50
-60
2
10
10
3
10
4
10
5
6
10
10
frequency
CPF
iSIG + ILEAK
-ve
7
10
8
10
CC
CSENS
VREF
RPF
9
10
peaking at ~10 MHz (gain) due to coupling
through
g bias circuits
CF
can improve with realistic filtering, but would
prefer some rejection at all frequencies to
start with
10
to
comp.
needs further study
9
effect of preamp feedback resistor tolerance
using process resistor with +/- 20% tolerance (+/- 3 σ)
for RPF gives some pulse shape variation
0.9
=> noise will be affected
0.8
160k
200k
240k
911e
880e
857e
volts
s
e.g. for CSENSOR = 5 pF get:
0.7
RPF value
160k
200k
240k
06
0.6
~ +/- 3% noise variation
0.5
0
50
100
150
200
250
time [nsec]
10
power estimate
previously presented estimate for 130nm binary chip – non-sparsified readout
power/chan. [μW]
preamp/shaper
comparator
digital
fast serial output
p
180
20
60
230
490
20 ns, CSENSOR ~5pF
simulations
guess – loosely based on APV
guess for LVDS readout
g
still valid?
230 μW probably excessive for readout power
low voltage differential current output should take less
still think 0.5 mW / channel is a good target, hopefully conservative and safe number to use for
overall short strip chip power estimates
11
full prototype in 1st iteration
relative simplicity of binary option means could go for complete chip on timescale ~ 1year
could learn a lot sooner rather than later - would also provide collaborators with something to use
tho gh chip n
though
numbers
mbers will
ill be limited
choose front end most likely to suit SLHC (e.g. n-side readout)
(can still submit test structures for alternative front ends)
CBC (CMS Binary Chip)
FE amp
comp.
digital pipeline
could leave out some features
e.g. bias gen., test pulse, I2C I/F
digital
MUX
but should have main functionality:
vth
vth
off chip
off-chip
O/P
driver
vth
slow control,
bias,
test pulse,
……
vth
digital
digital
pipeline, pipe control logic, and mux.
trimDAC for comparator thresholds
differential O/P
output would be APV-like (i.e. header with
pipeline address) but digital (just hits)
20 Mbps => could combine 4 CBCs onto
one 80 Mbps GBT lane (simple mux)
=> 128 CBCs / GBT link
12
binary chip specifications (preliminary)
parameter
target spec.
justification/comment
noise
<1000 e for C < ~5 pF
does not include leakage current contribution
timewalk
copy Atlas ABCD spec.?
spec ?
supply rejection
>20 dB at any frequency?
factor 10 – maybe implemented externally (passive RC)
overload recovery
hip signals up to 4 pC
sensitive to normal signals < 2.5 usec.
power
0 5 mW / ch.
0.5
ch for C< ~5pF
5pF
leakage current
(DC sensor)
up to 1uA
should fail gracefully for higher current
signal polarity
-ve
conventional signal (&leakage) current flows out of amp
amp.
bond pads
wire
cheap, easy to prototype, but labour intensive assembly
power supplies
1.2 V analogue, digital
supplied separately
digital could be run at lower VDD to save power
pipeline
256
up to 6.4 usec
buffering (FIFO)
up to 32
triggered pipeline timeslices awaiting readout
+…
+…
13
summary
UK programme incorporates development of 130 nm readout chip for short strips
current plans are:
binary un-sparsified architecture
full-size
full
size chip on first iteration
front end amplifier architectures already under design
remainder of chip (digital) will begin soon
some specifications clear – others will develop over coming months – input invited
hope to submit this year (Autumn) - chips available ~ end of year
binary architecture already compatible with some of the track-trigger approaches under consideration
relative simplicity (simpler chip,
chip simpler system) should also allow to free-up
free up resources to help with
track-trigger solution (“two-in-one”, cluster-width, or stacked)
14