pcb design - IIT Bombay
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1 IIT Bombay PCB DESIGN Revised Aug’07 • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< 3 Main issues • Effects of parasitics • Power dissipation • Digital Ckts pcpandey@ee.iitb.ac.in • Artwork ♦♦ <<< 5 Capacitance • Tracks opposite each other - Run supply lines above each other - Don’t let signal line tracks overlap for any significant distance • Tracks next to each other - Increase the spacing between critical conductors - Run ground between signal lines Inductance To be considered in • High frequency analog circuits • Fast switching logic circuits • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>> 4 1.1 Parasitic Effects R & L of conductor tracks C between conductor tracks >>> Resistance of 35 µm thickness, 1 mm wide conductor = 5 mΩ/cm Change in Cu resistance with temperature = 0.4% / °C Current carrying capacity of 35 µm thickness Cu conductor (for 10 °C temperature rise): Width (mm) 1 4 10 Ic (A) 2 4 11 • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>> 6 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 1.2 Supply Conductors Unstable supply & ground due to • Resistive voltage drop • Voltage drop caused by track L and high freq. current • Current spikes during logic switching ⇒ local rise in ground potential & fall in Vcc potential ⇒ possibility of false logic triggering. pcpandey@ee.iitb.ac.in pcpandey@ee.iitb.ac.in IIT Bombay PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 ♠♠ R.S. Khandpur : Printed Circuit Boards : Design, Fabrication, and Assembly, McGraw-Hill, 2005. ♠♠ >>> IIT Bombay pcpandey@ee.iitb.ac.in 1.1 Parasitic effects 1.2 Supply conductors 1.3 Component placement • Analog Ckts C.F. Coombs : Printed Circuits Handbook , McGraw-Hill, 2001 Resistance Subtopics • General W.C. Bosshart, Printed Circuit Boards: Design and Technology, TMH, 1992 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 IIT Bombay IIT Bombay • GENERAL CONSIDERATIONS IN LAYOUT DESIGN ♠♠ 1.General Considerations in Layout Design 2.Layout Design for Analog Circuits 3.Layout Design for Digital Circuits 4. Artwork Considerations ♠♠ >>> PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 • Component interconnections • Physical accessibility of components Topics References pcpandey@ee.iitb.ac.in pcpandey@ee.iitb.ac.in Dr. P. C. Pandey EE Dept, IIT Bombay ♠♠ 2 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 IIT Bombay PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 Solutions • Conductor widths : W (ground) > W (supply) > W(signal) • Ground plane • Track configuration for distributed C between Vcc & ground • Analog & digital ground (&supply) connected at the most stable point ♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>> 7 IIT Bombay 1.3 Component Placement ♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< pcpandey@ee.iitb.ac.in • Minimize critical conductor lengths & overall conductor length • Component grouping according to connectivity • Same direction & orientation for similar components • Space around heat sinks • Packing density • Uniform • Accessibility for • adjustments • component replacement • test points • Separation of heat sensitive and heat producing components • Mechanical fixing of heavy components 9 ♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>> 10 2.2 HF Oscillator / Amplifier • Decoupling capacitor between Vcc & GND → Capacitive load on o/p • Reduce capacitive coupling between output & input lines • Vcc decoupling for large BW ckts. (even for LF operation) • Separation between signal & GND to reduce capacitive loading ♠♠ >>> 11 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 2.3 Circuits with High Power O/P Stage Resistance due to track length & solder joints → modulation of Vcc & GND and low freq. oscillations • Large decoupling capacitors • Separate Vcc & GND for power & pre- amp stages • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>> 12 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 2.4 High Gain DC Amplifier Solder joints → thermocouple jn Temp gradients → diff. noisy voltages • Temp.gradients to be avoided • Enclosure for stopping free movement of surrounding air pcpandey@ee.iitb.ac.in pcpandey@ee.iitb.ac.in IIT Bombay • General PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 IIT Bombay • Supply lines with sufficient width and high capacitive coupling to GND (use decoupling capacitors) • Supply line should first connect to high current drain ckt blocks • Supply line independent for voltage references • Supply and ground conductors • Signal conductors for reducing the inductive and capacitive coupling • Special considerations for • Power output stage circuits • High gain direct coupled circuits • HF oscillator /amplifier • Low level signal circuits pcpandey@ee.iitb.ac.in IIT Bombay pcpandey@ee.iitb.ac.in 2.1 Ground & Supply Lines • Separate GND (& Vcc) lines for analog & digital circuits • Independent ground for reference voltage circuits • Connect different ground conductors at most stable reference point 2. LAYOUT DESIGN FOR ANALOG CIRCUITS ♠♠ >>> PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 8 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 IIT Bombay pcpandey@ee.iitb.ac.in IIT Bombay PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 ♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>> ♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>> 13 2.5 Low Level Signal Circuits 14 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 IIT Bombay IIT Bombay PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 High -Z circuits If R » 1⁄ jw(Cxy+Cy) then coupled Vy = Va × [Cxy/(Cy+Cxy)] A) High impedance circuits - Capacitive coupling pcpandey@ee.iitb.ac.in pcpandey@ee.iitb.ac.in B) Low impedance circuits - Inductive coupling • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< 15 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 IIT Bombay ♠♠ >>> Low – Z Circuits • Voltage induced in ground loops due to external magnetic fields • Current caused in the low- Z circuit loop due to strong AC currents in nearby circuits • Analog Ckts • Digital Ckts pcpandey@ee.iitb.ac.in pcpandey@ee.iitb.ac.in • Avoid ground loops • Keep high current ac lines away from low level,low Z circuit loops • Keep circuit loop areas small • General • Artwork ♦♦ <<< Noise generated due to current spikes during logic level switching, drawn from Vcc and returned to ground Ground potential increases, Vcc decreases: improper logic triggering. Problem more severe for synchronous circuits. Severity of problem (increasing): CMOS, ECL, TTL. • Digital Ckts • Artwork ♦♦ <<< >>> pcpandey@ee.iitb.ac.in pcpandey@ee.iitb.ac.in • Internal spike: charging & discharging of transistor junction capacitances in IC ( 20 mA, 5ns in TTL) • External spike: charging & discharging of output load capacitance • Analog Ckts • Artwork ♦♦ <<< >>> 16 • Ground & supply line noise • Cross-talk between neighboring signal lines • Reflections : signal delays, double pulsing • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>> 18 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 IIT Bombay IIT Bombay 3.1 Ground & Supply Line Noise • General • Digital Ckts 3. LAYOUT DESIGN FOR DIGITAL CIRCUITS ♠♠ >>> 17 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 ♠♠ • Analog Ckts Main problems Vm= - (d/dt) ∫B dA ♠♠ • General PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 IIT Bombay ♠♠ • Increase separation between low level high Z line and high level line (decrease Cxy) • Put a ground line between the two (guard line) Example: Guard for signal leakage from FET output to input Solution for ground & supply noise • Decoupling C between Vcc & ground for every 2 to 3 IC’s : ceramic, low L cap. of 10 nf for TTL & 0.5 nF for ECL & CMOS •Stabilizes Vcc-GND (helps against internal spikes • Not much help for external spikes • Low wave impedance between supply lines (20 ohms): 5 to 10 mm wide lines opposite each other as power tracks • Ground plane : large Cu area for ground to stabilize it against external spikes • Closely knit grid of ground conductors (will form ground loops, not to be used for analog circuits) • Twist Vcc & GND line between PCBs ♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>> 19 • Analog Ckts pcpandey@ee.iitb.ac.in • Digital Ckts • Artwork ♦♦ <<< 21 pcpandey@ee.iitb.ac.in IIT Bombay PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 Summary of Layout Design Considerations (for 1.6 mm thickness, double sided boards) Logic Family: Signal–GND Zw (Ω Ω) TTL 100 - 150 ECL 50 - 100 CMOS 150 - 300 Signal line width (mm) 0.5 with gnd 1, no gnd 1 - 3 with gnd 0.5, no gnd Vcc -GND Zw (Ω Ω) <5 < 10 < 20 Vcc line (mm) GND line (mm) 5 Very broad (plane /grid) 2 to 3 Broad (plane/grid) 2 5 ♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>> 22 Conductor orientation Conductor Routing • Begin and end at solder pads, join conductors for reducing interconnection length. • Avoid interconnections with internal angle <60°. • Distribute spacing between conductors . • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>> 24 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 Solder Pads Hole dia • Reduce the number of different sizes. • 0.2 - 0.5 mm clearance for lead dia. pcpandey@ee.iitb.ac.in ♠♠ • General 4. ARTWORK RULES ♠♠ IIT Bombay √ CMOS (Z: 150 – 300 Ω) 0.5 mm signal line without GND plane. Gnd not close to signal lines. • Orientation for shortest interconnection length. • Conductor tracks on opposite sides in x-direction & ydirection to minimize via holes. • 45° or 30° / 60° orientation for turns. >>> pcpandey@ee.iitb.ac.in IIT Bombay × ECL (Z: 50 Ω) 1 - 3 mm signal line with GND plane, or nearby gnd conductor. PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 23 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 Conductor routing examples Caused by mismatch between the logic output impedance & the wave impedance of signal tracks. • Signal delay (low wave imp.) • Double pulses (high wave imp.) ♠♠ >>> IIT Bombay • General 3.3 Reflections TTL (Z: 100 - 150 Ω) 0.5 mm signal line with GND plane, 1 mm without GND plane. Signal lines between PCBs twisted with GND lines. Solutions • Reduce long parallel paths • Increase separation betw. signal lines • Decrease impedance betw. signal & ground lines • Run a ground track between signal lines ♠♠ IIT Bombay 3.2 Cross-talk • Occurs due to parallel running signal lines (ECL: 10cm,TTL: 20 cm, CMOS: 50 cm) • Problem more severe for logic signals flowing in opposite directions 20 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 pcpandey@ee.iitb.ac.in pcpandey@ee.iitb.ac.in IIT Bombay PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>> Solder pad • Annular ring width ≥ 0.5 mm with PTH ≈ 3 × hole dia without PTH • Uniformity of ring around the hole. • Conductor width d > w > d/3. ♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>> 25 pcpandey@ee.iitb.ac.in IIT Bombay PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 ♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>> IIT Bombay pcpandey@ee.iitb.ac.in ♠♠ • General • Analog Ckts • Digital Ckts Revised Aug’07 • Artwork EE Dept, IIT Bombay Dr. P. C. Pandey ♦♦ PCB DESIGN PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 <<< >>> 1 IIT Bombay pcpandey@ee.iitb.ac.in ♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< R.S. Khandpur : Printed Circuit Boards : Design, Fabrication, and Assembly, McGraw-Hill, 2005. C.F. Coombs : Printed Circuits Handbook , McGraw-Hill, 2001 2 >>> W.C. Bosshart, Printed Circuit Boards: Design and Technology, TMH, 1992 References 1.General Considerations in Layout Design 2.Layout Design for Analog Circuits 3.Layout Design for Digital Circuits 4. Artwork Considerations Topics PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 IIT Bombay pcpandey@ee.iitb.ac.in ♠♠ • General • Analog Ckts • Digital Ckts 1.1 Parasitic effects 1.2 Supply conductors 1.3 Component placement Subtopics ♦♦ <<< • Effects of parasitics • Power dissipation • Artwork • Component interconnections • Physical accessibility of components Main issues • GENERAL CONSIDERATIONS IN LAYOUT DESIGN PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 >>> 3 IIT Bombay pcpandey@ee.iitb.ac.in ♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< 4 >>> Resistance of 35 µm thickness, 1 mm wide conductor = 5 mΩ/cm Change in Cu resistance with temperature = 0.4% / °C Current carrying capacity of 35 µm thickness Cu conductor (for 10 °C temperature rise): Width (mm) 1 4 10 Ic (A) 2 4 11 Resistance R & L of conductor tracks C between conductor tracks 1.1 Parasitic Effects PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 IIT Bombay pcpandey@ee.iitb.ac.in ♠♠ • General • Analog Ckts • Digital Ckts To be considered in • High frequency analog circuits • Fast switching logic circuits Inductance • Artwork ♦♦ <<< 5 >>> • Tracks opposite each other - Run supply lines above each other - Don’t let signal line tracks overlap for any significant distance • Tracks next to each other - Increase the spacing between critical conductors - Run ground between signal lines Capacitance PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 IIT Bombay pcpandey@ee.iitb.ac.in ♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< 6 >>> • Conductor widths : W (ground) > W (supply) > W(signal) • Ground plane • Track configuration for distributed C between Vcc & ground • Analog & digital ground (&supply) connected at the most stable point Solutions • Resistive voltage drop • Voltage drop caused by track L and high freq. current • Current spikes during logic switching ⇒ local rise in ground potential & fall in Vcc potential ⇒ possibility of false logic triggering. Unstable supply & ground due to 1.2 Supply Conductors PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 IIT Bombay pcpandey@ee.iitb.ac.in ♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< • Uniform • Accessibility for • adjustments • component replacement • test points • Separation of heat sensitive and heat producing components • Mechanical fixing of heavy components • Minimize critical conductor lengths & overall conductor length • Component grouping according to connectivity • Same direction & orientation for similar components • Space around heat sinks • Packing density 1.3 Component Placement PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 >>> 7 IIT Bombay pcpandey@ee.iitb.ac.in ♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ • Supply and ground conductors • Signal conductors for reducing the inductive and capacitive coupling • Special considerations for • Power output stage circuits • High gain direct coupled circuits • HF oscillator /amplifier • Low level signal circuits <<< 2. LAYOUT DESIGN FOR ANALOG CIRCUITS PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 >>> 8 IIT Bombay pcpandey@ee.iitb.ac.in ♠♠ • General • Analog Ckts • Digital Ckts • Artwork • Supply lines with sufficient width and high capacitive coupling to GND (use decoupling capacitors) • Supply line should first connect to high current drain ckt blocks • Supply line independent for voltage references ♦♦ • Separate GND (& Vcc) lines for analog & digital circuits • Independent ground for reference voltage circuits • Connect different ground conductors at most stable reference point 2.1 Ground & Supply Lines PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 <<< >>> 9 IIT Bombay pcpandey@ee.iitb.ac.in 10 ♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>> • Decoupling capacitor between Vcc & GND → Capacitive load on o/p • Reduce capacitive coupling between output & input lines • Vcc decoupling for large BW ckts. (even for LF operation) • Separation between signal & GND to reduce capacitive loading 2.2 HF Oscillator / Amplifier PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 IIT Bombay pcpandey@ee.iitb.ac.in 11 ♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< Resistance due to track length & solder joints → modulation of Vcc & GND and low freq. oscillations • Large decoupling capacitors • Separate Vcc & GND for power & pre- amp stages >>> 2.3 Circuits with High Power O/P Stage PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 IIT Bombay pcpandey@ee.iitb.ac.in ♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ • Temp.gradients to be avoided • Enclosure for stopping free movement of surrounding air Solder joints → thermocouple jn Temp gradients → diff. noisy voltages 2.4 High Gain DC Amplifier PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 <<< >>> 12 IIT Bombay pcpandey@ee.iitb.ac.in ♠♠ • General • Analog Ckts • Digital Ckts • Artwork B) Low impedance circuits - Inductive coupling A) High impedance circuits - Capacitive coupling 2.5 Low Level Signal Circuits PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 ♦♦ <<< >>> 13 IIT Bombay pcpandey@ee.iitb.ac.in ♠♠ • General • Analog Ckts • Digital Ckts • Increase separation between low level high Z line and high level line (decrease Cxy) • Put a ground line between the two (guard line) Example: Guard for signal leakage from FET output to input If R » 1⁄ jw(Cxy+Cy) then coupled Vy = Va × [Cxy/(Cy+Cxy)] High -Z circuits PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 • Artwork ♦♦ <<< >>> 14 IIT Bombay pcpandey@ee.iitb.ac.in 15 ♠♠ • General • Analog Ckts • Digital Ckts • Avoid ground loops • Keep high current ac lines away from low level,low Z circuit loops • Keep circuit loop areas small Vm= - (d/dt) ∫B dA • Artwork ♦♦ <<< >>> • Voltage induced in ground loops due to external magnetic fields • Current caused in the low- Z circuit loop due to strong AC currents in nearby circuits Low – Z Circuits PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 IIT Bombay pcpandey@ee.iitb.ac.in ♠♠ • General • Analog Ckts • Digital Ckts • Artwork • Ground & supply line noise • Cross-talk between neighboring signal lines • Reflections : signal delays, double pulsing Main problems ♦♦ <<< 3. LAYOUT DESIGN FOR DIGITAL CIRCUITS PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 >>> 16 IIT Bombay pcpandey@ee.iitb.ac.in 17 ♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>> Ground potential increases, Vcc decreases: improper logic triggering. Problem more severe for synchronous circuits. Severity of problem (increasing): CMOS, ECL, TTL. • Internal spike: charging & discharging of transistor junction capacitances in IC ( 20 mA, 5ns in TTL) • External spike: charging & discharging of output load capacitance Noise generated due to current spikes during logic level switching, drawn from Vcc and returned to ground 3.1 Ground & Supply Line Noise PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 IIT Bombay pcpandey@ee.iitb.ac.in 18 ♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>> • Decoupling C between Vcc & ground for every 2 to 3 IC’s : ceramic, low L cap. of 10 nf for TTL & 0.5 nF for ECL & CMOS •Stabilizes Vcc-GND (helps against internal spikes • Not much help for external spikes • Low wave impedance between supply lines (20 ohms): 5 to 10 mm wide lines opposite each other as power tracks • Ground plane : large Cu area for ground to stabilize it against external spikes • Closely knit grid of ground conductors (will form ground loops, not to be used for analog circuits) • Twist Vcc & GND line between PCBs Solution for ground & supply noise PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 IIT Bombay pcpandey@ee.iitb.ac.in 19 ♠♠ • General • Analog Ckts Solutions • Reduce long parallel paths • Increase separation betw. signal lines • Decrease impedance betw. signal & ground lines • Run a ground track between signal lines • Digital Ckts • Artwork ♦♦ <<< >>> • Occurs due to parallel running signal lines (ECL: 10cm,TTL: 20 cm, CMOS: 50 cm) • Problem more severe for logic signals flowing in opposite directions 3.2 Cross-talk PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 IIT Bombay pcpandey@ee.iitb.ac.in 20 ♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>> CMOS (Z: 150 – 300 Ω) 0.5 mm signal line without GND plane. Gnd not close to signal lines. ECL (Z: 50 Ω) 1 - 3 mm signal line with GND plane, or nearby gnd conductor. TTL (Z: 100 - 150 Ω) 0.5 mm signal line with GND plane, 1 mm without GND plane. Signal lines between PCBs twisted with GND lines. Caused by mismatch between the logic output impedance & the wave impedance of signal tracks. • Signal delay (low wave imp.) • Double pulses (high wave imp.) 3.3 Reflections PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 IIT Bombay pcpandey@ee.iitb.ac.in 21 • Digital Ckts 5 Very broad (plane /grid) Vcc line (mm) GND line (mm) • Analog Ckts <5 Vcc -GND Zw (Ω Ω) • General 0.5 with gnd 1, no gnd Signal line width (mm) ♠♠ TTL 100 - 150 Logic Family: Signal–GND Zw (Ω Ω) • Artwork 2 to 3 Broad (plane/grid) < 10 ♦♦ 1 - 3 with gnd ECL 50 - 100 (for 1.6 mm thickness, double sided boards) 2 5 <<< < 20 >>> 0.5, no gnd CMOS 150 - 300 Summary of Layout Design Considerations PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 IIT Bombay pcpandey@ee.iitb.ac.in ♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< • Begin and end at solder pads, join conductors for reducing interconnection length. • Avoid interconnections with internal angle <60°. • Distribute spacing between conductors . Conductor Routing • Orientation for shortest interconnection length. • Conductor tracks on opposite sides in x-direction & ydirection to minimize via holes. • 45° or 30° / 60° orientation for turns. Conductor orientation 4. ARTWORK RULES PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 >>> 22 IIT Bombay pcpandey@ee.iitb.ac.in ♠♠ • General Conductor routing examples • Analog Ckts • Digital Ckts × PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 • Artwork ♦♦ √ <<< >>> 23 IIT Bombay pcpandey@ee.iitb.ac.in ♠♠ • General • Analog Ckts • Digital Ckts • Artwork Solder pad • Annular ring width ≥ 0.5 mm with PTH ≈ 3 × hole dia without PTH • Uniformity of ring around the hole. • Conductor width d > w > d/3. Hole dia • Reduce the number of different sizes. • 0.2 - 0.5 mm clearance for lead dia. Solder Pads PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 ♦♦ <<< >>> 24 IIT Bombay pcpandey@ee.iitb.ac.in ♠♠ • General • Analog Ckts • Digital Ckts PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 • Artwork ♦♦ <<< >>> 25
