Etch Products Business Group
Integrated Dual Damascene Etching for
65nm Technology and Beyond
Yan Ye, Ph.D.
Dielectric Etch Technology Development
Applied Materials,
PEUG Meeting, Aril 13, 2004
Etch Products Business Group
Content
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Trends in dual damascene development
Integrated dual damascene etch process
Challenges for integrated etch process.
Feasibility of integrated dual damascene etch process.
Integrated etch process is one of major challenges for dual damascene
etch applications of 65nm technology and Beyond
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Low-K Dual Damascene Trends Observed
I-line
4.0
USG
FSG/SiN
3.5
k-value
248nm Litho
193nm Litho
OSG-I/SiC-I
3.0
157nm Litho?
OSG-II/SiC-II
2.5
Porous OSG/SIC-II
2.0
1.5
250nm
180nm
90nm
130nm
Technology Node
65 nm
45 nm
Trench First
Via First
New DD structure?
Via first
Trench first
Via First
Both low-k material and lithography are the driving forces
for new dual damascene schemes
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BARC Etchback Approach
Pre
M2 etch
Ash+ Barrier open
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Dual Damascene with Full-Filled BARC
Pre
BARC etch
M2 etch 2
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Dual Damascene with Bi-layer Resist
Pre
Mask etch
Ash
Trench etch
Barrier open
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Why Integrated Etch Process is Needed
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Low-K Dual Damascene Process
M1 Trench Etch
BD Via Etch
BD DD 2nd Trench etch and Blok open
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Enabler: Cycle Time Advantage
Representative Fab Layout
Lithography
Traditional
Etch Scheme
Trench Etch
PR Strip
Dip
Barrier Open
Wet
Dip
Dip
Wet
Dip
44 tools
tools // ~4.5
~4.5 hrs
hrs cycle
cycle time
time
11 tool/~30min
tool/~30min
All-in-One
Wet
Dip
Cu Deposition
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Challenges Faced For Integrated Etch Process
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Large Operation Window is Required for an
All-in-One Dual Damascene Process
BD Via Etch
BD Trench Etch
PR Strip
BLOκ
κ Open
Etch of Diverse Low-κ Materials and Integration
Schemes is Required
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Fast transition between steps is Required for
an All-in-One Dual Damascene Process
500O2/10-900mT/
100-4500Wb/0-2000Ws
Oxygen Emission
intensity (774nm)
4000
3000
Step 1
2000
Step 2
Step 3
Step 4
Step 5
Step 6
Step 7
Step 8
1000
0
-1000
-2000
0
50
Vrf measured from
Cathode (Volts)
100
Time (s)
150
200
250
Etch Products Business Group
All-in-1 Process Requires Tunability for Both Charged Species
and Neutral Species Distribution in Each Step
Effect of Charged Species
Distribution Tuning
6000
∆CD: 3 nm
ER (A/min)
Across-Wafer Etch
Rate Profile
∆CD [nm]
Center
3000
CTR
Effect of Neutral Species
Distribution Tuning
EDGE
CTR
EDGE
CTR
EDGE
Edge
0
-5
-10
-15
-20
-25
-30
-35
-40
0.50
Ctr
Edge
1.00
1.50
2.00
∆CD: 32 nm
Center-Fast
~1.% unif.
Center
2.50
Edge
Edge- Fast
Independent
Independent control
control of
of both
both charged
charged and
and neutral
neutral species
species distribution
distribution is
is necessary
necessary to
to
achieve
achieve complete
complete tunability
tunability of
of etch
etch rate
rate uniformity
uniformity and
and profile/CD
profile/CD uniformity
uniformity
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Integrated Etch Process Requires Process Transferable:
All-in-1 via etch comparison with 2-in-1 etch
2-in-1
PR Strip in a clean chamber
Main etch
Over etch
TOP
CTR
BTM
CTR
CTR
TOP
TOP
All-in-1
Etch, PR Strip, chamber clean
TOP
CTR
Identical
Identical process
process performance
performance is
is required
required
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Feasibility of Integrated Etch Process
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Integrated BD Dual Damascene M2 Trench Etch
Etch
Insitu Ash
BLoK Open
All-in-1
All-in-1 BD
BD Dual
Dual Damascene
Damascene Trench
Trench etch
etch is
is Demonstrated
Demonstrated
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All-in-1 Low-K Film Integrity Repeatability Test:
BD I M2 etch profile after ash & HF dip
Wafer #1
Wafer #200
Wafer #1000
Ash
HF Dip
No Low-k film integrity change in 1000 wafer burn-in
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2000 Wafer Burn-in Result for All-in-1 BD M2 Trench:
Process and Particle Performance
0
500
1000
1500
2000
Cycle Wafer
Count
0
500
1000
1500
2000
Post PM
Fence (A)
U-loading (%)
ED (A)
NonU(%)
0
-2.6
3180
3.3
0
-1.6
3120
1.8
0
-2.9
3180
2.9
0
0.3
3080
2.4
0
-0.6
3100
1.1
0
-2.1
3100
2.4
Post PM
15
10
10
5
5
0
0
75
0
10
00
12
50
15
00
17
50
20
00
PM
20
50
15
50
0
20
0
20
25
10
0
20
0
30
0
40
0
Particle Adder
RF-on Particle Chart
The average particle
adders are 3.9 and 2.9 for
>.12um and >0.20um
Wafer count #
>.12um
>10um
>.12um
>10um
Process and particle performance are stable through
2000 wafers burn-in.
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3 Level Metal Copper BD Interconnect Built Through
Via 2
Integrated Etch process
Via1
3 level Copper Interconnect
M3
V2
M2
V1
M1
Stacked
Via
Via resistance (Ω
Ω)
3 level Copper Interconnect with 95-99% yield 10 Million via
chain as well as stacked 1 Million Via Chain
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All-in-1 CDO (k~2.3) Trench Etch with 193nm PR
Ctr
FICD 93nm
1σ=2.8nm
Edge
DICD 109nm
1σ=2.8nm
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Integrated Porous OSG (ELK) Etch
SiC 2.0K
SiO 0.5K
SiC 1.0K
SiC 1.0K
Porous Silica 4.0K
Porous Silica 4.0K
M 1(Cu)
Oxide
All-in-1 Result
Demonstrated
Demonstrated all-in-1
all-in-1 capability
capability
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Summary
! Requirement for integrated dual damascene etch processes
has been observed. It requires new etch tool with large
process window, better tunability for both charge species
and neutral species in each step, smooth step transition,
effective clean without low-k film damage, and so on.
Feasibility to achieved required etch performance for
several integrated dual damascene scheme has been
demonstrated.
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