minimizing emi effects during pcb layout of z8/z8plus circuits

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APPLICATION NOTE
MINIMIZING EMI EFFECTS
DURING PCB LAYOUT OF
Z8/Z8PLUS CIRCUITS
INTRODUCTION
The Z8/Z8Plus families have redefined ease-of-use by
being the simplest 8-bit microcontrollers to program.
Combined with low-cost and extensive device variety, a
complete solution is easily implemented. PCB designs using
the Z8/Z8Plus must follow several layout guidelines.
Although some high-frequency effects are covered, discussion has been limited to the following:
•
The Z8/Z8Plus device operation at low frequency ranges
(0-20 MHz)
• The use of fairly long signal rise times (10-20ns)
The mechanical and thermal requirements of PCB boards
are not covered but should be known and implemented in
a design. The complexity of these circuits are fairly low.
Complex and higher-frequency circuits are left to those
users more knowledgeable in PCB layout. For a more indepth understanding of PCB layout, see the references at the
end of this application note. Many PCB layout books and
classes are also available.
THE LAYOUT DESIGN PROCESS
Creating Good Layouts
To create a good layout, evaluate potential problems early
in the design process. The goal is to reduce EMI effects from
the layout design portion of the application design process.
Most unwanted effects can be eliminated early in the layout
design by following these guidelines, which are the focus
of this application note.
Guidelines For Reducing EMI In PCBs
1. Identify the quiet and noisy I/O portions of the circuit.
2. Implement a low impedance power and ground distribution network, and analyze them for possible radiated
and susceptibility effects.
3. Plan for good EMI performance by minimizing shared
impedance and routing signal paths directly over their
return.
4. Minimize conductor inductance to decrease noise voltage
swing.
5. Implement ESD and EFT protection during layout.
These items are listed in order of importance and are interrelated. For example, implementing a good power and
ground distribution network relies on its underlying impedance. Although each is interrelated, use these guidelines in
sequence. For example, understanding the quiet and noisy
portions of the circuit helps the user layout the power and
ground network.
NOISY VS. QUIET CIRCUIT AREAS
Identifying Noisy Circuits
In a typical application, there are noisy and quiet portions
of a circuit. A good first step is to understand the noisy and
quiet areas on the board. When this is known, the PCB
designer can dedicate portions of the board for these circuits
AN002000-Z8X1099
and implement noise reduction techniques. When referring
to the terms noise or EMI (Electromagnetic Interference),
it usually infers a transfer of unwanted signals into a circuit
(Voltage or Current).
1
Application Note
Minimizing EMI Effects During PCB Layout of Z8/Z8Plus Circuits
For EMI or electrical noise to interfere with the operations
of a circuit, there has to be a SOURCE of interference, a
RECEPTOR for the interference, and a PATH which
couples the Source and Receptor. Figure 1 shows a graphical representation of the transfer of EMI.
Conducted
Coupling
Path
Source
(Emitter)
Victim
(Receptor)
Radiated
Figure 1. Model of EMI
This application note examines intra-system noise. Intrasystem noise occurs when the sources, victims, and coupling
paths are entirely within one system, module, or PCB. Noise
emissions can be conducted by power lines into systems or
systems can conduct noise emissions onto power lines. Noise
emissions can also radiate into the internal circuit space and
internal circuits can also be susceptible to radiated noise. For
example, a PCB ground loop makes an antenna that effects
other portions of the circuit.
As illustrated in Figure 1, radiated noise can be coupled into
a system and appear as conducted noise. This noise causes
logic gates to trip at the wrong voltage level or sensitive
analog circuits to have incorrect voltage levels. Two main
coupling mechanisms from parallel conductors on the PCB
board can increase noise. Parallel conductors can couple a
signal onto each other if the signal on one conductor is a
time-varying signal. (A time-varying signal has electromagnetic fields that can couple on the other conductor as
defined in Maxwell’s equations). The conductors are not
physically connected but are electromagnetically
connected, this is known as the transmission line effect. On
the Schematic a capacitor or transformer appears to be
connected between the two conductors. In Figure 2, the
voltage is coupled to the other parallel conductor by mutual
inductance, which appears as a wound transformer.
Figure 2. Circuit Model for Inductive Coupling
Figure 3. Circuit Model for Capacitive Coupling
2
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Application Note
Minimizing EMI Effects During PCB Layout of Z8/Z8Plus Circuits
Figure 3 demonstrates stray capacitance. Stray capacitance
results from capacitance between conductors that are in
close proximity.
As the application frequency and rise time increase, the
parameter model describes inductive and capacitive
coupling (See Figure 4).
R
C
L
G
C
R
G
L
Figure 4. Transmission Line Model
The two modes of interference are: differential-mode interference and common-mode interference. Differential-mode
is desirable and common-mode is an EMI problem. Figure
5 shows a differential-mode signal. The fields generated by
differential currents oppose each other and nearly cancel
out; therefore, little interference is caused.
IDM
VDM
Differential
Mode
Source
Load
IDM
Figure 5. Differential Mode Interference with Canceling Currents
In Figure 6, the common mode source adds noise to the
differential mode signals. This noise is usually coupled
from high-frequency currents affecting the PCB and wiring
inductance, causing the wiring to operate as a radiating
mono-pole antenna. These common mode signals are not
useful, and are the major cause of radiated EMI from cables,
PCB traces, and wiring. The wiring inductance is a signif-
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icant problem and must be tightly controlled. A major
source of common mode noise is clocks and repetitive I/O.
Figure 7 shows the resulting peak current from a clock
source. This peak current may be coupled onto adjacent
conductors because it is a time-varying field. CMOS logic
has a low average current but high peak currents with a high
frequency repetition rate.
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Application Note
Minimizing EMI Effects During PCB Layout of Z8/Z8Plus Circuits
1/2 VDM
L wiring
Load
1/2 VDM
VCM
L wiring
Common
Mode
Source
Figure 6. Common Mode Interference with Increased Noise Voltage
Repetitive CMOS Signal or Clock
Resultant current
V
I
+
8
Time
Time
Figure 7. Resulting Current from a CMOS Clock or Repetitive I/O
Having the basic understanding of how EMI can be coupled,
its paths, and its conduction modes, several circuit areas are
now suspect and should be examined during layout. Some
of the circuitry to be examined are listed below with placement suggestions1:
•
Separate Digital Interface circuitry (higher speed,
busses) from I/O circuitry (lower speed). Physically
isolate and route on separate connectors when possible.
•
Locate oscillators and clock circuits near the center of the
printed circuit board. This location minimizes coupling to
I/O runs and places the higher-frequency sources in the
center of the power and ground distribution system.
•
Locate memory circuits away from I/O circuits and each
respective run, preferably near the center of the printed
circuit board. These circuits draw high current transients
during switching.
4
•
Separate the analog from the digital portions of the
circuit. Coupling may occur from the digital portions to
analog lines, increasing noise.
•
Place the microcontroller clock first on the circuit board.
At low frequency, the microcontroller clock is one of the
nosiest areas of the circuit board.
If a clock run is added to drive other portions of a two-sided
board, follow these guidelines:
•
Add a ground run shadow to the backside (opposite) of
the board. This is the most effective noise-reduction
method.
– Where this is not possible, the ground run should
be adjacent to the circuit board on the same side.
– Where the clock run is adjacent, a second ground
is recommended, causing clock runs between two
ground runs.
When the noisy and quiet areas are identified, partition them
on the circuit board to reduce the coupled noise.
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Application Note
Minimizing EMI Effects During PCB Layout of Z8/Z8Plus Circuits
POWER AND GROUND DISTRIBUTION
Power and Ground Routing
Separating planes for power and ground distribution is the
most effective routing method. This requires a multi-layer
board. Power and ground planes almost become one at high
frequencies. When not using planes, follow this rule: the
closer the ground is to the power, the less EMI noise is
created. Power traces should be run as close as possible to
the ground traces. Power/Ground type effectiveness by
layer is listed in Table 1.
Table 1. Power/Ground Layers Ranked by Effectiveness (Higher Number = Worse)
Increasing Inductance (L)
Lowest L
Effectiveness Rank
1
Description
Multi-layer (VCC Plane and GND Plane)
.
2
2-sided (VCC trace over GND Plane)
.
3
2-sided (VCC trace over GND Trace)
.
4
1-sided (VCC trace parallel to GND Trace)
Highest L
5
Random wiring loop
The importance of proximity of the power and ground traces
is illustrated in Table 1. Route the power and ground traces
as close as possible. On a single-layer board, the return path
should be routed side-by-side with the power.
accuracy is needed, the value can be calculated from this
simple formula:
I =C
Decoupling Power
The board power supply connection needs to be decoupled
and must also have decoupling capacitors for each digital
device. The digital device capacitors provide two primary
functions: (1) supply sufficient switching transient current,
preventing power supply droop, and (2) decouple
conducted noise out of the system. These guidelines should
be followed in decoupling power:
•
For power and ground distribution, it is recommended
that the incoming power and ground signals terminate at
the input decoupling network at the printed circuit board
connector. This termination should occur prior to
connecting to the respective internal planes, which
usually happens at the printed circuit board connector.
Decouple power by using a 0.1 to 1.0µF Tantalum
capacitor. This capacitor essentially bypasses highfrequency noise to ground
•
Minimize the impedance and radiation loop of the
coupling capacitor by placing each adjacent to the critical circuit. Because of long capacitor lead lengths,
capacitors can become self-resonant at higher frequencies. Shorten capacitor leads and place capacitors as
close to the board as possible, preventing self-resonance.
•
Place adequate power-to-ground decoupling capacitors
throughout individual digital devices. A standard value
for these capacitors is 0.1µF for each device. If more
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dV
dt
⇒C = I
dt
dV
For example, if the maximum VCC droop that is tolerable is
0.1V, the switching time is 4nS, and the current that needs
to be supplied is 750mA, then the following formula applies:
C = 750mA ×
4nS
= 30nF
0.1V
This equation illustrates that a sufficient value for a standard
value decoupling capacitor is 0.047µF or greater.
Example Power/Ground Networks
The PCB industry document that provides standards for
PCB’s and PCB assembly is the “ANSI/IPC-D-275”2. This
document was created by the Institute for Interconnecting
And Packaging Electronic Circuits and contains a section
on power and ground distribution. Figures 8–10 are from
this publication and are examples of power/ground layouts.
Figure 8 is the worst layout, and Figure 10 is the best. Figure
8 shows adjacent signal return paths and high inductance
that leads to crosstalk. Figure 9 shows a better layout that
2.
“Design Standard for Rigid Printed Boards and
Rigid Printed Board Assemblies,” ANSI/IPC-D-275,
September 1991, The Institute for interconnecting and
Packaging electronic circuits, Lincolnwood, Ill.
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Application Note
Minimizing EMI Effects During PCB Layout of Z8/Z8Plus Circuits
further reduces power distribution, logic-return impedances, conductor crosstalk, and board radiation. Figure 10
illustrates the most effective layout for EMI reduction.
However, it shows the trade-off between the number of
adjacent returns and the area of layout.
Figure 8. Poor Voltage/Ground Distribution Layout Concept (From ANSI/IPC-D-275)
Figure 9. Acceptable Voltage/Ground Distribution Layout Concept (From ANSI/IPC-D-275)
6
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Application Note
Minimizing EMI Effects During PCB Layout of Z8/Z8Plus Circuits
Figure 10. Preferred Voltage/Ground Distribution Layout Concept (From ANSI/IPC-D-275)
Minimizing Power and Ground Network
Impedance
A critical parameter to observe while laying out the power
and ground network (along with signal runs) is the characteristic impedance of the conductor pairs. In most layouts,
three configurations of the conductors are used: parallel
strips, strips over ground plane, and strips side-by-side.
Table 2 shows the impedance of each configuration and a
a cross-section of the board, looking into the conductors.
The impedance varies between the parallel strips and strip
over ground plane compared to side-by-side configurations.
causes unwanted noise when a side-by-side configuration
is used for a long run on a board and the impedance is not
carefully watched.
The type of material used in board manufacturing can minimize conductor pair impedance. This directly effects the
characteristic impedance because of the different εR of the
material where εR is the dielectric constant of the material.
Two of the three conductor configurations in Table 2 can
be effected by the material used in the manufacture of the
PCB board. This is seen more clearly in Table 2, where the
characteristic impedance calculation equations are shown
for the three impedances.
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 377  h 

Z 01 = 
where W > 3h, h > 3t
 ε  W 
 R
 377  h 

Z 02 = 
where W > 3h
 ε  W 
 R
 377   D
 ln + D 2 − 1 where W >> t
Z 03 = 



 εR  W
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Application Note
Minimizing EMI Effects During PCB Layout of Z8/Z8Plus Circuits
It is important to know the εR properties of the material used in
board manufacturing to understand the impedance variations.
The characteristic impedance must be tightly controlled to
keep noise margins at a satisfactory level.Moreover, the characteristic impedance can vary widely during manufacturing.
A significant voltage level transient can be generated from
a relatively high impedance. For example, examine a power
bus using a side-by-side conductor routing method and TTL
logic. Using the 25Ω (or higher) impedance, and knowing
that TTL logic requires a current of approximately 16mA,
means that dV=0.016 X 25Ω = 400 mV. This 400mV is equal
to the noise immunity level of the TTL logic. Always determine if manufacturing can meet your design goals.
Table 2. Characteristic Impedance of Different Conductor Pairs
W
D
h
t
W
t
h
Z02
Z01
8
W
Z03
W/h or D/W
Parallel Strips
Strips Over Ground Plane
Strips Side by Side
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.5
1.7
2.0
2.5
3.0
3.5
4.0
5.0
6.0
7.0
8.0
9.0
10.0
12.0
15.0
20.0
25.0
30.0
40.0
50.0
377
281
241
211
187
169
153
140
112
99
84
67
56
48
42
34
28
24
21
19
17
14
11.2
8.4
6.7
5.6
4.2
3.4
377
281
241
211
187
169
153
140
112
99
84
67
56
48
42
34
28
24
21
19
17
14
11.2
8.4
6.7
5.6
4.2
3.4
N/A
N/A
N/A
N/A
N/A
0
25
34
53
62
73
87
98
107
114
127
137
146
153
160
166
176
188
204
217
227
243
255
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Application Note
Minimizing EMI Effects During PCB Layout of Z8/Z8Plus Circuits
PLAN FOR GOOD EMI PERFORMANCE
Minimizing Shared Impedance
A common circuit problem is shared impedance. This
contributes to incorrect voltage levels. Shared impedance
increases the noise sensitivity from transient switching
current or radiated EMI. For example, the effective inductance from the power connector to the chip power has a
specific inductance, but the inductance through the same
connection to the I/O can be different. It is this inductance
that causes voltage variations along this connection and also
causes a voltage reference at one point to be different from
another point. See Figure 11.
L1
L2
Power Connector
(VCC)
Vcc
R
"Shared Impedance"
Z8/Z8+
I/O
Gnd
NPN
Ground Connection
(GND)
L3
a.
L4
Figure 11. Characteristic Impedance of Different Conductor Pairsa
Gerald L. Ginsberg, “Printed Circuits Design”, pp. 82
As shown in Figure 11, the ground at the chip can be
different from the ground at the emitter of the NPN BJT.
The same is true for the chip power. A more effective
configuration is shown in Figure 12. A common connection
point has reduced shared impedance. This connection
scheme can reduce shared impedance and still allow large
line inductance values. Controlling line inductance is
described later in this document.
Power Connector
(VCC)
Vcc
R
Z8/Z8+
NPN
Gnd
I/O
Ground Connection
(GND)
Figure 12. Better Connection to Reduce Shared Impedance
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9
Application Note
Minimizing EMI Effects During PCB Layout of Z8/Z8Plus Circuits
Input
DIGITAL ISLAND
J1
1
R1
2
C1
JP1
HF_FILTER
RESISTOR
OUTPUT ISLAND
C2
2
1
J2
2
1
U1A
HEADER 1
J3
Output
2
RC_OR_FERRITE
1
2
1
C3
7407
HF_FILTER
U2
ESD ISLAND
POWER
JP2
C4
C5
C6
2
1
Y1
1
HEADER 2
1
2
3
4
5
6
7
8
9
P24
P25
P26
P27
Z86E08
VCC
XTAL2
XTAL1
P31
P32
P23
P22
P21
P20
GND
P02
P01
P00
P33
18
17
16
15
14
13
12
11
10
J4
RESONATOR
2
RC_OR_FERRITE
11
C7
U3A
2
+
3
1
-
JP3
2
1
HEADER 3
7
OP09
ANALOG ISLAND
Figure 13. Schematic for Example PCB Board
Using a Star Ground and Islands
Checklist For Improved EMI Performance
Using a dedicated ground run for each path reduces some
EMI problems. This is difficult to implement, therefore
designers need an additional step to create a surrounding
ground plane. This ground plane is used to surround and
isolate noisy circuit parts. This is effective on single-sided
PCBs, but it is more effective as the layers increase; then a
true, continuous ground plane becomes possible.
The following checklist helps the PCB designer resolve
most EMI design problems.
In boards with two or more layers, this continuous ground
plane can be further divided into partitioned islands with the
ground connections from each island joined at a star ground.
This reduces the return impedance and allows for adjacent
routing of the signal and return paths. See Figure 14 for an
example of a 2-layer board using a Z8. The bottom layer is
used for ground islands and the top layer is the routing layer
and component side. Figure 13 is the schematic for Figure 14.
The high-frequency filters and RC/Ferrite beads are used
in various parts of the circuit, preventing noise from
entering one part of the board from another. The four islands
are: ESD, Digital, Analog, and Output. The arrows on the
PCB board in Figure 14 indicate the return current flow from
the four islands. The side of JP2, which does not have a trace,
is connected to the ground plane. Note the return current is
separated into pathways returning to ground.
10
•
Segregate digital circuits and analog circuits.
•
Follow common impedance layout procedures when
planning grounding and power distribution.
•
Connect the oscillator directly to the Z8/Z8Plus GND
pin, using a short, direct trace. Do not use a shared trace.
•
Use a ceramic-bypass capacitor (.01 to 0.1µF) at the
Z8/Z8Plus’s VCC and GND pin connection. Use short
leads and short traces.
•
Locate electrolytic capacitors on VCC at the power
connector before splitting analog and digital VCC.
•
Assign each digital IC its own decoupling capacitor, and
place them in close proximity.
•
Separate digital and analog functions in external packages whenever possible.
•
Use short traces and small loops for driven digital
outputs.
•
Add filtering for noisy repetitive output signals. Use a
series damping resistor (22 to 47Ω) or inductor placed at
the output pin.
AN002000-Z8X1099
Application Note
Minimizing EMI Effects During PCB Layout of Z8/Z8Plus Circuits
•
Use EMI ferrite beads to replace less effective devices
such as series R or L. This reduces I/O signal interference. Use beads specifically designed for EMI suppression, placing output signal beads at the driving pin, and
input beads at the input connector.
•
Locate pull-up resistors at the corresponding signal
driving output pin, not at the input pin. This minimizes
loop area.
•
Use small loop areas for good ESD and external EMI
immunity. This minimizes ESD ground input problems.
•
Locate an ESD ground at the I/O connector with an ideal
length-to-width ratio of 3:1. Do not exceed a 5:1 ratio.
•
Terminate the ESD ground to the chassis ground. If no
chassis ground exists, terminate the ESD ground to the
power input ground at the connector.
AN002000-Z8X1099
•
Use a 1-10nF decoupling capacitor right at the device
connector. TConnect the ground to ESD ground. Use a
series R device to limit EDS current
•
Use ESD techniques for improved OTP-mode pin
operation:
– Minimize circuit loop areas and provide diode
clamps to VCC.
– Place a clamping diode on the Z8/Z8Plus, EPM,
OE, CE and VPP. Place these diodes close to the
Z8 to reduce induced noise. Verify correct pin
placement by checking pin diagram in the product
specification.
•
Terminate unused inputs. This reduces noise coupling
that affects device performance.
11
Application Note
Minimizing EMI Effects During PCB Layout of Z8/Z8Plus Circuits
Digital Island
Output Island
Analog Island
ESD Island
Figure 14. Sample PCB Board From Circuit Schematic
12
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Application Note
Minimizing EMI Effects During PCB Layout of Z8/Z8Plus Circuits
MINIMIZING LINE INDUCTANCE
Understanding Parasitic L
Controlling trace inductance (L) is critical in reducing noise
voltage swing. In Figure 15, parasitic L is measured by
varying connections and trace widths. This experiment
setup is used in several designs and shows the differences
in traces and connections.
Figure 15. Parasitic L Measurement Setupa
a.
Gary Cummings, “System EMI, ESD & EFT Workshop”, December 1997
Figure 15 illustrates:
•
The connection between C and D simulates a capacitor
with 0 internal inductance, connected on a 2-sided PCB.
•
Measurements are made with a dI/dt generator. I=0 to
40A and dI/dt rate is 100A / second.
•
Measuring induced VL between A to B and C to D
permits calculation of L= VL / (dI/dt).
PCB Signal Routing Effects Inductance
The designs examined using the experiment setup described
in Figure 15 are shown in Figure 16. In this figure, the trace
widths, trace placements, and connections have been varied
to show the varying effects of inductance on the layout
design.
Figure 16. Different Designs Used in Measuring Parasitic Inductancea
a.
IBID
AN002000-Z8X1099
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Application Note
Minimizing EMI Effects During PCB Layout of Z8/Z8Plus Circuits
Several conclusions can be made from the designs:
•
Compare a & b. Orienting capacitors to current flow
reduces inductance.
•
Compare b & c. Multiple links have less L than one link
between traces.
•
Compare d & e. For lowest L, a signal track must be
aligned above its return track on the opposite side. This
is an example of how well ground planes work.
•
Compare c & e. Decrease local dI/dt density & L by
enlarging copper tracks.
These experiment conclusions can aid the designer in
decreasing the parasitic inductance of traces.
OTHER EMI PROTECTION
Understanding ESD And EFT
Consider two other EMI problems during the layout of the
PCB board, ESD (Electro-Static Discharge), and EFT
(Electrical Fast Transient).
ESD (Electro-Static Discharge) is a circuit phenomenon
that occurs in two ways: direct discharge and indirect
discharge. Direct discharge occurs when a human finger
touches exposed conductors. Indirect discharge causes an
ESD malfunction when a nearby ESD event radiates energy,
which couples into the system. EDS events usually have:
•
Voltage levels of 2,000-15,000V
•
Peak currents of 10-30A
•
Discharge current rise time of (tr) of 1-3nS
• ESD frequency of 100-300MHz.
Because of these characteristics, high frequency design
techniques are essential for good ESD immunity.
EFT (Electrical Fast Transient) are upsets caused by power
line noise bursts (due to motors), relay contact arcing (due
to switching inductive loads), and any switching of a inductive load. EFT is different from ESD because the noise originates from the power line that supplies the on-board devices.
EFT noise enters a system in two ways: radiated upset or
conducted upset. Radiated upset is the proximity of a power
line and a coupled signal. Conducted upset is power-line
noise being conducted to sensitive areas of the circuit.
•
Switches, Buttons, and membrane keypads
•
LED leads and speaker leads
•
Metal screws too close to circuitry
•
Signal I/O connectors and cables
•
PCB conductors near edge of board
•
Exposed conductors
•
Conductors close to openings or seams in the product
housing. ESD easily enters when the gap from the probe
to a conductor is too small.
To prevent direct discharge ESD, take these steps; they are
listed in order of importance:
•
Prevent ESD by using physical separation such as air
gaps or dielectric barriers
•
Bypass capacitors on I/O to absorb ESD at entry point.
Place these capacitors at the connector interface.
•
Place separate ESD ground connected to chassis ground
(best) or input power ground at power connector.
•
Place series resistance on I/O lines (100Ω to 1000Ω) to
limit ESD peak current
•
Pay special attention to critical Z8 circuits – oscillator,
OTP pins, and interrupt inputs by ensuring small circuit
area and clamping diodes to VCC
•
Use ESD I/O filters with series ferrite bead L and
ceramic C to Ground
•
Use continuous metal shields
ESD Direct Discharge Into Circuit
As explained above, direct discharge is typical of a charged
human coming in contact with exposed conductors. During
layout, examine the PCB board for any possibility of
exposed conductors. Exposed conductors should be
protected. Areas to examine:
•
14
Battery and Power Supply Contacts
•
Group the protected I/O pins together, and use a large
ESD ground for ceramic bypass capacitors. Use copper
length-to-width ratio of 5:1 or less for minimum L.
See Figure 17 for a graphical representation of a PCB case
and possible ESD paths. See Figure 18 for a sample layout
method to prevent ESD discharge.
AN002000-Z8X1099
Application Note
Minimizing EMI Effects During PCB Layout of Z8/Z8Plus Circuits
Figure 17. Suggested ESD Barriers for PCB Cases
Figure 18. Layout Methods to Stop Direct ESD Discharge
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Application Note
Minimizing EMI Effects During PCB Layout of Z8/Z8Plus Circuits
ESD Indirect Discharge Into Circuit
Indirect Discharge is caused by a radiated upset, and this
event is caused in two ways:
•
voltages. Note that 10 cm2 is not an overly large loop area
but the effects are large!
Table 3. Effects of Loop Area on Induced Voltage
Pickup occurs in a connected I/O device or peripheral
(display, plugged-in I/O cable, etc.) which is then
conducted into the product to cause upset or
•
Pickup occurs within the product itself. For example, an
oscillator with a long ground return path to the microcontroller ground pin.
To prevent Indirect Discharge into a product, reduce the
circuit loop areas, ensuring low inductance grounding and
signal routing. Voltage is induced easily on larger circuit
loops. Table 4 shows the effects of loop area on induced
Loop Area
Induced Voltage
1 cm2
2 Volts
5 cm2
10 volts
10 cm2
20 Volts
Figure 19 is an example of a large circuit loop, causing large
induced voltages. By re-routing the power and ground lines
to the Z8, the new loop area is significantly reduced and is
shown in Figure 20.
14 cm
51 cm
GND
10µF Power Cap
+5V
VCC
Z8
7 cm
GND
5 cm
Enclosed Loop = (51*14)-(7*5) = 679 cm
2
Figure 19. Example of a Large Loop Area
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Application Note
Minimizing EMI Effects During PCB Layout of Z8/Z8Plus Circuits
51 cm
0.2 cm
14 cm
7 cm
GND
+5V
Z8
10µF Power Cap
VCC
7 cm
GND
5 cm
2
Enclosed Loop = (51*0.2)+(7*0.2)+(7*0.2) = 13.0 cm
Figure 20. Example of a Large Loop Area
EFT Design Guidelines
Follow these guidelines to reduce the effects of EFT noise:
•
Use small MCU circuit loops to prevent radiated
upset. Examine these circuits: the Z8 VCC/GND loop,
the oscillator/GND loop, and the external interrupt
circuit loops.
•
Separate the Z8 power distribution and ground loops
from its low voltage circuitry, AC powered loads, and
noisy switched loads, such as motors and relays. Do this
when MCU is not isolated from AC mains
•
Locate ceramic decoupling capacitor close to MCU pins.
Add series ferrite bead between VCC source and MCU
to dampen spikes.
SUMMARY
Implementing the guidelines in this application note
improves the quality and reduces noise susceptibility in
most PCB boards. Most problems are solved by using the
simple design steps covered in the first part of this note.
High-speed problems need to be more thoroughly examined
than other parts of the circuit.
____________________________________________________________________________________________________
1
Gerald L. Ginsberg, Printed Circuits Design, pp. 80-81,85
2
Design Standard for Rigid Printed Boards and Rigid Printed Board Assemblies, ANSI/IPC-D-275, September 1991, The Institute
for interconnecting and Packaging electronic circuits, Lincolnwood, Ill.
3 Gerald
L. Ginsberg, Printed Circuits Design, pp. 82
4
Gary Cummings, System EMI, ESD & EFT Workshop, December 1997
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Application Note
Minimizing EMI Effects During PCB Layout of Z8/Z8Plus Circuits
Information Integrity
The information contained within this document has been verified according to the general principles of electrical and mechanical
engineering. Any applicable source code illustrated in the document was either written by an authorized ZiLOG employee or
licensed consultant. Permission to use these codes in any form, besides the intended application, must be approved through a license
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local ZiLOG Sales Office to obtain necessary license agreements.
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© 1999 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology
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