Impact of Body-Biasing Technique on RTN-induced
CMOS Logic Delay Uncertainty
Takashi Matsumoto
Kazutoshi Kobayashi
Hidetoshi Onodera
Department of Communications
Department of Electronics
Department of Communications
Kyoto Institute of Technology, Kyoto, Japan
and Computer Engineering
and Computer Engineering
Kyoto University, Kyoto, Japan
Kyoto University, Kyoto, Japan
Email: tmatsumoto@vlsi.kuee.kyoto-u.ac.jp
Abstract—The impact of Random telegraph noise (RTN) on
a CMOS logic circuit is evaluated. Statistical nature of RTNinduced delay fluctuation is described by measuring 1,680 ROs
fabricated in a commercial 40 nm CMOS technology. Small
number of samples have a large RTN-induced delay fluctuation.
It is found that the impact of RTN-induced delay fluctuation
becomes as much as 10.4 % under low supply voltage (0.65V)
operation. The impact of RTN-induced delay fluctuation tends to
be reduced by forward body-biasing technique, but a few ROs
do not follow this tendency.
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I. I NTRODUCTION
Designing reliable systems has become more difficult in
recent years[1]. RTN already has a severe impact on CMOS
image sensors[2], flash memories[3], and SRAMs[4]. Recently
we have shown that RTN also induces performance fluctuation
to logic circuits[5]. On the other hand, adaptive body-biasing
technique has been widely used to compensate for die-to-die
parameter variations[6]. However, the impact of the bodybiasing technique on RTN at the circuit level has not been well
understood. In this paper, we investigated the impact of bodybiasing technique on RTN-induced circuit delay fluctuation.
Fig. 1. Simplest test structure that can emulate the synchronous circuit
operation.
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II. I MPACT OF B ODY-B IASING T ECHNIQUE ON RTN
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Fig. 1 shows the simplest test structure that can emulate
the synchronous circuit operation. Combinational circuit delay
is emulated by ring oscillator (RO) oscillation frequency.
Sequential circuit operation is emulated by D flip-flop (DFF)
toggled by the RO output. The power supply for RO (VDDRO )
and DFF (VDDDFF ) can be independently controlled. The
value of VDDDFF is set to be larger than VDDRO so as to
guarantee the DFF operation. We can also control the substrate
bias for pMOS and nMOS. Fig. 2 shows the whole test structure for RTN measurement. RTN-induced delay fluctuation
is measured by a ring oscillator (RO) frequency fluctuation.
There are 840 same ROs on 2 mm2 area and the statistical
nature of RTN can be evaluated by the RO array. This chip
is fabricated in a commercial 40 nm CMOS technology.
All measurements are done at room temperature. Figure 3
shows the histogram of measured ∆F /Fmax for the whole
test structure of Fig. 2 over two chips (1,680 ROs). Here,
Fmax is defined as the maximum oscillation frequency and ∆F
is defined as the maximum frequency fluctuation. ∆F /Fmax
is a good measure for the impact of RTN-induced frequency
fluctuation and maximum ∆F /Fmax = 10.4 %.
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Whole test structure for RTN measurement.
Figure 4 shows the the measurement results of ∆F /Fmax
of different ROs for various substrate bias condition. Substrate bias conditions are categorized as reverse bias case
(Vbs−pMOS = −0.2V, Vbs−nMOS = 0V), normal bias case
(Vbs−pMOS = 0V, Vbs−nMOS = 0V), and forward bias case
(Vbs−pMOS = +0.2V, Vbs−nMOS = +0.2V). 300 ROs in one
test structure of Fig. 2 are investigated at VDD RO=0.65V.
Figure 4 shows ROs that have more than 4 % fluctuation at
reverse bias case to evaluate the forward body-bias effect on
large ∆F /Fmax samples (28 ROs). When substrate bias is
changed from the reverse bias case to the forward bias case,
∆F /Fmax tends to decrease. However, for example, ∆F /Fmax
slightly increases in the case of the RO location “68”, “160”
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Fig. 3. The histogram of measured ∆F /Fmax for the whole test structure
of Fig. 1 over two chips (1680 ROs).
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Fig. 5. Frequency fluctuation of RO location 1 of Fig. 4 for various substrate
bias conditions.
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Fig. 4. ∆F /Fmax of different ROs for various substrate bias condition. ROs
that have more than 4 % fluctuation at reverse substrate bias case are shown.
and “219” when forward substrate bias is applied. The impact
of RTN-induced delay fluctuation tends to be reduced by
forward body-biasing technique, but a few ROs do not follow
this tendency.
Figure 5 shows the frequency fluctuation of RO location
(section No. 1) of Fig. 4 for various substrate bias. Four-state
fluctuation due to two traps is clearly observed for the normal
substrate bias case. The effect of one of two traps disappears
for the forward bias case. Figure 6 shows the frequency
fluctuation of RO location 1 of Fig. 4 when pMOS or nMOS is
forward biased. The effect of one of two traps disappears only
when nMOS is forward biased. Thus the disappeared two-state
fluctuation is caused by a single trap in a specific nMOS in
the RO.
III. C ONCLUSION
Statistical nature of RTN-induced delay fluctuation is described by measuring 1,680 ROs fabricated in a commercial
40 nm CMOS technology . Small number of samples (19 ROs)
have a large RTN-induced delay fluctuation of more than 6%
of nominal oscillation frequency. The impact of RTN-induced
delay fluctuation becomes as much as 10.4 % under low
supply voltage (0.65V) operation. The impact of RTN-induced
delay fluctuation tends to be reduced by forward body-biasing
technique, but a few ROs still have a large fluctuation.
Fig. 6. Frequency fluctuation of RO location 1 of Fig. 4 for various substrate
bias conditions.
ACKNOWLEDGMENT
The VLSI chip in this study has been fabricated in the
chip fabrication program of VLSI Design and Education
Center (VDEC), the University of Tokyo in collaboration with
STARC.
R EFERENCES
[1]
[2]
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[6]
S. Bokar, IEEE Micro, 25 (2005) p.10.
X. Wang, et al., IEDM Tech. Dig., p. 115, 2006.
H. Kurata, et al., IEEE J. Solid-State Circuits, 42 (2007) p.1362.
M. Yamaoka, et al., IEDM Tech. Dig., p.745, 2011.
K. Ito, et al., Proc. IRPS, 2011, p.710.
J. Tschanz, et al., IEEE J. Solid-State Circuits, 37 (2002) p.1396.