Reprinted from
REGULAR PAPER
Impact of Body-Biasing Technique on Random Telegraph Noise Induced Delay Fluctuation
Takashi Matsumoto, Kazutoshi Kobayashi, and Hidetoshi Onodera
Jpn. J. Appl. Phys. 52 (2013) 04CE05
# 2013 The Japan Society of Applied Physics
Person-to-person distribution (up to 10 persons) by the author only. Not permitted for publication for institutional repositories or on personal Web sites.
REGULAR PAPER
Japanese Journal of Applied Physics 52 (2013) 04CE05
http://dx.doi.org/10.7567/JJAP.52.04CE05
Impact of Body-Biasing Technique on Random Telegraph Noise Induced Delay Fluctuation
Takashi Matsumoto1 , Kazutoshi Kobayashi2;3 , and Hidetoshi Onodera1;3
1
Department of Communications and Computer Engineering, Graduate School of Informatics, Kyoto University, Kyoto 606-8501, Japan
Department of Electronics, Graduate School of Science and Technology, Kyoto Institute of Technology, Kyoto 606-8585, Japan
3
JST, CREST, Chiyoda, Tokyo 102-0076, Japan
E-mail: tmatsumoto@vlsi.kuee.kyoto-u.ac.jp
2
Received September 24, 2012; revised November 22, 2012; accepted November 28, 2012; published online March 21, 2013
The statistical nature of random telegraph noise (RTN) induced delay fluctuation is described by measuring 1,655 ROs fabricated in a commercial
40 nm CMOS technology. A small number of samples have a large RTN-induced delay fluctuation. We investigated the impact of the body-biasing
technique on RTN-induced circuit delay fluctuation for various substrate bias conditions. The impact of RTN-induced delay fluctuation tends to be
reduced by the forward body-biasing technique, but a few ROs still have a large fluctuation. # 2013 The Japan Society of Applied Physics
1. Introduction
Designing reliable systems has become more difficult in
recent years.1–3) In addition to conventional problems
such as transistor leakage, the degradation and variation of
transistor performance have a severe impact on the
dependability of very large scale integration (VLSI) systems.
Random telegraph noise (RTN)4–6) and negative bias
temperature instability (NBTI)7,8) are two major concerns
for recent transistor reliability that is related to the physical
property of a very thin gate oxide insulator. NBTI occurs in
p-channel metal–oxide–semiconductor (pMOS) transistors
stressed with negative gate voltages at high temperatures.
Critical device parameters such as drain current (Ids ),
threshold voltage (Vth ), and transconductance (gm ) are
degraded by NBTI. A remarkable phenomenon regarding
NBTI is that the degraded performance of a pMOS recovers
immediately after the stress is removed or relaxed.9)
Recently, we have proposed a very high-speed NBTI
recovery sensor to minimize the impact of the recovery
effect.10) We have discussed an LSI lifetime extension by
NBTI-recovery-based self-healing based on the 400 ns
measurement delay recovery measurement.11) RTN has
attracted attention as a temporal transistor performance
fluctuation. RTN occurs in both pMOS and n-channel MOS
(nMOS). RTN is an intrinsically random phenomenon. RTN
already has a severe impact on CMOS image sensors,12)
flash memories,13) and SRAMs.14–16) Recently, we have
shown that RTN also induces performance fluctuation in
logic circuits.17,18) In contrast, an adaptive body-biasing
technique has been widely used to compensate for die-to-die
parameter variations.19) However, the impact of the bodybiasing technique on RTN at the circuit level has not been
well understood. In this study, we investigated the impact of
the body-biasing technique on RTN-induced circuit delay
fluctuation.20)
2. Simplest Test Structure of Synchronous Circuit
Figure 1 shows a typical synchronous circuit structure where
a logic path exists between two registers. The impact of
the reliability of transistors that construct the synchronous
circuit has increased in recent years. When transistor
performance fluctuates owing to RTN, the propagation delay
of combinational logic also fluctuates. The correct operation
of a register may not be guaranteed. Figure 2 shows the
Fig. 1. (Color online) Typical synchronous circuit structure.
Fig. 2. (Color online) Simplest test structure that can emulate the
synchronous circuit operation.
simplest test structure that can emulate the synchronous
circuit operation. Combinational circuit delay is emulated by
ring oscillator (RO) oscillation frequency. Sequential circuit
operation is emulated by D flip-flop (DFF) toggled by the
RO output. The power supply for RO (VDDRO ) and DFF
(VDDDFF ) can be independently controlled. The value of
VDDDFF is set to be larger than VDDRO so as to guarantee
the DFF operation. We can also control the substrate bias for
pMOS and nMOS. Figure 3 shows the whole test structure
for RTN measurement. RTN-induced delay fluctuation is
measured by the RO frequency fluctuation. We measured
7-stage ROs in this study. There are 840 same samples
as shown in Fig. 2 on a 2 mm2 area. Thus, the statistical
nature of RTN can be evaluated by the RO array. This
chip is fabricated in a commercial 40 nm CMOS technology.
All measurements are carried out at room temperature.
Figure 4(a) shows the measurement results of the oscillation
frequency for about 100 s at VDDRO ¼ 0:65 V. We use
the minimum-width transistors for both nMOSFET and
pMOSFET allowed in the technology. The ratio of nMOS
04CE05-1
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T. Matsumoto et al.
Fig. 5. (Color online) F=Fmax of different ROs for various substrate
bias conditions. ROs that have more than 4% fluctuation in the reverse
substrate bias case are shown.
Fig. 3. (Color online) Whole test structure for RTN measurement.
Fig. 4. (Color online) (a) Measurement result of RTN-induced RO
frequency fluctuation. (b) Histogram of measured F=Fmax .
(pMOS) gate area of the smallest size inverter to the
standard size inverter in this technology is 0.30 (0.21). The
body biases for pMOS (Vbs-pMOS ) and nMOS (Vbs-nMOS ) are
set to 0 V. We count the output pulse at the counter 1,024
times and counting error is less than 0.1% compared with
the count number. Measurement results show the large
step-like frequency fluctuation. Here, Fmax is defined as
the maximum oscillation frequency. F is defined as the
maximum frequency fluctuation, as shown in Fig. 4(a).
F=Fmax is a good measure for the impact of RTN-induced
frequency fluctuation. It is 10.4% for Fig. 4(a). Figure 4(b)
shows a histogram of the measured F=Fmax for the whole
test structure of Fig. 3 over two chips. It is found that a small
number of samples have a large RTN-induced fluctuation
and a long tail exists for larger F=Fmax .
3. Impact of Body-Biasing Technique on RTN
Figure 5 shows the the measurement results of F=Fmax
of different ROs for various substrate bias conditions.
Substrate bias conditions are categorized as the reverse bias
case (Vbs-pMOS ¼ 0:2 V, Vbs-nMOS ¼ 0 V), normal bias case
Fig. 6. Frequency fluctuation of RO location 1 of Fig. 5 for various
substrate bias conditions.
(Vbs-pMOS ¼ 0 V, Vbs-nMOS ¼ 0 V), and forward bias case
(Vbs-pMOS ¼ þ0:2 V, Vbs-nMOS ¼ þ0:2 V). A test structure
including 300 ROs is investigated at VDDRO ¼ 0:65 V.
Figure 5 shows ROs that have more than 4% fluctuation in
the reverse bias case to evaluate the forward body-bias effect
on large F=Fmax samples (28 ROs). When the substrate
bias is changed from the reverse bias case to the forward bias
case, F=Fmax tends to decrease. However, for example,
F=Fmax slightly increases in the case of the RO locations
‘‘68’’, ‘‘160’’, and ‘‘219’’ when forward substrate bias is
applied. The impact of RTN-induced delay fluctuation tends
to be reduced by the forward body-biasing technique, but a
few ROs do not follow this tendency.
Figure 6 shows the frequency fluctuation of RO location
(section No.) 1 of Fig. 5 for various substrate biases. Fourstate fluctuation due to two traps is clearly observed for the
normal substrate bias case. The effect of one of the two traps
disappears for the forward bias case. Figure 7 shows the
04CE05-2
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Fig. 8. (Color online) Histogram of measured F=Fmax for various substrate bias conditions.
reduced by the forward body-biasing technique, but a few
ROs still have a large fluctuation.
Acknowledgments
We are grateful to S. Fujimoto, K. Kitajima, I. Mahfuzul, T.
Miki, and S. Nishizawa for chip design. The VLSI chip
in this study was fabricated in the chip fabrication program
of the VLSI Design and Education Center (VDEC), the
University of Tokyo, in collaboration with STARC.
1)
2)
3)
4)
5)
Fig. 7. Frequency fluctuation of RO location 1 of Fig. 5 for various
substrate bias conditions.
6)
frequency fluctuation of RO location 1 of Fig. 5 when
pMOS or nMOS is forward biased. The effect of one of the
two traps disappears only when nMOS is forward biased.
Thus, the disappearance of two-state fluctuation is caused
by a single trap in a specific nMOS in the RO. Figure 8
shows a histogram of the measured F=Fmax for one test
structure under various substrate biases. The impact of RTNinduced delay fluctuation tends to be reduced by the forward
body-biasing technique, but a few ROs still have a large
fluctuation.
4. Conclusions
7)
8)
9)
10)
11)
12)
13)
14)
15)
16)
The statistical nature of RTN-induced delay fluctuation is
described by measuring 1,655 ROs fabricated in a
commercial 40 nm CMOS technology. A small number of
samples have a large RTN-induced delay fluctuation. The
impact of RTN-induced delay fluctuation becomes as
much as 10.4% under low supply voltage (0.65 V) operation.
The impact of RTN-induced delay fluctuation tends to be
17)
18)
19)
20)
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# 2013 The Japan Society of Applied Physics