November 1996
74LVT573
3.3V ABT Octal Transparent Latch
with TRI-STATEÉ Outputs
General Description
Features
The LVT573 consists of eight latches with TRI-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is low, the data satisfying the input timing
requirements is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the bus
output is in the high impedance state.
These octal latches are designed for low-voltage (3.3V) VCC
applications, but with the capability to provide a TTL interface to a 5V environment. The LVT573 is fabricated with an
advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation.
Y
Y
Y
Y
Y
Y
Y
Y
Input and output interface capability to systems at 5V
VCC
Bus-Hold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
Live insertion/extraction permitted
Power Up/Down high impedance provides glitch-free
bus loading
Outputs source/sink b32 mA/ a 64 mA
Available in SOIC JEDEC, SOIC EIAJ, TSSOP and
SSOP II
Functionally compatible with the 74 series 573
Latch-up performance exceeds 500 mA
Logic Symbols
Connection Diagram
Pin Assignment for
SOIC, TSSOP and SSOP II
IEEE/IEC
TL/F/12450–1
TL/F/12450 – 3
TL/F/12450 – 2
Pin Names
D 0 – D7
Order Number
See NS Package Number
Description
Data Inputs
LE
Latch Enable Input
OE
Output Enable Input
O0 – O7
TRI-STATE Latch Outputs
SOIC JEDEC
SOIC EIAJ
TSSOP
SSOP II
74LVT573WM
74LVT573WMX
74LVT573SJ
74LVT573SJX
74LVT573MTC
74LVT573MTCX
74LVT573MSA
74LVT573MSAX
M20B
M20D
MTC20
MSA20
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C1996 National Semiconductor Corporation
TL/F/12450
RRD-B30M17/Printed in U. S. A.
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74LVT573 3.3V ABT Octal Transparent Latch with TRI-STATE Outputs
PRELIMINARY
Functional Description
Truth Table
The LVT573 contains eight D-type latches with TRI-STATE
standard outputs. When the Latch Enable (LE) input is
HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will
change state each time its D input changes. When LE is
LOW, the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW,
the standard outputs are in the 2-state mode. When OE is
HIGH, the standard outputs are in the high impedance mode
but this does not interfere with entering new data into the
latches.
Inputs
Outputs
LE
OE
Dn
On
X
H
H
L
H
L
L
L
X
L
H
X
Z
L
H
O0
H e HIGH Voltage Level
L e LOW Voltage Level
Z e High Impedance
X e Immaterial
O0 e Previous O0 before HIGH to LOW transition of Latch Enable
Logic Diagram
TL/F/12450 – 4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings (Note 1)
Symbol
Parameter
Value
Conditions
Units
VCC
Supply Voltage
b 0.5 to a 7.0
VI
DC Input Voltage
b 0.5 to a 7.0
VO
DC Output Voltage
b 0.5 to a 7.0
Output in TRI-STATE
V
b 0.5 to a 7.0
Output in High or Low State (Note 2)
V
IIK
DC Input Diode Current
b 50
IOK
DC Output Diode Current
b 50
IO
DC Output Current
ICC
DC Supply Current per Supply Pin
IGND
DC Ground Current per Ground Pin
TSTG
Storage Temperature
V
V
VI k GND
mA
VO k GND
mA
64
VO l VCC Output at High State
mA
128
VO l VCC Output at Low State
g 64
mA
g 128
mA
b 65 to a 150
§C
Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these
limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the Absolute Maximum Ratings. The ‘‘Recommended Operating
Conditions’’ table will define the conditions for actual device operation.
Note 2: IO Absolute Maximum Rating must be observed.
Recommended Operating Conditions
Symbol
Parameter
Operating
Data Retention
Min
Max
Units
2.0
1.5
3.6
3.6
V
0
3.6
V
0
0
VCC
5.5
V
VCC
Supply Voltage
VI
Input Voltage
VO
Output Voltage
IOH
High-Level Output Current
b 32
IOL
Low-Level Output Current
64
TA
Free-Air Operating Temperature
Dt/DV
Input Edge Rate, VIN e 0.8V–2.0V, VCC e 3.0V
HIGH or LOW State
TRI-STATE
mA
b 40
85
§C
0
10
ns/V
DC Electrical Characteristics
Symbol
Parameter
VCC
(V)
VIK
Input Clamp Diode Voltage
VIH
Input HIGH Voltage
2.7–3.6
VIL
Input LOW Voltage
2.7–3.6
VOH
Output HIGH Voltage
2.7–3.6
VOL
Output LOW Voltage
TA e b40§ C to a 85§ C
Min
2.7
Typ
(Note 3)
Units
Conditions
Max
b 1.2
V
II e b18 mA
V
VO s 0.1V or
VO t VCC b 0.1V
VCC b 0.2
V
IOH e b100 mA
2.7
2.4
V
IOH e b8 mA
3.0
2.0
V
IOH e b32 mA
2.0
0.8
2.7
0.2
V
IOL e 100 mA
2.7
0.5
V
IOL e 24 mA
3.0
0.4
V
IOL e 16 mA
3.0
0.5
V
IOL e 32 mA
3.0
0.55
V
IOL e 64 mA
3
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DC Electrical Characteristics
Symbol
II(HOLD)
II(OD)
II
(Continued)
T A eb40§ C to a 85§ C
VCC
(V)
Parameter
Bus-Hold Input Minimum Drive
Min
3.0
Bus-Hold Input Over-Drive
Current to Change State
3.0
Input Current
3.6
Control Pins
Data Pins
Typ
(Note 3)
Units
Conditions
Max
75
mA
VI e 0.8V
b 75
mA
VI e 2.0V
500
mA
(Note 4)
b 500
mA
(Note 5)
10
mA
VI e 5.5V
3.6
g1
mA
VI e 0V or VCC
3.6
b5
mA
VI e 0V
1
mA
VI e VCC
IOFF
Power Off Leakage Current
0
g 100
mA
0V s VI or VO s 5.5V
IPU/PD
(Note 6)
Power up/down TRI-STATE
Output Current
0–1.2V
g 100
mA
VO e 0.5V to VCC
VI e GND or VCC
IOZL
TRI-STATE Output Leakage Current
3.6
b5
mA
VO e 0.5V
IOZH
TRI-STATE Output Leakage Current
3.6
5
mA
VO e 3.0V
TRI-STATE Output Leakage Current
3.6
10
mA
VCC k VO s 5.5V
ICCH
Power Supply Current
3.6
0.19
mA
Outputs High
ICCL
Power Supply Current
3.6
12
mA
Outputs Low
ICCZ
Power Supply Current
3.6
0.19
mA
Outputs Disabled
ICCZ a
Power Supply Current
3.6
0.19
mA
VCC s VO s 5.5V,
Outputs Disabled
DICC
Increase in Power Supply Current
(Note 7)
3.6
0.2
mA
One Input at VCC b 0.6V
Other Inputs at VCC or GND
IOZH
a
Note 3: All typical values are at VCC e 3.3V, TA e 25§ C.
Note 4: An external driver must source at least the specified current to switch from LOW to HIGH.
Note 5: An external driver must sink at least the specified current to switch from HIGH to LOW.
Note 6: This parameter is valid for any VCC between 0V and 1.2V at 25§ C only.
Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Dynamic Switching Characteristics (Note 8)
Symbol
VOLP
VOLV
Parameter
Quiet Output Maximum Dynamic VOL
Quiet Output Minimum Dynamic VOL
TA e 25§ C
VCC
(V)
Min
Typ
Conditions
CL e 50 pF, RL e 500X
3.3
0.8
V
(Note 9)
3.3
b 0.8
V
(Note 9)
Note 8: Characterized in SOIC package. Guaranteed parameter, but not tested.
Note 9: Max number of outputs defined as (n). n b 1 data inputs are driven 0V to 3V. Output under test held LOW.
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Units
Max
4
AC Electrical Characteristics
TA e b40§ C to a 85§ C
Symbol
Parameter
VCC e 3.3V g 0.3V
Units
VCC e 2.7V
Min
Max
Min
Max
tPHL
tPLH
Propagation Delay
Dn to On
1.0
1.0
4.3
4.2
1.0
1.0
5.2
4.7
ns
tPHL
tPLH
Propagation Delay
LE to On
2.5
1.6
6.5
5.6
2.5
1.6
7.2
6.3
ns
tPZL
tPZH
Output Enable Time
1.3
1.0
5.5
5.1
1.3
1.0
6.6
6.2
ns
tPLZ
tPHZ
Output Disable Time
1.5
2.0
4.6
5.7
1.5
2.0
5.1
6.7
ns
tS
Setup Time, Dn to LE
0.7
0.6
ns
tH
Hold Time, Dn to LE
1.6
1.8
ns
tW
LE Pulse Width
3.3
3.3
ns
tOSHL
tOSLH
Output to Output Skew (Note 3)
1.0
1.0
ns
Note 3: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH).
Capacitance
Conditions
Typical
CIN
Symbol
Input Capacitance
Parameter
VCC e Open, VI e 0V or VCC
4
Units
pF
COUT
Output Capacitance
VCC e 3.3V, VI e 0V or VCC
8
pF
74LVT573 Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
TL/F/12450 – 5
5
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Molded Small Outline Package, JEDEC
Order Number 74LVT573WM or 74LVT573WMX
NS Package Number M20B
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead (0.300× Wide) Molded Small Outline Package, EIAJ
Order Number 74LVT573SJ or 74LVT573SJX
NS Package Number M20D
20-Lead Molded Shrink Small Outline Package, EIAJ, Type II
Order Number 74LVT573MSA or 74LVT573MSAX
NS Package Number MSA20
7
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74LVT573 3.3V ABT Octal Transparent Latch with TRI-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Molded Thin Shrink Small Outline Package, JEDEC
Order Number 74LVT573MTC or 74LVT573MTCX
NS Package Number MTC20
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