370
JOURNAL OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA, VOL. 5, NO. 4, DECEMBER 2007
New Curvature-Compensated CMOS Bandgap
Voltage Reference
Lu Shen, Ning Ning, Qi Yu, Yan Luo, and Chun-Sheng Li
Abstract⎯A novel curvature-compensated CMOS
bandgap voltage reference is presented. The reference
utilizes two first order temperature compensations
generated from the nonlinearity of the finite current gain
β of vertical pnp bipolar transistor. The proposed circuit,
designed in a standard 0.18 µm CMOS process, achieves a
good temperature coefficient of 2.44 ppm/°C with temperature range from −40 °C to 85 °C, and about 4 mV supply
voltage variation in the range from 1.4 V to 2.4 V. With a
1.8 V supply voltage, the power supply rejection ratio is
−56 dB at 10 MHz.
Index Terms⎯Bandgap voltage reference, CMOS,
curvature-compensation technique, finite current gain.
1. Introduction
Precision bandgap voltage references (BVR) are always
in great demand in many applications such as analog to
digital (A/D) and digital to analog (D/A) converters, voltage
regulators, and measurement systems. As the resolution of
data converter system increases, requirements for very high
temperature stability of BVR have also increased. This has
given a rise to many temperature compensation techniques,
such as quadratic temperature compensation [1], exponential
temperature compensation[2], and piecewise line curvature
correction [3]. Although these new techniques have reduced
the temperature coefficients (TC) of voltage references by
certain extent, there is still a flaw: the lower temperature
coefficients are obtained with expenses in the circuit
complexity.
In recent years, high order CMOS temperature
compensated current reference accomplished by two first
order temperature compensation current references is also
presented[4]. The circuit exploits the temperature characteristics of integrated-circuit resistors and gate-source voltage of
MOS transistors working in weak inversion. However, the
circuit is sensitive to process variation and difficult to
control.
This paper proposes a high precision curvature compenManuscript received August 15, 2007; revised September 5, 2007.
L.-U. Shen, N. Ning, Q. Yu, Y. Luo and C.-S. Li are with School of
Microelectronics & Solid-State Electronics, University of Electronic Science
and Technology of China (UESTC), Chengdu, 610054, China
(e-mail:4681608@163.com).
sation bandgap voltage reference, whose architecture is
simple and easily realized. With proper adjustment of the
resistors, two first order temperature compensation current
references are obtained just by changing the current levels of
the BJTs. Then, a current superposition circuit is introduced
to realize the high order temperature compensation. In
Section 2, a new curvature compensation technique is
introduced. Section 3 presents the circuit using the proposed
technique in this paper. In Section 4, simulation results are
summarized. Conclusions are given in Section 5.
2. New Curvature Compensation
Technique
The typical implementation of a traditional bandgap
voltage reference in CMOS technology is shown in Fig. 1.
The BJTs (Q0 and Q1) are typically implemented by the
diode-connected vertical pnp BJTs [5].
Fig. 1. Traditional bandgap voltage reference circuit in CMOS
technology.
In this circuit, the bandgap voltage reference is
generated by summing two voltages of opposite temperature
coefficients. It is typically the sum of the base-emitter
voltage of a bipolar transistor biased in the forward region,
which exhibits negative TC, and an amplified version of the
difference between two base-emitter voltages generated by
two bipolar devices sized with different emitter areas and
possibly different bias currents [6]. It can be expressed as
VREF = VEB + mΔVEB .
(1)
However, compared with VT, which is a fully linear
function of temperature, VBE is a complex function of
temperature containing many higher order terms [6].Most of
SHEN et al.: New Curvature-Compensated CMOS Bandgap Voltage Reference
important, the temperature character of ΔVBE is also nonlinear.
As shown in Fig. 1, two identical transistors (Is1=Is2) are
biased at emitter currents of nI0 and I0, then
ΔVEB = VEB1 − VEB2 = VT ln
I C1
I
− VT ln C 2 .
I S1
IS 2
(2)
Thus, we can write
⎛ β (1 + β 2 ) ⎞
⎛ 1 + β 2−1 ⎞
ΔVEB = VT ln ⎜ n 1
.
⎟ = VT ln ⎜ n
−1 ⎟
⎝ 1 + β1 ⎠
⎝ β 2 (1 + β1 ) ⎠
(3)
low-current region, where β decreases as IC decreases.
Region 2 is the mid-current region, where β is approximately
constant. Region 3 is the high-current region, where β
decreases as IC increases. Since
(4)
I C = I S exp (VEB VT )
We can obtain that β decreases as VEB decreases at region 1
and decreases as IC increases at region 3 but is a constant at
region 2.
When The BJTs (Q0 and Q1) in the circuit of Fig. 1
work at moderate current level represented by region 2, the
current gain β is independent of the variation of VEB and β1,
β2 are approximately equal, as shown in Fig. 4. Equation (3)
is therefore modified as
ΔVEB = VT ln n .
(5)
Therefore,
VREF = VEB + K ΔVEB = VEB + KVT ln n .
(6)
Suggesting that the BJTs work at region 2, the nonlinear
characteristic of VBE dominates rather than that of ΔVBE.
According to the analysis in [7], we find that the temperature
compensation current is curvatured-down.
β1
β2
Current gain
So there is a certain limit for temperature stability of the
first order compensated BVR. Therefore we have to exploit
curvature compensation technique if the circuit needs high
precision BVR.
A new high order temperature compensation technology
is described in this paper, which is shown in Fig. 2. The basic
principle is adding a properly scaled curvatured-down first
order temperature compensation current Iref1 to a properly
scaled curvatured-up first order temperature compensation
current Iref2 [4]. Finally, the high order curvature correction
current IREF is optimized by the appropriated ratio of a/b.
As a result, how to obtain Iref1 and Iref2 is the key to the
new high order temperature compensation. In this paper, the
nonlinearity of the finite current gain β of the BJTs is utilized
to generate them.
371
Temperature (°C)
Fig. 4. Typical curves of current gains β1 and β2 at region 2.
β1
Region 1
Current gain
12
Region 2
Region 3
T=125°C
Current gain
Fig. 2. Principle of proposed high order temperature compensation.
β2
9
6
T=25°C
3
T= −55°C
0
0.1μ
Temperature (°C)
1μ
10μ
100μ
1m
Collector current (A)
10m
Fig. 3. Typical curves of β versus IC for a pnp integrated-circuit
transistor.
As we know, the current gain β of vertical pnp bipolar
transistor is not a constant. This parameter does in fact
depend on the operating conditions of the transistor [7]. The
variation of β with collector current, which is apparent in
Fig. 3, can be divided into three regions. Region 1 is the
Fig. 5. Typical curves of current gains β1 and β2 at region 3.
When The BJTs work at high current level represented
by region 3, the current gain β is sensitive to the variation of
VEB [7]. Due to the difference between VEB1 and VEB2, β1 and β2
vary significantly, as shown in Fig.5. Equation (3) is
therefore modified as
⎛ 1 + β 2−1 ⎞
ΔVEB = VT ln ⎜ n
−1 ⎟
⎝ 1 + β1 ⎠
(7)
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JOURNAL OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA, VOL. 5, NO. 4, DECEMBER 2007
VDD
M1
OP1
+ －
M3
M2
M9
M4
M11
M5
M12
R2
R1
Q0
Q1
M4
M4
M10
M4
C0
R6
R7
MS3
MS2
MS1
R5
R3
R0
OP2
－ +
Q2
Q3
R4
GND
Fig. 6. The complete circuit of the proposed voltage reference.
and then
⎛ 1 + β 2−1 ⎞
VREF = VEB + K ΔVEB = VEB + KVT ln ⎜ n
.
−1 ⎟
⎝ 1 + β1 ⎠
(8)
Suggesting that the BJTs work at region 3, the nonlinear
characteristic of ΔVBE dominates rather than that of VBE. Thus,
we find that the temperature compensation current is
curvatured-up.
According to the analysis above, we conclude that both
curvatured-down current Iref1 and curvatured-up current Iref2
can be obtained through changing the current levels of the
BJTs.
VREF [3]. The fourth is start-up circuit composed of MS1 to MS3,
R0 and C0 [8].
In the design, resistors R1 and R3 are valued 31 KΩ with
R2 5 KΩ, to make Q0，Q1 working in region 2.While, resistors
R4 and R6 are valued 2.5 KΩ with R5 0.5 KΩ, to make Q2，Q3
working at region 3.
The architecture of OP1 and OP2 is the P-channel input
two-stage configuration shown in Fig. 7 to increase the
common mode input range [9]. The second stage is configured
as a simple common-source stage so as to allow maximum
output swing [10].
4. Simulation Data and Result
Analysis
3. Implementation of the Voltage
Reference
The proposed voltage reference shown in Fig. 6 is
composed of four sub-circuits. The first consists of
transistors M1 to M4, resistors R1 to R3, vertical pnp BJTs Q0
to Q1 and the op-amp OP1 to generate the curvatured-down
current Iref1.The second includes transistors M5-M8, resistors
R4 to R6 ,vertical pnp BJTs Q2 to Q3and the op-amp OP2 to
give the curvatured-down current Iref2. The third is current
superposition circuit consisting of M9 to M12 and R7 to output
Reference voltage (V)
Fig. 7. Operational amplifier circuit in the voltage reference.
Based on SMIC model for 0.18 µm process, voltage
versus temperature curve and voltage versus power supply
curve of the proposed current source are derived by Cadence
simulations, over a temperature range from −40 to 85 °C and
a supply voltage range from 1.4 V to 2.4 V, respectively.
Reference voltage TC curve is shown in Fig. 8. The
reference voltage is 1.066 V at room temperature, with zero
temperature coefficient (ZTC) point at 51.7 °C. Over the
working temperature range, the max-to-min fluctuation of the
reference voltage is only 0.3 mV, achieving a temperature
coefficient of 2.44 ppm/°C.
1.0669
1.0668
1.0667
1.0666
−40
0
40
80
Temperature (°C)
Fig. 8. Simulated voltage VREF against temperature.
The variation of VREF with supply voltage is plotted in
Fig. 9. The maximum fluctuation of reference voltage is only
SHEN et al.: New Curvature-Compensated CMOS Bandgap Voltage Reference
4 mV over the supply voltage range from 1.4 V to 2.4 V. This
can be further improved if a cascode stage is incorporated in
the operation amplifier design, but at the cost of a higher
supply voltage.
Reference voltage (V)
1.0676
1.0666
1.0656
1.0646
1.0636
1.4 1.6 1.8 2.0 2.2
Supply voltage (V)
2.4
Voltage (dB)
Fig. 9. Simulated voltage VREF against power supply.
1
100
10k
1M
Frequency (Hz)
100M
Fig. 10. PSRR of the bandgap voltage reference.
Fig. 10 gives the simulated PSRR at 1.8 V supply
without a filtering capacitor. It can be seen that the PSRR is
−56 dB below 10 MHz. High frequency terms of the bandgap
reference voltage can be filtered by adding an RC low-pass
filter.
5. Conclusions
A new curvature compensation approach for bandgap
voltage reference, which exploits the superposition of
curvatured-down and curvatured-up current, is proposed in
this paper. Both curvatured-down and curvatured-up current
can be obtained through changing the current levels of the
BJTs by proper adjustment of the resistors. Proved by
simulation, the bandgap reference delivers the output voltage
of 1.066V, and provides a temperature coefficient of
2.44 ppm/°C. The PSRR of the circuit is less than −56 dB for
frequencies below 10 MHz.
References
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compensated CMOS bandgap reference,” IEEE J. Solid-State
Circuits, vol. 18, pp. 634-643, Feb. 1983.
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Solid-State Circuits, vol. 29, pp. 1396-1403, Feb. 1994.
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[3] G. A. Rincon-Mora and P. E. Allen, “Exponential curvature
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Lu Shen was born in Shandong Province, China, in 1986. He
received the B.S. degree in microelectronics from University of
Electronic Science and Technology of China ( UESTC) in 2006. He
is currently pursuing the M.S. degree with the Department of
Microelectronics & Solid-State Electronics, UESTC. His research
interests focus on high-speed high-resolution pipelined ADCs.
Ning Ning was born in Shanxi Province, China, in 1981. He
received the B.S., M.S., and Ph.D. degrees from UESTC, in 2002,
2004, and 2007, respectively, all in microelectronics. His research
interests include VDSM device, circuit and SOC, ADC/DAC, and
ULSI reliability simulation & monitoring.
Qi Yu was born in Shandong Province, China, in 1972. He
received the B.S. and M.S. degrees from UESTC, in 1994 and 1997,
respectively, all in microelectronics. His research interests include
VDSM circuit and SOC, ADC/DAC, and ULSI reliability
simulation & monitoring.
Yan Luo was born in Sichuan Province, China, in 1984. He
received the B.S. degree in microelectronics from UESTC, in 2006.
He is currently pursuing the M.S. degree with the Department of
Microelectronics & Solid-State Electronics, UESTC. His research
interests focus on high-speed high-resolution pipelined ADCs.
Chun-Sheng Li was born in Hubei Province, China, in 1984.
He received the B.S. degree in microelectronics from UESTC in
2005. He is currently pursuing the M.S. degree with the Department
of Microelectronics & Solid-State Electronics, UESTC. His research
interests focus on high-speed high-resolution pipelined ADCs.