Sub-1V Curvature Compensated Bandgap Reference
Master Thesis Performed in Electronic Devices
By
Kevin Tom
Reg. Nr.: LiTH-ISY-EX-3592-2004
Linköping University, 2004.
Sub-1V Curvature Compensated Bandgap Reference
Master Thesis
Electronic Devices
Department of Electrical Engineering
Linköping University, Sweden.
Kevin Tom
Reg. Nr.: LiTH-ISY-EX-3592-2004
Supervisor: Atila Alvandpour
Examiner: Atila Alvandpour
Linköping, Nov. 1, 2004
Avdelning, Institution
Division, Department
Datum
Date
2004-11-01
Institutionen för systemteknik
581 83 LINKÖPING
Språk
Language
Svenska/Swedish
X Engelska/English
Rapporttyp
Report category
Licentiatavhandling
X Examensarbete
C-uppsats
D-uppsats
ISBN
ISRN LITH-ISY-EX-3592-2004
Serietitel och serienummer
Title of series, numbering
ISSN
Övrig rapport
____
URL för elektronisk version
http://www.ep.liu.se/exjobb/isy/2004/3592/
Titel
Title
Kompensering av Andra Ordningens fel i en sub-1V Bandgaps Referens
Sub-1V Curvature Compensated Bandgap Reference
Författare
Author
Kevin Tom
Sammanfattning
Abstract
This thesis investigates the possibility of realizing bandgap reference crcuits for processes having
sub-1V supply voltage. With the scaling of gate oxide thickness supply voltage is getting reduced.
But the threshold voltage of transistors is not getting scaled at the same rate as that of the supply
voltage. This makes it difficult to incorporate conventional designs of bandgap reference circuits to
processes having near to 1V supply voltage. In the first part of the thesis a comprehensive study
on existing low voltage bandgap reference circuits is done. Using these ideas a low-power, lowvoltage bandgap reference circuit is designed in the second part of the thesis work.
The proposed bandgap reference circuit is capable of generating a reference voltage of 0.730V. The
circuit is implemented in 0.18µm standard CMOS technology and operates with 0.9V supply
voltage, consuming 5µA current. The circuit achieves 7 ppm/K of temperature coefficient with
supply voltage range from 0.9 to 1.5V and temperature range from 0 to 60C.
Nyckelord
Keyword
Bandgap Reference, CMOS Voltage Reference
Abstract
This thesis investigates the possibility of realizing bandgap reference circuits for
processes having sub 1V supply voltage. With the scaling of gate oxide thickness supply
voltage is getting reduced. But the threshold voltage of transistors is not getting scaled at
the same rate as that of the supply voltage. This makes it difficult to incorporate
conventional designs of bandgap reference circuits to processes having near to 1V supply
voltage. In the first part of the thesis a comprehensive study on existing low voltage
bandgap reference circuits is done. Using these ideas a low-power, low-voltage bandgap
reference circuit is designed in the second part of the thesis work.
The proposed bandgap circuit is capable of generating a reference voltage of 0.730V. The
circuit is implemented in 0.18µm standard CMOS technology and operates with 0.9V
supply voltage, consuming 5µA current. The circuit achieves 7 ppm/oK of temperature
coefficient with supply voltage range from 0.9 to 1.5V and temperature range from 0 to
60o C.
1
2
Acknowledgements
First I would like to thank my supervisor and examiner Professor Atila Alvandpour for
giving the opportunity to do this project work and giving me valuable guidance and for
the helpful discussions during the thesis work.
I am grateful to all members of Electronic Devices Group, Linköping University for their
encouragement and support throughout my thesis work.
I would like to thank my class mate Ameya Bhide for the helpful discussions during the
thesis period.
Last, but not the least, I would like to express my deep gratitude to my parents for their
encouragement and support to my studies in Sweden.
3
4
Table of Contents
ABSTRACT .................................................................................................................................................. 1
ACKNOWLEDGEMENTS ......................................................................................................................... 3
TABLE OF FIGURES ................................................................................................................................. 7
LIST OF TABLES........................................................................................................................................ 9
1
INTRODUCTION............................................................................................................................. 11
1.1
1.2
1.3
2
TERMINOLOGY AND DEFINITIONS ........................................................................................ 13
2.1
2.2
2.3
2.4
2.5
2.6
3
DYNAMIC THRESHOLD MOS (DTMOS) TRANSISTORS.............................................................. 25
CMOS BGR USING RESISTIVE SUB-DIVISION ........................................................................... 27
BGR USING TRANSIMPEDANCE AMPLIFIER ............................................................................... 29
BGR USING DEPLETION TRANSISTORS ...................................................................................... 30
DISADVANTAGES OF BGR CIRCUIT............................................................................................ 32
BGR CIRCUIT USING BULK BIASING ......................................................................................... 33
THRESHOLD VOLTAGE BASED VOLTAGE REFERENCE ............................................................... 34
PROPOSED LOW VOLTAGE LOW POWER BGR................................................................... 35
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.3
5.4
6
DERIVATION OF THE TEMPERATURE INDEPENDENT VOLTAGE ................................................... 17
CMOS BANDGAP REFERENCE CIRCUITS.................................................................................... 20
SOLVING THE OFFSET ERROR ...................................................................................................... 22
CASE STUDY OF LOW VOLTAGE CMOS BANDGAP CIRCUITS ....................................... 23
4.1
4.2
4.3
4.4
4.5
4.6
4.7
5
BANDGAP VOLTAGE................................................................................................................... 13
PTAT VOLTAGE ........................................................................................................................ 13
CTAT VOLTAGE ........................................................................................................................ 13
BANDGAP REFERENCE CIRCUIT (BGR)...................................................................................... 13
VBE VOLTAGE ............................................................................................................................ 13
PARTS PER MILLION (PPM)......................................................................................................... 14
BANDGAP VOLTAGE REFERENCE PRINCIPLE.................................................................... 15
3.1
3.2
3.3
4
ZENER BASED VOLTAGE REFERENCES ....................................................................................... 11
BANDGAP VOLTAGE REFERENCE ............................................................................................... 12
ADVANTAGES OF BANDGAP REFERENCE CIRCUIT ...................................................................... 12
BANDGAP REFERENCE CIRCUIT ................................................................................................. 36
WORKING ................................................................................................................................... 36
PTAT Voltage Generation .................................................................................................... 37
Operational Amplifier........................................................................................................... 41
Power Supply Independent Biasing ...................................................................................... 43
Startup Circuit ...................................................................................................................... 45
Curvature Compensation...................................................................................................... 47
DESIGN CHOICES AND SIMULATED RESULTS ............................................................................. 49
CONCLUSION .............................................................................................................................. 53
REFERENCES.................................................................................................................................. 54
5
6
Table of Figures
FIGURE 1 HYPOTHETICAL BANDGAP REFERENCE CIRCUIT ........................................................................... 16
FIGURE 2 CONVENTIONAL BIPOLAR BANDGAP REFERENCE CIRCUIT ............................................................ 16
FIGURE 3 VARIATION OF VREF WITH TEMPERATURE ..................................................................................... 19
FIGURE 4 A) VERTICAL NPN TRANSISTOR B) VERTICAL PNP TRANSISTOR ................................................... 20
FIGURE 5 TYPICAL CMOS BANDGAP REFERENCE CIRCUIT .......................................................................... 21
FIGURE 6 OFFSET ERROR COMPENSATION USING CHOPPED OPERATIONAL AMPLIFIER ................................ 22
FIGURE 7 CURRENT SUMMING BGR ............................................................................................................. 23
FIGURE 8 VOLTAGE SUMMING BGR ............................................................................................................. 24
FIGURE 9 A) VREF VS. VDD B) VREF VS. TEMPERATURE ................................................................................... 25
FIGURE 10 DTMOS CROSS SECTION ............................................................................................................. 26
FIGURE 11 DTMOS BGR CIRCUIT ............................................................................................................... 26
FIGURE 12 DTMOS BGR TEMPERATURE DEPENDENCE ............................................................................... 27
FIGURE 13 BGR BASED ON RESISTIVE SUB DIVISION .................................................................................... 27
FIGURE 14 VREF VARIATION IN [11]............................................................................................................... 28
FIGURE 15 BGR CIRCUIT WITH IMPROVED NOISE IMMUNITY ........................................................................ 29
FIGURE 16 BGR CIRCUIT USING TRANSIMPEDANCE AMPLIFIER [7] ............................................................. 29
FIGURE 17 WEAK INVERSION PMOS OPERATIONAL AMPLIFIER ................................................................... 31
FIGURE 18 NMOS OPERATIONAL AMPLIFIER USING LEVEL SHIFTERS ......................................................... 31
FIGURE 19 OPERATIONAL TRANSCONDUCTANCE AMPLIFIER ........................................................................ 33
FIGURE 20 THRESHOLD VOLTAGE BASED VOLTAGE REFERENCE ................................................................ 34
FIGURE 21 CMOS BANDGAP REFERENCE CIRCUIT ....................................................................................... 35
FIGURE 22 PROPOSED BANDGAP REFERENCE CIRCUIT ................................................................................. 36
FIGURE 23 VARIATION OF PN JUNCTION VOLTAGE WITH TEMPERATURE ....................................................... 37
FIGURE 24 CIRCUIT FOR PTAT VOLTAGE GENERATION ................................................................................ 38
FIGURE 25 PTAT VOLTAGE VARIATION WITH TEMPERATURE ...................................................................... 39
FIGURE 26 BANDGAP CIRCUIT ...................................................................................................................... 39
FIGURE 27 REFERENCE VOLTAGE VARIATION WITH TEMPERATURE ............................................................ 41
FIGURE 28 OPERATIONAL AMPLIFIER ........................................................................................................... 41
FIGURE 29 VA, VB AND VREF VARIATION WITH SUPPLY VOLTAGE ................................................................ 42
FIGURE 30 A) BLOCK DIAGRAM OF SELF BIASED REFERENCE B) REGIONS OF OPERATION ............................. 43
FIGURE 31 VREF VARIATION WITH SUPPLY VOLTAGE .................................................................................... 44
FIGURE 32 OPERATING POINTS OF OPERATIONAL AMPLIFIER ....................................................................... 45
FIGURE 33 STARTUP CIRCUIT ........................................................................................................................ 46
FIGURE 34 A) CURRENT THROUGH TRANSISTOR M6. B) CURRENT THROUGH M4......................................... 46
FIGURE 35 BGR CIRCUIT WITH CURVATURE COMPENSATION ...................................................................... 48
FIGURE 36 VREF VARIATION AFTER CURVATURE COMPENSATION ................................................................. 49
FIGURE 37 A)VREF VARIATION WITH TEMPERATURE B)VREF VARIATION AFTER CURVATURE COMPENSATION
............................................................................................................................................................ 51
FIGURE 38 VREF VARIATION WITH SUPPLY VOLTAGE .................................................................................... 51
FIGURE 39 REFERENCE VOLTAGE VARIATIONS FOR DIFFERENT SUPPLY VOLTAGES....................................... 52
7
8
List of Tables
TABLE 1 CURRENT SUMMING BGR............................................................................................................... 24
TABLE 2 DTMOS BGR................................................................................................................................. 25
TABLE 3 BGR BASED ON RESISTIVE SUB DIVISION ....................................................................................... 28
TABLE 4 BGR USING TRANSIMPEDANCE AMPLIFIER .................................................................................... 30
TABLE 5 BGR USING DEPLETION TRANSISTORS ........................................................................................... 30
TABLE 6 THRESHOLD VOLTAGE BASED VOLTAGE REFERENCE ..................................................................... 34
TABLE 7 OPERATIONAL AMPLIFIER FEATURES ............................................................................................. 43
TABLE 8 COMPONENT VALUES OF BGR CIRCUIT.......................................................................................... 50
TABLE 9 MEASURED RESULTS ...................................................................................................................... 52
TABLE 10 RESULT COMPARISON ................................................................................................................... 53
9
10
1 Introduction
Precision voltage reference circuits are necessary for accurate working of mixed and
analog integrated circuits such as oscillators, PLLs, Data Converters and Dynamic
Random Access Memories (DRAM’s). These voltage references should be insensitive to
variations in process, temperature and supply voltage. The performance of many mixed
analog/digital systems is limited by inaccuracies and power supply noise coupling errors
in integrated voltage references [1, 20]. So precision voltage reference circuits forms an
integral part of almost all integrated circuit designs.
Some of the desired characteristics of a voltage reference circuit areSilicon implementable
Stable and accurate
Independent of output loading
Insensitive to power supply variations (especially for battery operated devices)
Insensitive to temperature
Most popular reference voltage generators areZener-based Voltage References
Bandgap Voltage References
1.1 Zener Based Voltage References
Zener-based temperature compensated voltage reference circuits were popular few years
back. However these devices have breakdown voltages greater than 6V, which puts a
lower limit on the supply voltage requirements. Further, they require tight process control
to maintain a given tolerance, and they are relatively noisy [1, 21]. So mainly because of
the power supply requirements zener-based voltage references are no more popular in the
latest integrated circuits.
11
1.2 Bandgap Voltage Reference
Bandgap voltage reference circuit uses the negative temperature coefficient of emitter
base voltage in conjunction with the positive temperature coefficient of emitter-base
voltage differential of two transistors operating at different current densities to make a
zero temperature coefficient reference. Bandgap reference circuits gained popularity for
the reasons discussed below
1.3 Advantages of Bandgap Reference circuit
The base-emitter voltage of a bipolar transistor is most predictable and well
understood parameter.
Temperature insensitive.
Can operate at low supply voltages.
Capable of producing “arbitrary” output voltages.
Circuit can be easily incorporated in a monolithic IC design.
Advances in sub-micron CMOS processes resulted in supply voltages getting scaled and
latest process operate at sub 1V supply voltage. Further, increased demand for battery
powered portable devices and low-power designs require low supply voltages. This trend
presents a great challenge in designing bandgap reference circuits which can operate at
very low voltages.
Work done in this thesis is classified into two sections:1. Comprehensive study of existing bandgap reference circuits and understand the
limitations in implementing these designs in processes with sub 1V supply.
2. Modeling a Low-Voltage, Low-Power Bandgap Reference Circuit.
12
2 Terminology and Definitions
A brief explanation of frequently used terms in this document are given here-
2.1 Bandgap Voltage
Bandgap voltage refers to the voltage difference between the valence band and
conduction band of the semiconductor material, which has a constant value and its
variation with temperature, is significantly less.
2.2 PTAT Voltage
PTAT stands for Proportional to Absolute Temperature Voltage, meaning the
variations in voltage is proportional to temperature, or voltage increases with
temperature.
2.3 CTAT Voltage
CTAT stands for Complementary to Absolute Temperature Voltage, meaning the
variations in voltage is complementary to temperature, or voltage decreases with
increase in temperature.
2.4 Bandgap Reference Circuit (BGR)
BGR is a precision voltage reference circuit, in which the negative temperature
dependency of a voltage source is cancelled by the positive voltage dependency of
another voltage source, resulting in a stable voltage at the reference temperature
which is equal to the bandgap voltage of the semiconductor at the reference
temperature.
2.5 VBE Voltage
It is the potential drop across a forward biased diode connected bipolar junction
transistor (BJT)
13
2.6 Parts Per Million (ppm)
Reference-accuracy unit used commonly with precision voltage reference designs.
Designers typically use this measure to specify temperature coefficients and other
parameters that change little under varying conditions. For a 2.5V reference, 1ppm is
one-millionth of 2.5V, or 2.5µV. If the reference is accurate to within 10ppm, then it is
extremely good performance for any voltage reference.
14
3 Bandgap Voltage Reference Principle
By definition bandgap reference circuit is a voltage reference circuit, the output of which
is equal to the bandgap voltage of the semiconductor used. The first bandgap reference
circuit was proposed by Robert Widlar in 1971 [1]. This circuit was implemented in the
conventional junction isolated bipolar technology, to make a stable low voltage reference
of 1.26V, which is the bandgap voltage of silicon at room temperature (25oC).
Early implementation of these voltage references were based on the difference between
the threshold voltages of enhancement and depletion mode MOS transistors [2]. This
provides low temperature coefficient (TC) but the drawback being the output is not easy
to control because of the direct dependence on the doses of ion implantation steps and
further depletion mode transistors are not available in most of the CMOS processes.
So in modern processes the implementation principle of bandgap voltage reference is to
cancel the negative temperature coefficient(TC) of a pn junction (In practice the base
emitter voltage of a bipolar transistor (VBE)) with the positive temperature
coefficient(TC) of a thermal voltage given by VT =
kT
, where ‘k’ is Boltzman’s constant,
q
‘T’ the absolute temperature and ‘q’ the electron charge. This principle is illustrated in
Fig.1 [4].
It is well understood that the pn junction voltage (VBE) is nearly complementary to
absolute temperature(CTAT) meaning it decreases (≈ -2mV/
0
C) almost linearly with
temperature [3]. It is also noted that VBE is equal to the bandgap voltage (VG0) of the
semiconductor, in a first order approximation extrapolated to absolute zero. If another
voltage equal in magnitude to VBE but proportional to absolute temperature (PTAT) is
summed with VBE, we obtain a voltage equal to VG0. In this way a well defined voltage
reference in generated which is independent of temperature. The resulting reference
voltage will have a temperature coefficient of around 10ppm/ 0 K.
15
Figure 1 Hypothetical Bandgap Reference Circuit
A PTAT voltage can be obtained through the difference of two VBEs biased at different
current densities. The relation is given by
⎛ JC2 ⎞
∆ VBE = VBE1 - VBE2 =VT ln ⎜ ⎟
⎝ JC1 ⎠
(1)
JC2 and JC1 being the current densities of VBE junctions. Typical bipolar implementation
[4] of the bandgap reference circuit is given in Fig. 2.
Figure 2 Conventional Bipolar Bandgap Reference Circuit
16
3.1 Derivation of the Temperature Independent Voltage
Conditions for temperature compensation can be derived starting with the V-I
relationship of a forward biased base emitter junction of a bipolar transistor given by
Ic = Ise
⎛ qV BE ⎞
⎜
⎟
⎝ kT ⎠
where IS is the saturation current of the transistor. The complete equation for the base
emitter voltage (VBE) of a transistor is given by
T ⎞
⎛
⎛ T ⎞ nkT ⎛ T ⎞ kT ⎛ Ic ⎞
ln ⎜ ⎟
ln ⎜ ⎟
VBE = VG 0 ⎜1 − ⎟ + VBE 0 ⎜ ⎟ +
q
⎝ T0⎠
⎝T0 ⎠
⎝ T 0 ⎠ q ⎝ Ic 0 ⎠
(2)
where VG 0 is the extrapolated bandgap voltage of the semiconductor material at absolute
zero temperature, q the charge of an electron, n is a process constant (equals 1.5 in most
processes), k Boltzman’s constant, T is absolute temperature, Ic is collector current and
VBE 0 is the base emitter voltage at temperature T 0 [4]. The last two terms in (2) can be
ignored as they are quite small and can be made even smaller by making Ic vary with
absolute temperature. This is the CTAT voltage.
We have already seen how to generate a PTAT voltage and the expression for a PTAT
voltage is given by
⎛ JC2 ⎞ kT ⎛ Jc 2 ⎞
∆ VBE = VBE1 - VBE2 = VT ln ⎜ ⎟ =
ln ⎜
⎟
q ⎝ Jc1 ⎠
⎝ JC1 ⎠
Now having both VBE and ∆VBE the temperature independent reference voltage is
obtained by adding (1) to (2) in its simplified form, giving
T ⎞
⎛
⎛ T ⎞ kT ⎛ Jc 2 ⎞
ln ⎜
VREF = VG 0 ⎜1 − ⎟ + VBE 0 ⎜ ⎟ +
⎟
⎝ T0⎠
⎝ T 0 ⎠ q ⎝ Jc1 ⎠
(3)
Differentiating with respect to temperature yields
∂VREF
VG 0 VBE 0 k ⎛ Jc 2 ⎞
=−
+
+ ln ⎜
⎟
∂T
T0
T 0 q ⎝ Jc1 ⎠
(4)
For zero temperature dependence, this quantity should equal zero, giving
VG 0 = VBE 0 +
kT 0 ⎛ Jc 2 ⎞
ln ⎜
⎟
q
⎝ Jc1 ⎠
(5)
17
The first term on the right is the initial base emitter voltage while the second is the
component proportional to the base emitter voltage difference. Hence if the sum of the
two is equal to the bandgap voltage of the semiconductor, the reference will be
temperature compensated. In practice, for minimum drift, it is necessary to make the
output voltage somewhat higher than the theoretical value, in order to compensate for
various low order terms that could not be included in the derivation. However this is only
first order temperature compensation.
Now let us see how this voltage is realized using bipolar transistors (BJT) in Fig. 2.
⎛ I 1.IS 2 ⎞
⎛ R 2.IS 2 ⎞
∆ VBE (ON) = VR3 = VT .ln ⎜
⎟ = VT .ln ⎜
⎟
⎝ I 2.IS 1 ⎠
⎝ R1.IS 1 ⎠
Then, the voltage across R 2 is-
VR 2 VR 3
=
= I2
R 2 R3
VR 2 =
R2
R2
⎛ R 2.IS 2 ⎞
.∆VBE = VT .ln ⎜
⎟
R3
R3
⎝ R1.IS 1 ⎠
Giving the final voltageVREF = VBE1 +
R2
⎛ R 2.IS 2 ⎞
.VT .ln ⎜
⎟
R3
⎝ R1.IS 1 ⎠
VREF = VBE1 + K ∆VBE
(6)
(6) gives the fundamental equation of a bandgap reference circuit, where the
multiplication constant K is set by the ratio of resistors R2 to R3. In the case of silicon, the
value of VREF at 250C is 1.26V. So a bandgap reference circuit at room temperature gives
a reference voltage of 1.26V. The value of multiplication factor can be set either by
resistors R2 or R3 or by the emitter area of bipolar transistors Q1 and Q2.
18
Intuitively, the following things can be observed from (6).
1. The temperature Coefficient (TCF) of VBE is negative while that of VT is positive.
2. Magnitude of both temperature coefficients are not equal so a multiplication
factor K is introduced, which can be either set by ratio R2 of R3, or by the emitter
areas of transistors Q1 and Q2.
3. Op amp ensures that the current flowing through R1 and R2 is the same. This is
achieved by the feedback from output to input.
4. Eq. (6) compensates only first order temperature dependency. Second order
effects arises as the variations in temperature coefficients of the terms in (6) is not
linear throughout the temperature range.
5. One may wonder why we require bipolar transistors in this design, can this not be
done using the MOS transistors, the reason being bipolar transistors are efficient
for biasing it in very low currents in the range of µA and they also have a well
defined VBE. If we had gone for MOS transistors then we may end up in using
very big resistors to reduce current, but thereby consuming more area.
Variation of reference voltage with respect to temperature is shown if Fig. 3.
Figure 3 Variation of VREF with Temperature
19
3.2 CMOS Bandgap Reference Circuits
In most of the CMOS processes independent bipolar transistors are not available. But still
most of the CMOS voltage references also make use of bandgap reference concept. For
this they rely on well transistors [2]. These are vertical bipolar transistors that use wells
as their bases and substrate as their collectors; these are shown in Fig. 4.
Figure 4 a) Vertical NPN transistor b) Vertical PNP transistor
These transistors have high current gains, but their main drawback is the series base
resistance due to the large lateral dimensions between the base contact and the effective
emitter region [5]. To minimize this error the maximum collector current is kept below
0.1mA. Another drawback is the offset voltage due to the resistors used in the design,
20
meaning it’s difficult to fabricate precise value resistors, which leads to large variations
in the output reference voltage and thus degrading the temperature stability of the circuit
[6]. Offset problem can be addressed by laser trimming, that is each resistor can be
individually trimmed to the exact value during fabrication. These issues have to be
addressed while designing a CMOS bandgap reference circuit. A typical CMOS bandgap
reference circuit is shown in Fig. 5.
Figure 5 Typical CMOS Bandgap Reference Circuit
Here the reference voltage is given by,
⎛ A1 ⎞
Vref = VBE2 + VTln ⎜ ⎟
⎝ A2 ⎠
(7)
where A1 and A2 are the emitter areas of Q1 and Q2. Intuitively the first term to right in
(7) is a CTAT voltage and the second term a PTAT voltage. It is also of interest to note
the minimum supply voltage for the operation of this circuit [7]. VDDmin can be expressed
as
VDDmin = VREF + Vdsat (PMOS)
(8)
For most designs VREF = 1.26V and Vdsat (PMOS) can vary from 0.1 to 0.3V depending on
the process, so theoretically the minimum supply voltage is around 1.4V.
21
3.3 Solving the offset error
As mentioned the main concern in CMOS bandgap references is the offset problem, this
considerably reduces the accuracy of the output voltage, though laser trimming is a
solution it is enormously expensive. Paper [8] shows that the dominant term of the output
voltage is indeed a function of the offset voltage, so to achieve improved accuracy offset
error has to be reduced. Switched capacitor operational amplifiers is a solution, another
solution using a chopped operational amplifier is presented in [8]. They propose the
circuit in Fig. 6.
Figure 6 Offset Error Compensation using Chopped Operational Amplifier
Transistors M10, M11, M13, and M15 act as input choppers of the applied voltage
difference at IN+ and IN-. The offset from M2 and M3, the input pair, as well as the
offset from the current mirror pair, M6 and M7, are cancelled by the second chopper,
M19, M20, M21, and M22. Due to the transposition at the third chopper M27, M28,
M29, and M30 the offset of the current sources M12 and M13 are also eliminated. Thus
M31 provides the bandgap referenced output voltage. Simulations show that the use of
chopping techniques reduces the spread of the output voltage to 3.2mV as compared to
32mV without chopping. The total power consumption is measured to be 7.5µW.
22
4 Case Study of Low Voltage CMOS Bandgap Circuits
Supply voltage is scaling and increased demand for low power portable devices has
necessitated the design of sub 1V reference circuits. The BGR topologies discussed till
now gives a non scalable reference voltage of approximately 1.26V. The feasibility of a
sub 1V BGR is investigated in [9], where they propose two different techniques. The first
technique operates by summing two currents with opposite temperature dependence on a
resistor, and the resistor value further controls the reference voltage. The second
technique sums two voltages that are first attenuated, where resistive voltage dividers are
used for the determination of the attenuation factor. The circuit that sums two currents is
given in Fig.7.
Figure 7 Current Summing BGR
Current Summing BGR is composed of three sub circuits. The first generates the PTAT
current; the second mirrors the current to another transistor, which generates the CTAT
component. The last sub circuit consists of a resistor whose function is to sum the
currents and convert it to the desired voltage reference level. The minimum supply
voltage required for correct operation is 0.7, the voltage of the forward biased diode, and
the drain to source voltage of the output transistor of the current mirror driving it. The
drain to source voltage can be as low as 0.2V. In this way a low voltage BGR can be
realized.
23
Figure 8 Voltage Summing BGR
Voltage summing BGR in Fig.8 is also composed of three sub circuits. The only
difference between the current summing BGR and the voltage summing BGR is the third
sub circuit. The third section is composed of a differential amplifier in a non-inverting
feedback loop. The offset voltage from the use of unmatched bipolar transistors generates
the PTAT component. The applied diode voltage is not the full base-emitter voltage, as in
a standard BGR, but a fraction. The minimum supply voltage of one path is VT plus a
VCEsat, plus the source to drain voltage of the current source. The second path’s minimum
supply voltage is a VBE plus the minimum voltage of the current source plus the output
voltage of the VBE generator. This value is equal to 1V with the technology that was used
in this study.
Results of this study are presented in table1 and variations in reference voltage with
supply voltage and temperature is plotted in Fig.9. The output voltage was found to vary
by less the 0.5% over the 0.9V to 2.5V range. In the same range the temperature
dependence varied by 2%.
Table 1 Current Summing BGR
Technology
Flash Memory
Supply Voltage Ref. Voltage
1V
800mV (variable)
Temperature Coefficient
8ppm
24
Figure 9 a) VREF vs. Vdd b) VREF vs. Temperature
4.1 Dynamic Threshold MOS (DTMOS) Transistors
Another technique employed in the design of low voltage BGR design is through the use
of dynamic threshold MOS (DTMOS) devices [10]. As we have seen the bandgap for low
power applications can be made to appear smaller through resistive subdivision, but it is
at the expense of area. The bandgap voltage can also be made to appear smaller if the
diode junction is in the presence of an electrostatic field. This method can be
implemented by replacing the normal diodes with MOS diodes that have interconnected
gates and back gates. These devices are DTMOS devices; a cross-section is shown in
Fig.10. The use of a P-DTMOS device results in a VG0 of 0.6V and the temperature
gradient is approximately –1mV/K. These values are half the typical values of a standard
BGR. Overview of this topology is given in table 2.
Table 2 DTMOS BGR
Technology
0.35µm (DTMOS)
Supply Voltage Ref. Voltage
900mV
815mV (variable)
Temperature Coefficient
9ppm
25
Figure 10 DTMOS cross section
A DTMOS BGR can be designed using the same topology as that of a standard CMOS
BGR. Fig. 11 explains such a circuit. The circuit consists of a folded cascode operational
amplifier and matched resistors with unequal value. The DTMOS diodes are shown with
the gate-back gate connection. The input stage also utilizes DTMOS transistors, which
allows operation at low supply voltages. The op amp’s output stage, shaded, uses a low
voltage current mirror. Correct operation of this op amp was verified for supply voltages
down to 0.7V. The circuit’s temperature dependence is shown in Fig.12. The variation
over the range, -20°C to 100°C, is just 4.5mV.
Figure 11 DTMOS BGR Circuit
26
Figure 12 DTMOS BGR Temperature dependence
4.2 CMOS BGR Using Resistive Sub-Division
Another low voltage BGR circuit is proposed in [11]. Topology presented in this paper
has been employed in many of the low voltage bandgap reference circuits with
modifications. Their circuit topology is shown in Fig. 13. Here the diodes can be replaced
by PnP transistors available in latest processes.
Figure 13 BGR based on resistive sub division
Here the reference voltage is given by,
VREF =
R4
VREF _ CONV
R2
27
where VREF _ CONV is the conventional BGR voltage. So by suitable selection of resistor
values R4 and R2, lower reference voltages than the conventional one can be achieved.
Experimental result for this circuit is given in Fig. 14. The circuit was designed for a
reference voltage of 515mV. VREF showed a variation of 515mV ± 1mV for the supply
variation of 2.2 to 4 V at 27°C; and 515mV ± 3mV for temperature variation from 27 to
125°C. However the minimum supply voltage was limited to 2.1V. Summary of the
design is given in table 3.
Figure 14 VREF variation in [11]
Several modifications were proposed to the circuit presented in [11]. [12] proposes the
use of cascode devices to improve the output impedance of the current sources, by
increasing the output impedance of current sources, sensitivity of VREF to supply noise is
reduced. Resistors R1 and R2 of Fig.13 are replaced with series equivalents. The addition
of nodes V3 and V4 improve the ability of the op amp to operate in sub 1V conditions.
The proposed circuit is given in Fig. 15. The circuit was simulated through 20°C to
100°C and supply voltages of 0.95V to 1.50V. The curves are found to have a spread of
less than 0.24%.
Table 3 BGR Based on Resistive sub division
Technology
Flash Memory
Supply Voltage Ref. Voltage Temperature Coefficient
2.1
560mV
8ppm
28
Figure 15 BGR Circuit with improved noise Immunity
4.3 BGR Using Transimpedance Amplifier
[7] further modified the circuit in [11] by using resistors in place of the input differential
stage of the operational amplifier. This circuit is given in Fig. 16.
Figure 16 BGR Circuit Using Transimpedance Amplifier [7]
Here they obtain a PTAT current by sensing the voltage difference; this current is
summed with a current complementary to VBE to obtain the reference voltage. This is
achieved with the help of a transimpedance amplifier. Vref of this circuit is given by
29
⎡1
⎛ A1 ⎞ VBE 2 Vb ⎤
− ⎥
VREF = R 3. ⎢ .VT ln ⎜ ⎟ +
⎝ A2 ⎠ R 2 R 2 ⎦
⎣ R1
Similar to [11] the value of Vref can be changed by choosing different values of R1, R2,
and R3. Experimental results for a Vref of 1V were shown to be accurate within ±1% over
0°C to 100°C, with R1 untrimmed and ±0.3% after trimmed. Summary of the design
given in table 4.
Table 4 BGR Using Transimpedance Amplifier
Technology
1.2µm BiCMOS
Supply Voltage Ref. Voltage Temperature Coefficient
1.4V
1.2V
7ppm
4.4 BGR Using Depletion Transistors
[13] also suggests improvements to the circuit in [11]. The motivation for the
improvements is that the differential amplifier in [11] has MOS depletion transistors in
the input stage. These devices are not used in standard processes and result in higher
process costs. PMOS transistors in weak inversion are proposed in place of the depletion
mode transistors of [11]. The new circuit is shown in Fig. 17. As the supply voltage is
decreased below 1.4V the input devices enter weak inversion. The BGR remains biased
correctly as long as the supply is above 0.9V, below which the loop gain is insufficient
and the operational amplifier fails to function.
Table 5 BGR Using Depletion Transistors
Technology Supply Voltage Ref. Voltage
0.350µm
1.2V
515mV (variable)
Temperature Coefficient
7ppm
30
Figure 17 Weak Inversion PMOS Operational Amplifier
A second circuit (Fig. 18) proposed uses an NMOS topology with PMOS level shifters to
provide the correct common mode voltage to the input stage. The circuit is unable to
operate with a supply voltage as low as the first, but it does not require a startup circuit
for correct biasing at power-on. The supply voltage is limited to approximately 1.4V.
Summary of the design given in table 5.
Figure 18 NMOS Operational Amplifier using Level Shifters
Studying these low voltage bandgap reference circuits following things can be observed.
The technique used for the design of conventional bandgap circuits can also be extended
to the design of low voltage temperature independent circuits. Still the circuits bear the
31
name bandgap, though the reference voltage is not equal to the silicon bandgap because
the idea used for implementing these low voltage circuits is same that of conventional
design, i.e. to cancel the CTAT dependency with a PTAT dependency. Sub 1V BGR
designs require a minimum supply voltage of 700mV, which is the saturation voltage of
the diode connected transistors used (BJT). Further this minimum voltage is also
dependent on the operational amplifier design. We need to ensure that this minimum
voltage is sufficient for the proper operation of the operational amplifier. Careful
understanding of the circuits reveals that low voltage reference circuit designs are mainly
limited by the voltage requirements of the operational amplifier. Paper [12] is an
example. We have already seen, this topology can give very low temperature independent
reference voltage, but the operational amplifier requires a minimum supply voltage of
1.5V. So design of operational amplifiers which can give significant gain at low supply
voltages should be the main design motto.
Design of low voltage reference circuits has start up issues. Since the voltage levels are
low we need to ensure that the circuit is getting properly biased on start up. This start up
circuits should be designed in such a way that once the circuit gets stabilized, it should
not further influence the circuit operation.
Circuits discussed till now compensates first order temperature dependency, second order
dependency arises as the variation in the junction voltage is not linear through out the
operating temperature range. So to compensate second order effects additional circuitry
has to be incorporated in these designs thereby giving high precision voltage references.
So to conclude this study, the main disadvantages of BGR circuit are given below.
4.5 Disadvantages of BGR Circuit
Additional blocks needed to ensure a non-zero output voltage viz. star-up
Accuracy of models is limited- trial and error technique required
Voltage supply has to be higher than the “bandgap” voltage.
32
4.6 BGR Circuit Using Bulk Biasing
If we want designs to operate below 700mV, then with existing processes it is not
possible as the BJT requires at least 700mV to remain in saturation. Further as we don’t
have well defined voltages, designs based on conventional techniques are not possible.
Alternate techniques have to be explored. Paper [14], [15] discusses issues related to
design of voltage references that can work at sub 0.6V supply.
Paper [14] discusses bulk biasing to reduce the threshold voltage of PMOS and NMOS
transistors and it uses operational transconductance amplifier (OTA) in place of the
conventional operational amplifier. Fig. 19 shows the proposed OTA. In this circuit,
vertical bipolar transistors are replaced by MOSFETs operating in the weak inversion
mode, thereby reducing the VBE voltage drop from 0.7 to 0.2. Bulk biasing is the
technique by which we forward bias the source bulk junction to reduce the threshold
voltage.
Figure 19 Operational Transconductance Amplifier
33
4.7 Threshold Voltage Based Voltage Reference
Paper [15] introduces the new concept of threshold voltage based voltage references. The
basic idea here is to compensate the temperature dependency of the threshold voltage
(VT) of a PMOS transistor with that of an NMOS transistor, both having a CTAT
dependency. This concept is pictorially shown in Fig. 20. The performance of the
proposed voltage reference is shown to be comparable to bandgap circuits, but at the cost
of more area and complexity.
Figure 20 Threshold Voltage Based Voltage Reference
Table 6 Threshold Voltage Based voltage Reference
Technology Supply Voltage Ref. Voltage Temperature Coefficient
0.5µm
4.5V
2.6V
9ppm
34
5 Proposed Low Voltage Low Power BGR
Proposed design is motivated by the requirement of a precision voltage reference that can
work at low supply voltage. It also incorporates a simple technique to compensate for the
second order temperature dependency. The circuit topology is quite similar to the one
discussed in [18], which was implemented in a 0.8µm BiCMOS process. The design is
optimized for low power, low voltage applications.
Let us now consider a typical CMOS bandgap reference circuit as given in Fig. 21.
Figure 21 CMOS Bandgap Reference Circuit
Its working is explained in the briefest terms. This circuit relies on two bipolar transistors
(Q1 and Q2) working at different emitter current densities. The rich transistor (Q2) will
run at typically 8 times the current density of the lean one (Q1). This factor of 8 will
cause typically around 60mV delta (∆VBE) between the base emitter voltages of these two
transistors. This delta voltage is amplified by a factor of around 5 and added to the
forward biased pn junction voltage (VBE). These two voltages add up to 1.25V, which is
approximately the bandgap voltage of silicon at room temperature given by
⎛ A1 ⎞
Vref = VBE2 + VTln ⎜ ⎟
⎝ A2 ⎠
(9)
35
where A1 and A2 are current densities of transistors Q1 and Q2. As we have already seen
the first term to the right in (9) is a CTAT voltage while the second term is a PTAT
voltage.
5.1 Bandgap Reference Circuit
Fig.22 shows the proposed bandgap reference circuit. It is different from the conventional
design (Fig.21.), as the PTAT voltage generated across R1 is mirrored to a diode
connected transistor B4 to generate a temperature independent reference voltage, whose
value can be easily set by the resistor ratio of R3 to R2.
Figure 22 Proposed Bandgap Reference Circuit
5.2 Working
Let us break the circuit and see the working part by part. The variation in voltage with
respect to temperature across a pn (VBE) junction is given by
Eg
∂VBE ∂VT IC VT
VT
=
ln − −
IS IS kT 2
∂T
∂T
36
where VT is the thermal voltage given by VT = kT / q, where k is Boltzman’s constant, T
the absolute temperature and q the electron charge [5]. In this design for a supply voltage
of 1V and temperature at 25 oC VBE = 700mV giving
∂VBE
≈ -1.5mV⁄ oK.
∂T
This variation is shown in Fig. 23. This negative TC voltage has to be compensated by a
positive TC voltage.
Figure 23 Variation of pn junction voltage with temperature
5.2.1 PTAT Voltage Generation
This positive TC voltage comes from the voltage difference of two pn junctions (VBE1
and VBE2) having different current densities, given by
VBE1 − VBE 2 = ∆VBE = VT ln
IC
IC
− VT ln
= VT ln n ,
IS
nIS
(10)
where n is the current density ratio of B2 to B1 [5]. In our design this is achieved through
an emitter area ratio of 8 and setting the currents through B1 and B2 equal. Operational
amplifier sets the emitter currents of B1 and B2 equal. Therefore voltage across R1
equals ∆VBE and the current flowing through R1 is proportional to temperature (PTAT).
This set up is shown in Fig. 24.
37
Figure 24 Circuit for PTAT voltage Generation
To reduce power, the current flowing through transistor (B1 and B2) is limited to 1µA.
The high gain of the operational amplifier sets the voltage across nodes A and B equal
giving,
⎛ Ic ⎞
VA = VB = VBE1 = VBE2 + I1 x R1 where VBE1 = VTln ⎜ ⎟
⎝ Is ⎠
Therefore VBE1- VBE2 = VTln (n) = I1 x R1. Where n is 8. So the voltage across R1 is the
positive TC voltage. The current across R1 is
VT ln n
which is proportional to absolute
R1
temperature (PTAT) current. So the current can be easily controlled by adjusting the
value of R1. Variation of PTAT voltage with temperature is shown in Fig.25. It’s
interesting to note that the variation with temperature in PTAT voltage is not at the same
rate as that of the CTAT voltage.
38
Figure 25 PTAT voltage variation with Temperature
The complete circuit to generate bandgap reference voltage is shown in Fig. 26.
Figure 26 Bandgap Circuit
39
So the PTAT current flowing through resistor R1 is mirrored to diode connected transistor
B4 using current mirror M4. The output voltage is formed across R2 and B4 by adding
the positive TC voltage (I2R2) to the negative TC voltage (VBE4), resulting in a
temperature independent voltage at the reference temperature of 25oC. So the reference
voltage (voltage across R2 and B4) is given by
VREF = VBE 4 +
VT ln( n)
R 2 = 1.26V
R1
(11)
using (10), equation (11) can be rewritten as
VREF = VBE4 + K ∆VBE
(12)
where K is set by the ratio of R2 to R1. Further VREF can also we written as
VREF = VBE4 + I2R2
(13)
The base emitter voltage is 0.7V at 25oC. We can set the PTAT current flowing through
R2 to be 1µA. Therefore, from equation (13) the resistance R2 can be determined by
R2 =
1.26 − 0.7
≈ 560 K
0.1
This is the first order compensation. The complete equation for the reference voltage is
given by [5]
VREF = VG 0 +
T
kT 0
(VBE1 − VG 0 ) + ( m +η −1) + KVT ln n
T0
q
(14)
where VG0 is the bandgap voltage of silicon at 0o K, m is the temperature constant ≈ 2.3
and η is the correction term due to temperature dependency of the diffusion resistors
used, T0 is the reference temperature and VBE1 is the junction voltage of B1 at reference
temperature. The addition of resistor R3 further changes the reference voltage value to
VREF = K ' (VBE 4 + IM 4 R 2 )
where K ' =
(15)
R3
. So by setting the value of R3 the reference voltage can be easily set.
R 2 + R3
For this design the reference voltage is set as 0.730V. Reference voltage variation with
temperature is shown in Fig. 27.
40
Figure 27 Reference Voltage Variation with Temperature
5.2.2 Operational Amplifier
We have already seen design of low voltage bandgap voltage reference circuits are
constrained by the power supply requirements of the operational amplifier. In this design
operational amplifier is designed to operate at sub 1V. Fig.28. shows the circuit
schematic of the operational amplifier.
Figure 28 Operational Amplifier
41
It is composed of transistors M8 to M14. The purpose of the operational amplifier is to
force node A and B in Fig.26 to same voltage. This is achieved by the high gain of the
circuit and the feed back mechanisms that is formed around it. The operational amplifier
has nmos input stage as the input voltage is nearer to Vdd, with current mirror load. The
output Vb provides the bias for the entire circuit and a feedback loop is also formed. This
ideally provides constant Vgs to all pmos transistors and a constant current can be
obtained. The transistor channel lengths are kept fairly large to reduce the effect of noise
on the output voltage. This design requires a minimum supply voltage of 900mV as
shown in Fig. 29. Operational amplifier details are given in table 6.
Figure 29 Va, Vb and VREF variation with Supply Voltage
In Fig. 29 voltages at node A (Va), B (Vb) and reference voltage (VREF) is plotted against
supply voltage. It is evident from the figure that these voltages take a steady level at a
supply voltage of 900mV. Intuitively only at 900mV, VA equals VB.
42
Table 7 Operational Amplifier Features
Parameter
Value
DC Gain
50dB
Gain Bandwidth Product 1Mhz
Supply Voltage
900mV
Offset voltage
500µV
If supply rejection was the design issue we could have added a cascode stage to the
operational amplifier design, but this would have resulted in higher supply voltage
requirement in order to maintain transistors in saturation.
5.2.3 Power Supply Independent Biasing
Another requirement from a reference voltage generator is the power supply
independence. By which we mean, the reference voltage should not vary with changes in
supply voltage. In our design power supply sensitivity is reduced by so called bootstrap
bias technique also called self biasing [4]. Here instead of developing the input current by
connecting a resistor to the supply, the input current is made to depend directly on the
output current of the current source. This concept is illustrated in Fig. 30.
Figure 30 a) Block Diagram of self biased reference b) Regions of operation
43
Here the important variables are the input current Iin and out put current Iout. From the
standpoint of the current source, the output current is almost independent of the input
current for a wide range of input currents as shown in Fig. 30b. For current mirror Iin is
made equal to Iout as the gain of current mirror is set to unity. So from Fig. 30b it is
evident that the circuit has two operating points A and B. A is the desired operating point
and B is the undesired one as Iin = Iout = 0.
If the output current in Fig. 30a increases for any reason, the current mirror increases the
input current by the same amount because the gain of the current mirror is assumed to be
unity. As a result, the current source increases the output current by an amount that
depends on the gain of the current source. Therefore, the loop responds to an initial
change in the output current by further changing the output current in a direction that
reinforces the initial change. In our design, the current source discussed here is same as
the output of the operational amplifier and the current mirrors being the pmos transistors
M1, M2, M3 and M4 in Fig. 22.
In practice, point B in Fig.30b is a stable operating point. Thus, unless precautions are
taken, the circuit may operate in the zero current condition even when the power supply
voltage is non-zero. This is a drawback of the self-biased circuit. So a startup circuit is
usually required to prevent the self-biased circuit from remaining in the zero current state.
Dependency of reference voltage on supply voltage is shown in Fig. 31.
Figure 31 VREF variation with supply voltage
44
5.2.4 Startup Circuit
In order to ensure proper working of the circuit, we need a mechanism which can provide
a small current to flow through the operational amplifier and enable it during start up.
This is required as we are operating the circuit at low supply voltage [4]. The V-I
characteristic of the operational amplifier is shown in Fig.32. It can be seen that the
circuit has two stable operating points. One in which no current is flowing through the
circuit and the second after the transistors are saturated. So it is possible that during start
up, the circuit may get biased in the operating point, where no current flows through the
circuit. But this can be prevented if we can make a small current to flow through the
circuit during start up.
Figure 32 Operating Points of Operational Amplifier
This is achieved through transistors M5 to M7 in Fig. 33. M5 is a diode connected pmos
transistor which is in saturation; it provides sufficient gate voltage for M6 to turn on.
When M6 is on, a small current flow through the operational amplifier because transistors
M5 and M6 pull down the output node of the operational amplifier, enabling the entire
circuit. Once current starts flowing, M7 is turned on and sinks all current from M5 and
disables M6.
45
Figure 33 Startup Circuit
Transistors M5, M6, and M7 are made weak, so that it won’t influence the operation of
the circuit once the BGR circuit is properly biased. This is shown in Fig. 34.
Figure 34 a) Current through transistor M6. b) Current through M4
46
From Fig.34 it is evident that transistor M4, pulls down the output of the operational
amplifier during startup, thereby making a small current to flow through the operational
amplifier and once the circuit is properly biased as shown by Fig.34b it can be noticed
that the current flow through transistor M4 is negligible. This model of startup circuit has
the drawback as it consumes static power, but is quite simple to implement.
5.2.5 Curvature Compensation
Eq. (12) compensates temperature dependence of the output voltage at the first order
only. Second order effects arises as the variation in VBE is not linear with temperature
throughout the operating range, but it varies according to the relation proposed in [14]
and is given by
VBE (T ) = VG − (VG − VBE 0 )
T
T
− (η − α ) VT ln
T0
T0
(16)
where η is a process parameter and is 4 for this standard CMOS process, while α equals
1 if the current in BJT is PTAT and 0 when the current is temperature independent.
Bandgap architecture shown in Fig.26 corrects the first term in (16) leading to second
order temperature dependence. These effects are generally compensated using operational
amplifiers or switched capacitor structures. However for our design we have considered
techniques given in [10] and [11], as it occupies less area and easy to implement. This
implementation requires an additional current mirror M3, resistors R4, R5 and BJT B4 as
shown in Fig. 35.
47
Figure 35 BGR Circuit with Curvature Compensation
Here the idea is to correct the non linear term by a proper combination of the VBE across a
junction with temperature independent current ( α =0) and the VBE across a junction with
a PTAT current ( α =1). From Fig.35 it is evident that current in bipolar transistors B1
and B2 is PTAT ( α =1), while the current in pmos transistor M3 is first order
temperature independent. If we can inject this current to a diode connected bipolar
transistor B3, across B3 we produce a VBE where α ≈ 0 [11]. So using (16) VBE across B3
and B1, 2 can be expressed as
VBE , B 3(T ) = VG − (VG − VBE 0)
T
T
− ηVT ln
T0
T0
(17)
and
VBE , B1, 2(T ) = VG − (VG − VBE 0)
T
T
− (η − 1)VT ln
T0
T0
(18)
the difference of (17) and (18) lead to the voltage proportional to the non linear term of
(16) given by
VNL ≅ VBE 3(T ) − VBE1, 2(T ) = VT ln
T
T0
(19)
48
where, VNL is the voltage proportional to the non-linear term of (16). Now to achieve
curvature compensation current proportional to VNL is subtracted from the reference
voltage using resistors R4 and R5, which drain current proportional to VNL, leading to the
new equation.
VREF = K ' (VBE 4 + IM 4 R 2 ) +
R1
VNL .
R 4, 5
(20)
The value of R4, R5 which leads to curvature compensation is given by [11]
R 4, 5 =
R1
.
η −1
The variation of reference voltage with temperature after curvature compensation is
shown in Fig.36.
Figure 36 VREF variation after curvature compensation
5.3 Design Choices and Simulated Results
Components B1 to B4 are diode connected vertical PNP transistors readily available in
standard CMOS process. Resistors R1 to R5 are implemented using n well diffusion
resistors. The channel lengths of PMOS transistors are kept large to reduce the effect of
noise and power supply variations on reference voltage. Transistor M4 is designed twice
as large as M2 and M1, thus reducing the size of resistors R2 and R3, because of more
49
current drive. The values of components are presented in table7. The values are
optimized using Cadence® Affirma™ Simulation Tool.
Table 8 Component Values of BGR Circuit
Component Name
M1,M2,M3
M4
M5,M6
M7
M8,M9
M10,M11
M12,M13
M14
R1
R2
R3
R4
R5
Q1,Q2,Q3,Q4
(Emitter Area)
W/L Value in µ meter
240/7
500/7
2/8
2/5
25/7
20/4
25/4
50/7
88K
516K
900K
25K
35K
1,8,1,8
The variation in reference voltage of the BGR with and without curvature compensation
is given in Fig.37. The temperature variation is measured for a 900mV supply and for a
temperature range of 0 to 60 oC. The circuit achieves a temperature coefficient of
7ppm/oK. The variation in Vref with supply voltage is plotted in Fig. 38. The supply
voltage is varied from 0.9 to 1.5V. The supply voltage dependence is found to be
300ppm/V. This can be further improved if we can incorporate a cascode stage in the
operation amplifier design, but at the cost of a higher supply voltage, which was not the
focus of this design.
50
Figure 37 a)VREF Variation with temperature b)VREF Variation after curvature compensation
Figure 38 VREF variation with supply voltage
Variation in reference voltage with temperature, for supply voltage in the range 0.9-1.5V
is plotted in Fig 39. Summary of the measured results are given in table 8. Further
improvement in performance is possible if we increase the transistor sizes and reduce the
offset error of the operational amplifier.
51
Figure 39 Reference voltage variations for different supply voltages.
Table 9 Measured Results
Parameter Measured
Value
Supply voltage range
Vref
Power consumption
Temperature Variation(0-60oC)
Without compensation
With Compensation
Dependence on Supply voltage
0.9-1.5V
0.730V
5µW
400µV →14ppm/K
200µV →7ppm/K
220µV/V→300ppm/V
52
5.4 Conclusion
In this work effort is made to understand various topologies of the existing bandgap
reference circuits and identify the limitations why these circuits are difficult to be used
with current processes, mainly with sub 1V technologies. Through the ideas obtained out
of this study, we have designed and analyzed a curvature compensated fully CMOS
bandgap reference circuit, in 0.18µm standard CMOS process. The simulated results are
presented. Results show substantial reduction in power when compared to the reference
design, which was implemented in 0.8µ meter BiCMOS technology. The circuit achieves
a temperature coefficient of 7ppm//oK and supply voltage dependence of 300ppm/V.
Comparison of the results with the reference design is presented in table 9.
Table 10 Result Comparison
Parameter Measured
Reference Design
Current Value
Power Supply Voltage
Technology
Power consumption
Temperature Variation(0-60oC)
Without compensation
With Compensation
Dependence on Supply voltage
Reference Voltage
1.5V
0.8µm BiCMOS
92µW
900mV
0.18 µm CMOS
5µW
800µV →20ppm/K
300µV →7.5ppm/K
114µV →212ppm/V
536mV
400µV →14ppm/K
200µV →7ppm/K
220µV →300ppm/V
730mV
53
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55
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