Status and Trends of
SiGe BiCMOS Technology
David Harame
Manager SiGe BiCMOS Simulation,
Modeling, Design Automation,
Verification, and Release Department
IBM Communications Research and Development Center
Essex Junction, VT
Communications R&D Center
GGF 12/8/99
Outline - Introduction
Introduction
IBM Technology overview
Total Technology Support
SiGe BiCMOS production circuits
Summary
Communications R&D Center
GGF 12/8/99
Graded Base SiGe HBT
Narrow bandgap base
Base "quasi-electric field"
Small ∆EG at E-B jct.
High emitter doping
Medium base doping
Polysilicon emitter
ee-
Si
SiGe
N
EC
EF
P
N
EV
Germanium
Content
Energy(ev)
e-
Emitter
Base
Collector
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GGF 12/8/99
Key Technology Enablers and Issues
Key Enablers: CMOS integration + Passives
High Level Integration differentiates BiCMOS from III-V
CMOS in BiCMOS must exactly match “base” CMOS
HIgh Q passives differentiate technology providers
Monolithic circuits require high Q passives
Key issues: Process Integration
Conflicting CMOS / HBT thermal budget requirements
Addressed with integration methodology
Shrinking CMOS interconnects non-optimal for RF
Specialized metal systems for RF
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GGF 12/8/99
Outline - SiGe Technology
Introduction
Technology overview
SiGe HBT BiCMOS integration
SiGe HBT Differentiators
Passives
Total Technology Support
SiGe BiCMOS production circuits
Summary
Communications R&D Center
GGF 12/8/99
"Base-after-gate" integration flow
Major thermal cycles prior to base deposition
Low thermal-cycle HBT module
CMOS / Common
Shallow Trench Isolation
Bipolar/Analog
Subcollector & n-EPI
Deep Trench Isolation
Collector Plug Implant
FET Well Implants
Dual Gate Oxide & Gate Formation
LDD Implants & Anneals
Spacer Formation
nFET S/D/G Implants
pFET S/D/G Implants
HBT Module:
Bipolar Window Open
SiGe Epi Base Growth
Extrinsic Base, Collector
& Emitter Formation
Source/Drain and Emitter Anneal
Silicide & Contacts
Standard 2 to 6 Metal Layers
– Includes MIM Capacitor
Thick Metal Add-On Module
Ref: S. St Onge, BCTM 99
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Communications R&D Center
Process Flow for 0.25µ
µm SiGe BiCMOS
N- Epi
N- Epi
N+
N+
P-
P-
N+
N
N+
NWell
N+
N-
N+
P-
P-
Gate Poly
N
N+
NWELL
N+
N-
N+
P-
P-
Single Crystal UHV/CVD SiGe Window
N
N+
N+
Poly protect
P
NWELL
P
N+
P-
NPN
N-
P-
PFET
Poly Resistor
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Process Flow for 0.25µ
µm SiGe BiCMOS
N
N+
P
N+
NWELL
P
N+
P-
N
P-
N+
P
N+
NWELL
P
N-
N+
P-
P
N-
P-
P
N
N+
N+
P
NWELL
P
N+
P-
NPN
N-
P-
PFET
Poly Resistor
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Process Flow for 0.25µ
µm SiGe BiCMOS
P
P
N
N+
P
P
NWELL
N+
N+
P-
P
N-
P-
P
N
N+
N+
P
P
NWELL
N+
P-
NPN
N-
P-
PFET
Poly Resistor
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Process Flow for 0.25µ
µm SiGe BiCMOS
P
P
N
N+
P
P
NWELL
N+
N+
P-
P
N-
P-
P
N
N+
N+
P
P
NWELL
N+
P-
NPN
N-
P-
PFET
Poly Resistor
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SiGe HBT Cross Section (0.25µµm SiGe BiCMOS)
Emitter
Intrinsic
Base
Collector
Extrinsic
Base
Deep Trench
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fT comparison
0.18µ
µm generation performance increase 2.5X
Vertical + lateral scaling gives higher performance at
lower power
140
120
VCB = 1V
0.18um
generation
2
1µm
100
0.16µm
fT, GHz
2
80
Lateral
scaling
60
40
Vertical
scaling
0.25 µm
generation
2
0.35µm
0.5 µm
generation
2
1µm
20
0
1E-5
0.0001
0.001
Ic (Amps)
GGF 12/8/99
0.01
0.1
Communications R&D Center
HBT MAG and h21
120 GHz fT
100 GHz fMAX (fit to MAG @ 40-70GHz)
100
MAG, h21**2
0.18x4 junction area
VBE=0.90V VCB=1V
10
h212
MAG
1
10
100
Freq (GHz)
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Communications R&D Center
SiGe Bipolar/BiCMOS Roadmap
3 generations of SiGe Production
CMOS
> 150 GHz / 2.0V
tbd / tbd
0.13um
1.2v
120 GHz / 2.0v
50 GHz / 3.3v
25 GHz / 5.5v
0.18um
1.8v
0.25um
2.5v
Base After
Gate
Integration
50 GHz / 3.3v
29 GHz / 5.5v
8T
BiCMOS Production
7HP
BiCMOS Production
6HP
20 GHz / 9.5v
5MR
0.5um
3.3, 5v
50 GHz / 3.3v 5B0
19 GHz / 7.8v
0.5um
3.3v
Base During
Gate
Integration
45 GHz / 3.3v
25 GHz / 5.5v
Bipolar
50 GHz / 3.3v
29 GHz / 5.5v
5HE
1996
High Speed NPN Ft / BVceo
High Breakdown NPN Ft / BVceo
5HP
BiCMOS Production
Bipolar Production
End Of
Life
1997
Main Technology
1998
1999
Derivative
2000
2001
2002
2003
Production
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Technology Summary Table
Lithography
µm
NPN fT (Hi BV/HP) GHz
0.5
28/45
0.25
28/45
0.18
30/120
NPN fMAX
NPN BVCEO
GHz
V
50/60
5.5/3.3
50/60
5.5/3.3
50/100
5.0/2.1
NPN Density
relative
1x
1.15x
1.52x
Emitter Width
µm
0.42
0.3
0.18
NFMIN
CMOS Supply
dB
V
0.8
3.3
0.8
2.5/ 3.3
0.4
1.8/ 3.3
CMOS Pwr
CMOS Gate Delay
mW/MHz/gt
ps
0.3
90
0.1
50
0.03
33
CMOS Density
relative
1x
4x
7.5x
BEOL M1 Current
Density
BEOL Metal
relative
1x
0.94x
1.5x
Material
Al
Al
Cu
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Differentiator: Performance - fT Range
Epi base and SiGe grading enable 150-200Ghz. HBT performance.
Generations of HBT's are selected by market needs, eg.BVceo.
fT & fmax alone provide no information as to technology advancement.
10
SiGe HBT's
Si BJT's
Gen 5&6 HBT
Gen 7 HBT
Johnson Limit
BVceo(Volts)
8
6
4
2
0
0
20
40
60
Peak F t (Ghz)
GGF 12/8/99
80
100
120
Communications R&D Center
Differentiator: Linearity
Linearity efficiency = OIP3 / PDC
Technology
OIP3 (dBm)
PDC (mW)
Linearity Eff.
IBM SiGe HBT
25
16.2
19.5
GaAs HBT
25
29.1
11
GaAs HEMT
23
20
10
GaAs MESFET
20
60
2
Si BJT (max.
linearity)
27
46
11
Si BJT (max. fT)
22
40
4
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Differentiator: Noise Performance
Excellent NFMIN
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
20
18
solid lines = model
16
14
12
10
8
6
Present (34 µm2, 3 mA, 3 V)
4
Associated Gain (dB)
Min. Noise Figure (dB)
Noise improvements into 0.18µ
µm generation
Next (56 µm2, 10.7 mA, 2 V) 2
0
1
2
3
4
5
6
7
8
9
10
11
0
Frequency (GHz)
Ref: D.R.Greenberg IMS 2000
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Communications R&D Center
Passives Development
Two Modes of Development
New Technology Development
Enhancements on existing technologies
Device
Inductors
Type
Spiral
Capacitors
Poly-Ins-Single xtal
Poly-Ins-Poly
Metal-Ins-Metal
Resistors
Polysilicon
BEOL thin film
Single-crystal diff'n
Varactor
Junction
MOS accumulation
Interconnect
Transmission line
Local interconnect
Issues
Q
Density
Reliability
(Voltage rating)
VCC
Q
Tolerance
TCR
Parasitic C
Current rating
Tuning range
Q
Linearity
CMOS compat.
Electromigration
Loss
Solutions
Thick dielectric module
Thick metal
10-20 Ω-cm substrates
Optimize processes
Offer variety
Process control
Offer variety
Layout options for low C
Offer variety
Layout tradeoffs
captured in models
Low levels - CMOS
Upper levels - thick
Copper
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Metal Layer Stack Comparison
0.25µ
µm
BiCMOS
0.5µ
µm
BiCMOS
0.18µ
µm
BiCMOS
AM
AM
LM
M2
LY
CMOS
scaling
MT
M3
M4
M2
M1
M3
M2
M1
STI
DT
"Analog" metal
levels
STI
DT
M1
CMOS ASIC
compatible
levels
STI
DT
Communications R&D Center
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Typical spiral cross-section and model topology
Inductor Spiral
Via
L1: spiral inductance
Underpass
R1: spiral series resistance
dielectric
height
Si02
C3: spiral to underpass +
turn-to-turn capacitance
Silicon (P-)
C1&C2: spiral to substrate
capacitance
R2&R3: substrate resistance
SPICE
model
C4&C5: substrate capacitance
Communications R&D Center
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Thick metal/dielectric add-on module
100% increase in metal thickness (2µ
µm to 4µ
µm)
75% increase in dielectric thickness (5µ
µm to 8.7µ
µm)
4µm
3µm
Standard
metal
P- substrate (15Ω-cm)
Achieves inductor Q values approaching 20
Communications R&D Center
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MOM simulation of multi-turn spiral
current flow
Current crowding more pronounced in multi-turn coils
More even distribution
Edge Current
Edge current
4µ
µm
Additional metal thickness
allows more "sidewall" for
current flow, reducing
effective resistance
Expected area
of sidewall
current flow
Spiral line with current crowding
Communications R&D Center
GGF 12/8/99
Outline - Total Technology Support
Introduction
Technology overview
Total Technology Support
Overview
Models
Design Automation
SiGe BiCMOS production circuits
Future directions
Summary
Communications R&D Center
GGF 12/8/99
Total technology support
Foundry and internal designs supported by IBM
Models
Accurate, scalable & statistical RF models including
matching, temperature, frequency, & bias
Cadence and ADS based design environments
Time Domain and Frequency Domaing simulation
Application support organizations
Technical specialists for analog and CMOS ASIC
Training in technology & design environment
Product engineering organization
Supports customer through manufacturing environment
First-pass design success
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IBM BiCMOS Model Methodology
Process Based Statistics!
"Optimal Prediction of Manufacturing
Line"
Scalable Models!
"Optimal Design
Flexibility"
Advanced
Models for
Advanced
Design
Scalable
Statistical
Model
Statistical
Process
Description
Device Scaling
Equations
Physical
Layout
In-line
Electrical
Data
Device
Physics
Nominal Lot
Characterization
Split Lot
Characterization
Design
Rules
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Characterization Data Inputs to Final Model
Arc Edge
Ldrawn
Leff
Body
Final
Model
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W/2
XATAN
Rc
Physical &
Process
Simulation
Data
200
150
fT (GHz)
In-Line
Electrical
Data
0.25x5µm2
0.5V VCB
100
50
Test Site
Hardware
Data
0
1E-4
1E-3
1E-2
1E-1
Ic (A)
Communications R&D Center
Important Modeling Aspects
Physics/process based models simplify development of new
features or extensions
Use of industry standard models allows support for multiple vendor
simulators
e.g. HSPICE, SPECTRE, HP-ADS
Model Generation
Parameter extraction using near-nominal hardwar
Nominal models re-centered
Salability across range of device geometries
Statistical tolerances based on in-line data and process split
lots
Model Verification
Device /Model across bias, temperature conditions
Review parameter correlations with process splits
Ensure corner definitions maintain proper physical relations
Verify Monte Carlo analysis results against process specs
Ensure Kit Integration correct
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Statistical Philosophy - Monte Carlo/Corners
General
Define Gaussian distributions to represent
process/lithography variations/some extracted parameters
First order correlations based on physical relationships or
common/shared process steps
e.g. NPN Ic and Va correlated with base pinch resistance
Device models include localized device mis-match
Monte Carlo
Random variation of all defined process distributions
Model parameters recalculated for each combination ("case")
Each "case" represents one point of expected process range
Gives best approximation of manufacturing process variation
Most time consuming but best analysis
Corner Models
Specific skew of dominant parameters assumed
Represents typical "up" / "down" device performance
Default "up" / "down" may not be valid for all bias,
temperature conditions or circuit applications
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RF CMOS (MOSFETs) Models
Rgate
Rsub
Simplest Case
Current MOSFET models:
AC characterized to 50 GHz
Extrinsic gate and substrate resistance elements added to
BSIM3v3.2 core for improved frequency response
Scalable width, length and multiple gate finger geometries
Use of the BSIM3v3 thermal and 1/f noise equations
Non-quasi-static (NQS) model, device temperature differences,
and adjacent Vth mis-match f(W,L)
Future Enhancements:
Migration from BSIM3 to BSIM4 model
Noise figure / large signal measurements & correlation g
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Resistor Model Topology
Distributed R-C subcircuit improves accuracy at
higher frequencies over single lumped R-C elements
Typical resistance model accuracy within 5% across
-55C to +125C range (body and end R separate T coef)
Additional parasitic diiode element included for
resistor within NWELL or NS, as needed
Scalable width and length geometries
Rend/2
Cpar/6
Rbody/2
2Cpar/3
Rbody/2
Rend/2
Cpar/6
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Advanced SiGe HBT VBIC Models
Advanced VBIC model
topology includes separate
elements:
Current source for impact
ionization
Self-heating network
Fixed oxide capacitances
(E-B, C-B)
Extrinsic series
resistances
Parasitic PNP to substrate
Separate impact ionization
current source required to
properly model
high-breakdown type NPN
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SiGe HBT Future Model Growth
Evaluation / extraction for other advanced BJT models:
HiCUM (Schroter)
MEXTRAM (Phillips)
Extend model and measurement correlation for:
Noise figure data and Large signal data
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SiGe Design Methodology
Schematic Capture
Cadence Composer
Frequency Domain Simulation
Time Domain Simulation
Cadence Analog Artist
Spectre Direct
IDF
Agilent ADS
Harmonic Balance/HF Spice
Circuit Envelope
Parameterized Cells (PCells)
Virtuoso-XL/DLE LayoutEditor
Design Verification
LVS/DRC
Hierarchical Checking
DIVA & Assura
Resimulation
Resimulation
Layout
IBM SiGe Design Kit
Scaleable VBIC HBT Model
PFET, NFET
Spiral inductors, Stacked
MIM, Resistors, Varactor,
ESD
Parasitic Extraction
Coeffgen, PRE, LPE
Sequence Columbus RF (1Q01)
Cadence RCX (2Q01)
GDS II
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Outline - SiGe Production Circuits
Introduction
Technology overview
Total Technology Support
SiGe BiCMOS production circuits
Wireless
Wired
Storage
Future directions
Summary
Communications R&D Center
GGF 12/8/99
Tri-Band LNA/Image Reject Mixer
Product
Tri-band GSM Image Reject Mixer with LNA
Features
900MHz, 1.8GHz and 1.9GHz operation
Low power with sleep mode and single
supply (3.0V) operation
Fully integrated differential design including
LNA for improved performance
Integrated IF phase shifter/combiner and LO
quadrature generator which simplifies use
Flexible design with external low sensitivity
matching
CMOS compatible band select logic control
RF+
4:1
DCS
LO
RF-
RC
polyphase
filter
Frequency (MHz)
935-960 MHz (GSM)
1.8-2.0GHz
(DCS/PCS)
Cascade Gain
22 dB
NF
RF Input VSWR
3.5 dB
< 2:1
LO Input VSWR
< 2:1
IIP3
LO Power
Supply Voltage
-14 dBm
200mVp ECL
2.7-3.3 V
Supply Current
< 30 mA
Port Isolation (min)
20 dB (all ports)
Image Rejection
> 30 dB
IF Frequency
IF Load Impedance
400 MHz
600 Ω
Package
Temperature
TSSOP24
-40 to +85C
IF+
RF+
4:1
IF-
GSM
LO
LO
Quad
Gen.
RF-
Sleep
Bias Control
Vcc
LNA
Vcc
Mix
Band Control
Band sel.
LO LO LO LO
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GGF 12/8/99
TDMA Power Amp
Competitive specs to GaAs
Integration potential, lower cost
AMPS
POUT
Gain
PAE
NADC
POUT
Gain
PAE
ACPR
ALT
Ruggedness
GGF 12/8/99
IBM
Measured
"Typical"
GaAs Data
Sheet
”Typical”
31
27
53%
32
26
50%
29.5
29.5
48
-26
-48
10:1@5V
30
28
45
-28
-48
10:1@5
V
Communications R&D Center
2.5 GHz Frequency Synthesizer
Example of non scaling in Analog & RF chips
Wirebond pad counts and passives do not scale with
reducing lithography dimensions
Pad count detemining peripheral chip dimensions
Large passives dominate space consumption
40% of space determined by two capacitors
Large area inductors
3.8x2.0 mm2
M. Soyuer, IBM
Yorktown Hts., NY
Communications R&D Center
GGF 12/8/99
Intersil Wireless LAN Chipset
Block Diagram, I/Q Modulator/ Demodulator
Commercial product
2.4 GHz (ISM Band)
3 SiGe BICMOS + 1 CMOS chips
Replaces 8 chips (some GaAs) +
board components
IF_IN
I
OFFSET
CAL
Q
O
0/ 90 PLL MODULE
> 2 Million chip sets shipped
IF_OUT
IF DETECTOR OUT
RECEIVE AGC
BASEBAND RXI
Σ
CAL ENABLE
BASEBAND RXQ
IF 2X LO/VCO IN
CHARGE PUMP OUT
3-WIRE INTERFACE
REF IN
BASEBAND TXI
BASEBAND TXQ
TRANSMIT IF AGC
Specification
Pin Count
Radio Bit Rate
Receiver Icc
2x Loc. Osc. Freq.
Gain Control
RX Phase Balance
Tx Carrier Suppression
Phase detector Icc
Baseband Coupling
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HFA 3726 (old)
80
2 MBit/ s
70 mA
20-800 MHz
Limiter
+/- 4 degrees
-28 dBc max
0.8 mA
AC
HFA 3783 (new-SiGe)
48
11 MBit/ s
36 mA
160-1200 MHz
Tx and Rx AGC
+/- 2 degrees
-30 dBc max
0.1 mA
DC w/ internal offset
correction
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Digital Network Switch
Highest level of HBT integration published (1997)
(highest integration today > 150K - not published)
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Production PRML Read Channel
First SiGe product at 0.25µ
µm
1200 SiGe HBT's
300K Gates 0.25µ
µm CMOS Logic (>1,000,000 Transistors)
>75 200mm wafers/day in production at IBM Burlington
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GGF 12/8/99
Alcatel 10Gbit/sec SONET
τ
10 and 40 Gbps Circuits with IBM SiGe
First Experimental Multi Chip Reticle 18 x 18 mm²
• All 10 Gbps circuits were first time right
• The chips have been moved to production directly
• The average circuit yield is > 90%
8:1 MUX
13 Gbps
5 V, 2.5 W
2000 Tr.
3 x 3 mm²
10 Gbps Clock and Data Recovery Multi Chip Module
GGF 12/8/99
68x69 Cross-Point Switch
AMCC Introduces Industry's First Silicon Germanium 68 x 69
Differential Crosspoint Switch with over 200 Gbps Switching
Capacity
68 x 69 differential crosspoint switch
NRZ data rates up to 3.2 Gbps
Rise/fall times of 85 picoseconds
1.8 picoseconds typical RMS jitter accumulation
Bandwidth-to-power ratio over 30 gigabits per watt
SAN DIEGO, August 22, 2000 - Applied Micro Circuits Corp. (AMCC) [NASDAQ:AMCC], a leader in
high-bandwidth silicon connectivity solutions for the world's optical networks, today announced the
S2090, the industry's first very high-speed Silicon Germanium (SiGe) 68 x 69 differential crosspoint
switch with full broadcast switching capability. Ideal for use in high-speed applications such as Dense
Wavelength Division Multiplexing (DWDM) switching, digital video, high-speed automatic test
equipment (ATE), and datacom or telecom switches, the S2090 can handle NRZ data rates up to 3.2
Gbps per channel with corresponding output rise/fall times of 85 picoseconds. Furthermore, the S2090
also demonstrates and unprecedented 1.8 picoseconds typical Root Mean Square (RMS) jitter
accumulation and sports power optimization features, which can achieve typical power dissipation as
low as 7 Watts.
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POS/ATM SONET Mapper
Single chip OC-48c SONET/SDH Mapper with integrated
serializer / deserializer, integrated clock recovery (CDR),
clock synthesis (CSU)
Highly integrated HBT and
ASIC methodology
1.2M CMOS devices
6K SiGe HBTs
Die size 10.84x10.84 mm2
65 percent reduction in
board real estate compared
to existing solutions
3.3V technology with 3.4W
of typical power
Communications R&D Center
GGF 12/8/99
Outline - Introduction
Introduction
Technology overview
Total Technology Solution
SiGe BiCMOS production circuits
Summary
Communications R&D Center
GGF 12/8/99
Summary
SiGe HBT BiCMOS is integrated into a wide range
mainstream products today
Key differentiators for the SiGe HBT
high integration : HBT count and CMOS
power, linearity, noise
Volume products in wired, wireless, storage, test and
other applications
Two generations of SiGe BiCMOS in production
Highly integrated parts with > 1.6 M FETs, 150K HBTs
Roadmap to continuous improvements
Passives and interonnect improvements are central
Models and Design Kits -> tools for circuit designers
Accurate statistical models across T, Freq., Bias
Robust design platforms with state of the art point tools
Communications R&D Center
GGF 12/8/99