Design.
For Beyond CMOS
Sandip Tiwari
st222@cornell.edu
The design process can not be considered effective and
successful if
it needs PhD level experts,
or doesn’t work robustly,
doesn’t produce working products within spec’s in first spin,
and is not open for new research breakthroughs that may
be useful in technology applications.
Acknowledgements: Collaborators, students, peers,
funders (NSF, DARPA, Mellowes Endowment, Hosts), ...
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Design is Central to Good Engineering
Analog Computing circa 200 BC:
Antikythera mechanism
The Modern Era:
Copernicus, …
Galileo
Tiwari_10_2011_Greece.pptx
phases of moon
2
Understanding
<=>
Engineering
Design
Science
Good Engineering => Good Tools =>Tiwari_10_2011_Greece.pptx
New Science => New Engineering => New Tools =>
3
So, what do we do today?
Digital World
Analog/Mixed-Signal/RF World
High performance microprocessors:
Trillion transistors
hundreds of tools (layout, timing,
process, models, noise, power,
DRC, LVS, Yield, verification, )
hundreds of people
2-3 years
hundreds of milllion$’s
Embedded :
Sub-trillion transistors
hundreds of tools (layout, timing,
models, noise, power, DRC,
LVS, Yield, verification, …)
IP,
10’s of people
1-2 years
10’s of million$’s
Million transistors
Even more tools
Small-signal, parasitics, tlines, large
signal, cross-talk, …
With enough resources,
we can design for digital
with trillion transistors,
but,
can’t design analog with
million transistors.
We usually get it right first time around
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Problems with Current Microelectronics
Infrastructure
 Designed for digital – is quasi-static




Process models – layout – 2D device – compact model for quasistatic with
layout, snm, thermal, noise, statistics, ..
Corners for all variations
Designed for worst cases
Partitioned, Inefficient & weighted with historical baggage
 Stochasticity is intrinsic at nanoscale; it is not just a threshold variation
 Quasistatic approaches brake for high frequency



In-plane effects– lateral diffusions, capacitances, … parasitics
Digital corners and analog corners are two very different beasts
Small-signal, Large-signal, effects. …
 Every change, e.g., 3D, is a kluged tool to be repeatedly used with base.
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Different Design Models
hardware
architecture
software
architecture
Simulink HDL Coder
EDA Simulator Link MQ
EDA Simulator Link IN
Atlas
Supreme/FEDSS
Real-Time Workshop
Embedded Coder,
Targets, Links
Generate
Ansys,
Abaqus
Generate
VHDL
RTL
Cadence Virtuoso, …
Cadence Encounter, …
Layout, Schematic,
HFSS,
Timing, Compact
Sonnet
Models, …
MATLAB® and Simulink®
algorithm and system design
Mechanical
HDL
Verify
EM
Verify
Electronics
C/C++
SW
Quantum
Know
your 2nd
order
PDE’s
Tiwari_10_2011_Greece.pptx
FPGA
ASIC
SW
OS
CPU
CPU
6
Today’s Microelectronics
Physical
100
Time Scale (s)
10-3
10-6
10-9
10-12
Structural
Behavioral
Chip
Floor Planning
Placement
Timing
Congestion
Routing
Compact
Verification
ASX,
Spice,
…
Device
Temperature
Lumped
Boltzmann
Power
Interconnect
Hydrodynamic
Electromagnetic
Noise
Drift-Diffusion
Monte Carlo
Atomistic
Continuum
High Abstraction (HDL)
Quantum
Master Eq.
NEG
10-15
10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3 10-2 10-1
Length Scale (m)
1
101
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102
103
7
Design’s Uncertainty Principle
Boundaries
Let us see how
we can reduce
the constant of
this Uncertainty
Relationship
(Complexity Depth)-1
∆Effort × ∆Failure ≥ Constant
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The problems of beyond?
 Signals are not just I, Q and V in t.
 New signal modalities and their transformations. E, H, Phonons, Fluid,
Entanglement, …
 Corners at nanoscale? Stochasticity intrinsic.
 Heterogeneous integration.
 2D – 3D
 Abstractions across scales.
Consequences
 We don’t really know how to judge beforehand what works and what
doesn’t work?
 What is robust and what is not?
 What energy and power in changing signals?
 What are process technology interactions and effects?
 Thermal, Temporal, Length, …
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Radiation: Multiscale and Multiphysics
VUmps
(GEANT4)
Events
C++ Tools,
Scripting
Automatic
Meshing
Geometry
Mathematica
& Python
ISE TCAD
(DESSIS)
Gaussian charge generation
1018
e-/cm3
1014 e-/cm3
RADSAFE, R. Weller et al. (Vanderbilt)
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Beyond CMOS: Fluid-Magnetic-ElectricMechanical
Tunneling
Precession
Soft/hard
…
Magnetic
Field
Viscosity
Turbulence
Fluid
Electrodynamic
Boundary Layer
Charge
Time
…
…
Mechanical Structure
Linear
Plastic
Creep
…
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The objective of design is that non-specialists, with
sufficient training, e.g., BS/MS, can design without
knowing details of technology and everything else,
so that designs can function in first pass with
reliability and robustness.
This allows many designers (x100 or more) to
take advantage of the costly technology
infrastructure towards societal benefit. The
technology costs are thus amortized.
The design approaches should also balance
efficiencies and effectiveness.
And be open to new science breakthroughs.
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Behavioral
“Beyond CMOS” !
System
Algorithm
Registers
Boolean Expr
Differential Eq
Structural
CPU, Memory
Controller, Netlist
ALU, Register,
MUX
Gate, FlipFlop
Transistors
Ab Initio
Polygons
Cells, Modules
Floorplans
Blocks
Boards
Systems
Physical
Component
Device
Function
Algorithm
System
Growth
Deposition
Anneals
Lithography
Etching
ILD
Packaging
Process
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New Technology Challenges
Molecular Electronics
 100 C effects - reliability, >100 nA/m currents, …
Solid-State Quantum Computing
 Define the system. CMOS: 1 error in 10 years in 1 switch: e ~ 10 -20, 10 s
Spintronics
 A write, Integration at length scale, spin-to-electrical conversion, …
Nanowires
 VT control, Multi-VT and sigma, heat, tunneling is depth sensitive – dopant tails, …
Memristors – Variable Resistors
 Synaptic architectures not understood; refresh-decay, isn’t this “hysteresis”, …
Graphene
 Contact resistances 1 order of magnitude better than silicon needed. For digital, suppressing
leakage, variability, surface effects, …
When the answer is negative in a fundamental form at the lowest strata, the conclusion is easy.
When it passes that test, it is much harder.
Challenge is Global Optimization versus Local optimization under system constraints.
Late 70’s: IBM stayed with bipolar because CMOS was too slow. The answer under
power constraints was in architecture (similar to the multicore today). So, systemscale design very critical.
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New Technology Challenges
When the answer to improvement in a subset of properties is
negative in a fundamental form at the lowest strata, the
conclusion is easy.
When it passes that test, it is much harder.
The Challenge is that if the system use is of many
components interacting together
Global Optimization versus Local Optimization under
system constraints is a hard problem that requires a
thorough design incorporating the abstractions.
Example: In late 70’s, IBM stayed with bipolar because CMOS
was too slow. The answer under power constraints was in
architecture (similar to the multicore today).
So, system-scale design very critical.
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Build A New Open Infrastructure
Problem Description
Functional, …
Core Libraries
User Interfaces /
Extractors
Graphical: Matlab ..
Checks
Verifications, ..
Standardize
interfaces
Standardize and define the abstractions
Multiple solvers – domain specific
Multiple solvers – multi-domain
Open to newer tools being brought in
Solver 1
Electrical
Solver N
Electrical
Solver 1
Mechanical
Solver N
Mechanical
Solver 1
Thermal
Solver N
Thermal
Solver 1
EM
Solver N
EM
Solver 1
Coupled El-Therm
Solver N
Coupled El-Therm
Solver 1
Coupled El-Mech
Solver N
Coupled El-Mech
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Back Up
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100 nm
Classical
Scale
Continuum
& Bulk
Continuum
& Nano
100 nm
Semi-Classical
Physics
Molecular
Dynamic
QM
10 nm
Tight Binding
nm
Ab Initio
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