International Journal of Advanced Scientific and Technical Research
Available online on http://www.rspublication.com/ijst/index.html
Issue 3 volume 2, March-April 2013
ISSN 2249-9954
Unipolar PWM Control Technique having Inverted Sine
Carrier for Trinary DC source Multilevel Inverter
V.Arun#1, B.Shanthi#2, S.P.Natarajan#3
#1 Department of EEE, Arunai Engineering College, Thiruvannamalai, India
#2 Centralised Instrumentation and Service Laboratory, Annamalai University, Chidambaram
#3 Department of EIE, Annamalai University, Chidambaram, Tamilnadu, India
ABSTRACT
This paper proposes a trinary DC source 9-level inverter. Trinary DC source multilevel
inverter is triggered by the Unipolar PWM strategy having sinusoidal and trapezoidal reference
with inverted sine carriers. These Pulse Width Modulating (PWM) techniques include Phase
Disposition (PD), Alternate Phase Opposition Disposition (APOD), Carrier Overlapping (CO).
Performance factors like Total Harmonic Distortion (THD), VRMS (fundamental), crest factor
and form factor are evaluated for various modulation indices. Simulations were performed using
MATLAB-SIMULINK. It is observed that UISCPDPWM strategy with trapezoidal reference
provides output with relatively low distortion and UISCOPWM strategy with trapezoidal
reference provides relatively higher fundamental RMS output voltage.
Key words: APOD, CO, PD, PWM.
Corresponding Author: V.Arun
INTRODUCTION
Multilevel inverter technology has emerged recently as a very important alternative in the area of
high-power medium-voltage energy control. Multilevel inverters include an array of power
semiconductors and capacitor voltage sources, the output of which generate voltages with
stepped waveforms. Lai and Peng [1] developed modulation control techniques for three phase
trinary multilevel inverter. Dixon and Moran [2] introduced sinusoidal space vector modulation
control techniques for three phase trinary multilevel inverter. Various control technique for
cascaded multilevel inverter described by Corzine et al in [3]. Liu and Luo [4] introduced trinary
81-level multilevel inverter for STATCOM application. Seyezhai and Mathur [5] introduced the
inverted sine PWM techniques for asymmetric cascaded multilevel inverter. Lin and Luo [6]
introduced trinary 81-level multilevel inverter for motor drive. Aghdam et al [7] proposed
multicarrier PWM methods for asymmetric multilevel inverter. Shanthi and Natarajan [8]
developed unipolar PWM strategies for single phase five level cascaded inverter. Pandian and
Rama Reddy [9] described trinary multilevel inverter fed induction motor drive. Bensraj et al
[10] introduced unipolar PWM using trapezoidal amalgamated reference. Bensraj and Natarajan
[11] proposed multicarrier trapezoidal PWM strategies for a single phase five level cascaded
inverter. Urmila and Subbarayudu [12] proposed various modified reference modulating
techniques. Dixon et al [13] proposed asymmetric multilevel inverter for traction drives.
Seyezhai in [14] proposed inverted sine PWM techniques for three phase asymmetric multilevel
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International Journal of Advanced Scientific and Technical Research
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Issue 3 volume 2, March-April 2013
ISSN 2249-9954
inverter. Radha et al [15] introduced asymmetric multilevel inverter for electrical vehicles.
Srikanth et al [16] discussed grid connected nine level trinary inverter. Reza et al [17] proposed
multilevel inverter with unequal DC source. This paper presents a single phase trinary DC source
multilevel inverter topology for investigation using unipolar PWM control techniques.
Simulations were performed using MATLAB-SIMULINK. Harmonic analysis and evaluation of
different performance measures for various modulation indices have been carried out and
presented.
II. BASIC OPERATION OF MULTILEVEL INVERTER
Figure 1 shows a circuit configuration of a cascaded H-bridge multilevel inverter
employing trinary DC input source. It looks like a traditional cascaded H-bridge multilevel
inverter except input dc sources. By using VDC and 3VDC, it can synthesize nine output levels;
-4VDC, -3VDC, -2VDC, -VDC, 0, VDC, 2VDC, 3VDC, 4VDC. The lower inverter (HB2)
generates a fundamental output voltage with three levels, and then the upper inverter adds or
subtracts one level from the fundamental wave to synthesize stepped waves. Here, the final
output voltage levels becomes the sum of each terminal voltage of H-bridge, and it is given as
Vab  VHB1  VHB 2
HB1
S1
S3
VDC
a
S2
S4
Vab
HB2
S5
S7
3VDC
b
S6
S8
Fig 1: Trinary DC source cascaded MLI
In trinary DC source MLI, output voltage level is nine , if n number of H-bridge module has
independent DC sources in sequence of the power of 3, an expected output voltage level is given
as
Vn  3n , n  1, 2,3..
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Issue 3 volume 2, March-April 2013
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III. UNIPOLAR INVERTED SINE PULSE WIDTH MODULATION SCHEME
The scheme uses a unipolar sine and trapezoidal as modulating signal and inverted sine
as carriers. In Inverted sine carrier PWM scheme, high frequency inverted sine carriers are
compared with rectified sine and trapezoidal reference. The intersection between the unipolar
reference signal and the carrier signals defines the switching instant of the PWM pulse. The
multiple carriers used are positioned above zero level and the number of carriers is dependent on
the output voltage levels. For an m-level inverter, (m-1)/2 carriers with the same frequency fc
and the same amplitude Ac are disposed. The reference waveform has peak-to-peak amplitude
Am and frequency fm. The reference is continuously compared with each of the carrier signals.
If the reference is greater than a carrier signal, then the active device corresponding to that
carrier is switched on; and if the reference is less than a carrier signal, then the active device
corresponding to that carrier is switched off. There are many alternative strategies are possible,
some of them are tried in this paper and they are:
a.
Phase disposition PWM strategy (PDPWM).
b.
Alternate phase opposition disposition PWM strategy (APODPWM).
c.
Carrier overlapping PWM strategy (COPWM).
The formulae to find the Amplitude of modulation indices are as follows:
For PDPWM, APODPWM:
ma  2 A m /(m  1) Ac )
For COPWM:
ma  Am / (2.5* A c )
(3)
(4)
The frequency ratio mf are as follows:
m f  fc / fm
(5)
The advantages of ISPWM method are [5]:

It has a better spectral quality and a higher fundamental component compared to the
conventional sinusoidal PWM (SPWM) without any pulse dropping.

The ISCPWM technique enhances the fundamental output voltage particularly at lower
modulation index ranges

There is a reduction in the total harmonic distortion (THD) and switching losses.
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
Issue 3 volume 2, March-April 2013
ISSN 2249-9954
To increase the fundamental amplitude in the sinusoidal pulse-width modulation the only
way is by increasing the modulation index beyond 1 which is called over modulation. Over
modulation causes the output voltage to contain many lower order harmonics and also makes
the fundamental component vs modulation index relation non-linear. Inverted sine pulse width modulation technique replaces over modulation technique.
A) Unipolar Inverted Sine Carrier Phase Disposition PWM (UISCPDPWM)
The inverted sine carriers of same amplitude and frequency are disposed such that bands they
occupy are contiguous. The carrier arrangement for trinary DC source multilevel inverter having
Sine reference and Trapezoidal are illustrated in figures 2 & 3 respectively
Fig 2. Carrier arrangement for UISCPDPWM strategy with sine reference (ma=0.9 and mf=40)
Fig 3. Carrier arrangement for UISCPDPWM strategy with Trapezoidal reference
(ma=0.9 and mf=40)
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B) Unipolar Inverted Sine Carrier Alternative Phase Opposition Disposition PWM
(UISCAPODPWM)
Carriers for trinary DC source multilevel inverter having Sine reference and Trapezoidal are
illustrated in figures 4 & 5 respectively. The inverted sine carriers of same amplitude are phase
displaced from each other by 180 degrees alternately.
Fig 4. Carrier arrangement for UISCAPODPWM strategy with sine reference
(ma=0.9 and mf=40)
Fig 5. Carrier arrangement for UISCPDPWM strategy with Trapezoidal reference
(ma=0.9 and mf=40)
C) Unipolar Inverted Sine Carrier Overlapping PWM (UISCOPWM)
Carriers for trinary DC source multilevel inverter having Sine reference and Trapezoidal are
illustrated in figures 6 & 7 respectively. In carrier overlapping technique, (m-1)/2 carriers are
disposed such that the bands they occupy overlap each other; the overlapping vertical distance
between each carrier is Ac/2.
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Issue 3 volume 2, March-April 2013
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Fig. 6. Carrier arrangement for UISCOPWM strategy with sine reference (ma=0.9 and mf=40)
Fig. 7. Carrier arrangement for UISCOPWM strategy with Trapezoidal reference
(ma=0.9 and mf=40)
IV. SIMULATION RESULTS
The single phase trinary DC source nine level inverter is modeled in SIMULINK using
power system block set. Switching signals for trinary multilevel inverter using UISCPWM
strategies are simulated. Simulations were performed for different values of ma ranging from 0.8
to 1 and the corresponding %THD are measured using the FFT block and their values are shown
in Table I. Tables II to IV show the VRMS (fundamental) , Crest Factor (CF) and Form Factor
(FF) of the output voltage and for various modulation indices of single phase trinary DC source
MLI. Figure 8 to19
show the simulated output voltage of Trinary MLI and their
corresponding harmonic spectrum. Figure 8 & 9 displays the nine level output voltage generated
by UISCPDPWM strategy with sine reference and Trapezoidal reference and its FFT plot is
shown in Figure 10 & 11. Figure 12 & 13 shows the nine level output voltage generated by
UISCAPODPWM strategy with sine reference and Trapezoidal reference and its FFT plot is
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Issue 3 volume 2, March-April 2013
ISSN 2249-9954
shown in Figure 14 & 15. Figure 16 & 17 shows the nine level output voltage generated by
UISCOPWM strategy with sine reference and Trapezoidal reference and its FFT plot is shown
in Figure 18 & 19. For ma= 0.9, it is observed from the Figures. (10, 11, 14, 15, 18, and 19) the
harmonic energy is dominant in: a) 39th order in UISCPDPWM with sine reference and 7th ,19th
and 29th of trapezoidal reference. b) 29th, 31st and 37th in UISCAPODPWM with sine reference
and 31st, 37th and 39th of trapezoidal reference. c) 5th, 37th and 39th in UISCOPWM with sine
reference and 5th, 7th, 9th, 13th and 39th of trapezoidal reference.
The following parameter values are used for simulation: V DC =75V, R (load) = 100 ohms,
fc=2000 Hz and fm=50Hz.
Fig. 8. Output voltage generated by UISCPDPWM strategy with sine reference
Fig 9. Output voltage generated by UISCPDPWM strategy with Trapezoidal reference
Fig 10. FFT plot for output voltage of UISCPDPWM strategy with sine reference
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Fig. 11. FFT plot for output voltage of UISCPDPWM strategy with Trapezoidal reference
Fig. 12 Output voltage generated by UISCAPODPWM strategy sine reference
Fig. 13 Output voltage generated by UISCAPODPWM strategy Trapezoidal reference
Fig. 14. FFT plot for output voltage of UISCAPODPWM strategy with sine reference
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Fig. 15. FFT plot for output voltage of UISCAPODPWM strategy with Trapezoidal reference
Fig. 16. Output voltage generated by UISCOPWM strategy with sine reference
Fig. 17. Output voltage generated by UISCOPWM strategy with Trapezoidal reference
Fig. 18. FFT plot for output voltage of UISCCOPWM strategy with sine reference
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Fig. 19. FFT plot for output voltage of UISCCOPWM strategy with Trapezoidal reference
Table1. % THD For Different Modulation Indices
ma
UISCPDPWM
Sine Ref.
UISCAPODPWM
Trapezoidal
Ref
Sine Ref.
UISCOPWM
Trapezoidal
Ref
Sine Ref.
Trapezoidal
Ref
1
14.05
12.57
16.02
12.56
18.39
17.25
0.95
14.76
14.66
17.1
17.39
19.8
18.8
0.9
16.29
15.83
17.84
18.53
20.53
19.53
0.85
17.2
17.14
17.83
18.38
22.08
20.85
0.8
18.2
18.55
17.58
17.98
24.36
22.53
Table 2. VRMS For Different Modulation Indices
ma
UISCPDPWM
Sine Ref.
1
UISCAPODPWM
Trapezoidal
Ref.
Sine Ref.
UISCCOPWM
Trapezoidal
Ref.
Sine Ref.
Trapezoidal
Ref.
219
227.6
207.3
221.8
227.3
232.5
0.95
209.3
218.9
195.3
203.8
220.6
226.3
0.9
201.2
209.3
186.5
193.4
212.9
219
0.85
191.2
201.3
179
185
205.2
211.8
0.8
179.6
190.9
171.2
177.2
195.3
204.2
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Table 3. % CF For Different Modulation Indices
ma
UISCPDPWM
UISCAPODPWM
UISCOPWM
Sine Ref.
Trapezoidal
Ref.
Sine Ref.
Trapezoidal
Ref.
Sine Ref.
Trapezoidal
Ref.
1
1.414612
1.413884
1.414375
1.414337
1.41443
1.414194
0.95
1.414238
1.413888
1.414235
1.414132
1.414325
1.414052
0.9
1.414513
1.414238
1.414477
1.414168
1.414279
1.414155
0.85
1.414749
1.41381
1.413966
1.414595
1.414717
1.41407
0.8
1.413697
1.413829
1.41472
1.414221
1.414235
1.41381
Table 4. Form Factor For Different Modulation Indices
ma
UISCPDPWM
Sine Ref.
Trapezoidal
Ref.
UISCAPODPWM
Sine Ref.
Trapezoidal
Ref.
UISCCOPWM
Sine Ref.
Trapezoidal
Ref.
1
1946.667
3034.667
1382
2957.333
1515.333
1.79E+08
0.95
697.6667
1459.333
473.4545
5907.246
5882.667
6034.667
0.9
2682.667
1860.444
2486.667
1031.467
2838.667
5840
0.85
2549.333
766.8571
4773.333
986.6667
5472
5648
0.8
2394.667
727.2381
4.46E+08
1181.333
1041.6
2722.667
V.CONCLUSION
In this paper, UISCPWM techniques for Trinary DC source nine level inverter have been
presented. Trinary DC source multilevel inverter gives higher output voltage with low
harmonics. Performance factors like %THD, Vrms, CF and FF have been evaluated presented
and analyzed. It is found that the UISCPDPWM strategy with trapezoidal reference provides
relatively lower %THD, UISCOPWM strategy with trapezoidal reference is found to perform
better since it provides relatively higher fundamental RMS output voltage. CF is almost same for
all the strategies. Depending on the performance measure required in a particular application of
chosen MLI based on the output quality appropriate PWM have to be employed.
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