Solution of ECE65 Final (Winter 2006)
Notes: 1. For each problem, 20% of points is for the “correct” final answer.
2. Messy, incoherent papers lose point! Explain what you are doing!
3. Use the following information in solving or designing circuits: OpAmps have a unity-gain
bandwidth of 106 Hz, a maximum output current limit of 100 mA, and a slew rate of 1 V/µs.
OpAmps are powered by ±15 V power supplies (power supplies not shown),
NPN Si transistors have β = 200, βmin = 100, rπ = 3 kΩ, and ro = 100 kΩ.
NMOS transistors have K = 0.25 mA/V2 and Vt = 2 V.
In circuit design, use 5% tolarence commercial resistor and capacitor values of 1, 1.1, 1.2,
1.3, 1.5, 1.6, 1.8, 2, 2.2, 2.4, 2.7, 3., 3.3, 3.6, 3.9, 4.3, 4.7, 5.1, 5.6, 6.2, 6.8, 7.5, 8.2, 9.1 (×10 n
where n is an integer). You can also use 5 mH inductors.
Problem 1. In the circuit below, find vo in terms of v1 and v2 (Assume OpAmps are ideal).
(10 pts)
V1
−
R2
v1 − v 2 v1 − v A
+
=0
R2
R1
v2 − v 1 v2 − v B
+
=0
R2
R3
R1
R1
v A = v1 1 +
− v2
R2
R2
R3
R3
vB = −v1
+ v2 1 +
R2
R2
→
→
Vo
R3
V2
V2
+
R1
V1
Both OpAmps have negative feedback, so
vp1 = vn1 = v1 and vp2 = vn2 = v2 . Then,
by node-voltage method:
VA
+
_
−
+
VB
Then:
R1 R3
R1 R3
+
− v2 1 +
+
R2 R2
R2 R2
R1 + R 3
vo = (v1 − v2 ) 1 +
R2
vo = v A − v B = v 1 1 +
Solution of ECE65 Final (Winter 2006)
1
Problem 2. An OpAmp circuit containing only one OpAmp is attached to a 500 Ω load.
(A) Design the OpAmp circuit such that if an input voltage of Vi sin(ωt) is applied to the
circuit, the output voltage would be 4Vi sin(ωt) for a frequency range of DC to 100 kHz
(Assume OpAmp is ideal for this part ONLY).
(B) An input voltage of Vi cos(105 t) is applied to the circuit. What is the maximum value
of Vi for the circuit to operate per its design specifications of part A. (10 pt)
Part A: First, we find the transfer function of the circuit:
vo
H=
=4
vi
Since H is independent of frequency, this circuit is an amplifier. Because there is no phase shift between input and
output, it should be a non-inverting amplifier. Prototype
of the circuit is shown with
A=1+
Vi
Vo
+
−
R2
RL
R1
R2
R1
Setting A = 4 and choosing R1 = 10 kΩ, we find R2 = 30 kΩ (both commercial values).
Part B: We need to check OpAmp limitations to find maximum Vi . Frequency response
limit does not apply.
1) Voltage supply limit (Saturation):
vs− ≤ vo ≤ vs+
→
|Vo | ≤ 15
→
AVi ≤ 15
→
Vi ≤ 3.75 V
2) Slew Rate:
dvo
= AVim ω ≤ S0
dt
→
4 × Vi × 105 ≤ 106
→
Vi ≤ 2.5 V
3) Maximum Current Limit: Ignoring the current flowing into R2 as it is much larger than
RL = 500 Ω, we find
Isc ≤ 100 × 10−3 → Vo = RL Isc ≤ 500 × 0.1
Vo
50
Vi =
≤
→ Vi ≤ 12.5 V
A
4
→
Vo =≤ 50 V
The slew rate limit is the most restrictive with Vi ≤ 2.5 V.
Solution of ECE65 Final (Winter 2006)
2
Problem 3. Design a first-order filter with a gain of 0 dB for DC signals and a gain of
-6 dB at 20 kHz. The load for this filter, RL ≥ 10 kΩ. (10 pts)
Since the circuit is a first-order filter, it should be either
a high-pass or a low-pass filter. Since the gain at 20 kHz
is smaller than gain for DC signals, it should be a lowpass filter. Since the gain for DC signal (maximum gain)
is 0 dB (or a gain of 1), it is a passive low-pass filter.
Prototype of the circuit is shown with
H(jω) =
1
1
=
1 + jω/ωc
1 + jf /fc
and
R
+
+
C
V
i
Vo
−
−
ωc = 2πfc =
1
RC
RL
and
Zo |max = R
To find the cut-off frequency of the filter, we note:
|H(f = 20 kHz)| = q
20 × 103 √
= 3
fc
→
1
1 + (f /fc
)2
=q
1
1 + (20 ×
103 /f
c
)2
= 10−6/20 = 0.50
fc = 11.6 kHz
Then, using our filter design equations:
Zo |max = R RL = 10 × 103
1
= 11.6 kHz
fc =
2πRC
→
R ≤ 0.1 × 10 × 103 = 103 Ω
Choosing the largest acceptable value of R to get the smallest capacitor value, we get R =
1 kΩ and C = 1.37 × 10−8 F or 13.7 nF. Commercial values are R = 1 kΩ and C = 13 nF.
Problem 4. Show that the circuit below is a NOR gate (Assume a “LOW” voltage of 0.2 V
and a “HIGH” voltage of 5 V and BJTs are identical). (10 pts)
5V
i
1 kΩ
vo
4
BE1-KVL:
v1 = 10 iB1 + vBE1
BE2-KVL:
v2 = 104 iB2 + vBE2
CE-KVL:
5 = 103 i + vo
KCL:
i = iC1 + iC2
vo = vCE1 = vCE2
Solution of ECE65 Final (Winter 2006)
v1
10kΩ
Q1
v2
10kΩ
Q2
3
First, let’s examine the state of transistors for different values of v1 or v2 . If v1 = 0.2 V,
assume Q1 is in cut-off, iB1 = 0 and vBE1 < vγ = 0.7 V:
BE1-KVL:
0.2 = 104 × 0 + vBE1
→
vBE1 = 0.2 V < vγ
So, Q1 will be in cut-off (this is independent of state of Q2) with iC1 = 0. Similarly, if
v2 = 0.2 V, Q2 will be in cut-off with iC2 = 0 (this is also independent of state of Q1)
If v1 = 5 V, assume Q1 is ON (either active or saturation), vBE1 = vγ = 0.7 V and iB1 > 0:
BE1-KVL:
5 = 104 × iB1 + 0.7
→
iB1 = 0.43 mA > 0
So, Q1 will be ON (this is independent of state of Q2) with iB1 = 0.43 mA. Similarly, if
v2 = 5 V, Q2 will be ON with iB2 = 0.43 mA (this is also independent of state of Q1).
Case 1: v1 = v2 = 0.2 V
From above, both BJTs will be in cut-off and iC1 = iC2 = 0. From KCL above i = iC1 +iC2 =
0 and from CE-KVL above vo = 5 V. So when both inputs are “LOW”, the output is “HIGH.”
Case 2: v1 = 0.2 V and v2 = 5 V
From above, Q1 will be in cut-off with iC1 = 0 and Q2 will be ON with iB2 = 0.43 mA.
Assume Q2 is in saturation: vCE2 = 0.2 and iC2 /iB2 < β. From CE-KVL, vo = vCE1 =
vCE2 = 0.2 V and i = iC2 = 4.8 mA. Since iC2 /iB2 = 4.8/0.43 = 11.2 < β = 200, the
assumption of Q2 being in saturation is correct and vo = 0.2 V. Therefore, when v1 is LOW
and v2 is HIGH, the output will be “LOW.”
Case 3: v1 = 5 V and v2 = 0.2 V
Because of the symmetry, this is similar to case 2 with Q1 and Q2 switched. Therefore,
Q2 will be in cut-off with iC2 = 0 and Q1 will be in saturation with iB1 = 0.43 mA,
vo = vCE1 = 0.2 V and i = iC1 = 4.8 mA. Therefore, when v1 is HIGH and v2 is LOW, the
output will be “LOW.”
Case 4: v1 = 5 V and v2 = 5 V
From above, both BJTs will be ON with iB1 = iB2 = 0.43 mA. Since BJTs have the same iB
and the same vCE , both will be in the same state and iC1 = iC2 and i = 2iC1 = 2iC2 . Assume
both BJTs are in saturation: vo = vCE1 = vCE2 = 0.2 V and iC1 /iB1 = iC2 /iB2 < β. Then
from CE-KVL, i = 4.8 mA and iC1 = iC2 = 2.4 mA. Since iC1 /iB1 = iC2 /iB2 = 2.4/0.43 =
5.6 < β = 200, the assumption of Q1 and Q2 being in saturation is correct and vo = 0.2 V.
Therefore, when v1 is HIGH and v2 is HIGH, the output will be “LOW.”
In summary, the output is HIGH only if both inputs are LOW. Thus, this is a NOR gate.
Solution of ECE65 Final (Winter 2006)
4
Problem 5. Find the Q-point parameters of the FET in the circuit below. (10 pts)
Since we are interested in bias point of the circuit, the capacitor is open circuit. We can replace 100 kΩ, 270 kΩ and the
20 V power supply with their Thevenin equivalent (similar
to BJT bias circuits). Alternatively, since IG = 0, we can
find VG by using the voltage divider formula:
20 V
0.47µF
V
i
VG =
ID
270 kΩ
V
G
V
o
V
S
100 × 103
× 20 = 5.41 V
100 × 103 + 270 × 103
100 kΩ
ID
1 kΩ
Since IG = 0, the current in the 1 kΩ resistor is ID , and VS = 103 ID :
VGS = VG − VS = 5.41 − 103 ID
We assume that FET is in active region: ID = K(VGS −Vt )2 and VGS > Vt and VDS > VGS −Vt .
First, substituting for ID in the above equation we get:
2
VGS = 5.41 − 103 × 0.25 × 10−3 (VGS − 2)2 = 5.41 − 0.25VGS
+ VGS − 1
2
0.25VGS
− 4.41 = 0
The above equation has two roots and for each case, the corresponding value of I D can be
found from VGS = 5.36 − 103 ID
VGS = 4.2 V
VGS = −4.2 V
→
→
VS = 1.21 V
VS = 9.61 V
and
and
ID = 1.21 mA
ID = 9.61 mA
The second root is not a physical solution because if VGS = −4.2 < Vt = 2 V, FET should
be in cut-off and ID = 0 and not 9.61 mA. Therefore, VGS = 4.2 V, VS = 1.21 V, and
ID = 1.21 mA. Writing DS-KVL for FET
20 = VDS + 103 ID
→
VDS = 20 − 103 × 1.21 × 10−3 = 18.79 V
(or alternatively, VDS = 20 − VS = 18.79 V). Since VGS = 4.2 > Vt = 2 V and VDS = 18.79 >
VGS − Vt = 4.2 − 2 = 2.2 V, our assumption of FET in active is correct.
Therefore, the bias point values are: VGS = 4.2 V, ID = 1.21 mA, and VDS = 18.79 V.
Solution of ECE65 Final (Winter 2006)
5
Problem 6. Design a BJT amplifier with a gain of 4, a cut-off frequency of 10 Hz, and
Q-point parameters of VCE = 10 V and Ic = 4 mA. (10pts)
VCC
The prototype of this circuit is a common emitter amplifier with
an emitter resistance.
DC bias: The power supply voltage is not given. A good choice
if VCC = 2VCE = 20 V.
R1
vi
RC
vo
Cc
VCC = RC IC + VCE + RE IE
20 − 10 = 4 × 10−3 (RC + RE )
RC
=4
RE
4RE + RE = 2.5 kΩ
→
R2
RC + RE = 2.5 kΩ
RE
Av =
→
RE = 500 Ω, RC = 2 kΩ
Check for good biasing VE > 1 V: VE = RE IE = 500 × 4 × 10−3 = 2 > 1, it is OK.
RB and VBB :
VCC
RB (β + 1)RE → RB ≈ 0.1βmin RE = 0.1 × 100 × 500 = 5.0 kΩ
RC
KVL:
iC
VBB = RB IB + VBE + RE IE
VBB = 5.0 × 103 ×
4 × 10
200
RB
−3
+ 0.7 + 500 × 4 × 10−3 = 2.8 V
+
−
R1 and R2 :
R1 R2
= 5. kΩ
R1 + R 2
R2
2.8
=
=
= 0.14
R1 + R 2
20
+
iB
+
vBE
VBB
vCE
_ _
RE
RB = R 1 k R 2 =
VBB
VCC
leading to R1 = 35.7 kΩ and R2 = 5.8 kΩ.
The value of coupling capacitor is found from:
Ri ≈ RB = 5. kΩ
1
→
2π fl =
Ri Cc
Cc =
1
1
=
= 3.2 µF
2π fl Ri
2π10 × 5, 000
Design values are: R1 = 36 kΩ, R2 = 5.6 kΩ, RE = 510 Ω, RC = 1.5 kΩ, and Cc = 3.3 µF.
Solution of ECE65 Final (Winter 2006)
6
Problem 7. In the circuit below, find vo for vi ranging from −5 to +5 V . (10 pts)
iD
i1
vi
io
1 kΩ
+
−
1 kΩ
+
vo
−
Case 1: Assume diode is ON: vD = vγ = 0.7 V and iD > 0.
KVL:
vo = vi − 0.7
To check the region of validity of our assumption we need to calculate iD :
vD
= 0.7 × 10−3 A = 0.7 mA
103
vo
io = 3 = 10−3 × (vi − 0.7)
10
iD = i o − i 1 > 0 → i o > i 1
→ 10−3 × (vi − 0.7) > 0.7 × 10−3
i1 =
→ vi > 1.4 V
So, if vi > 1.4 V, the diode will be ON and vo = vi − 0.7 V
Case 2: Assume diode is OFF: iD = 0 and vD < vγ = 0.7 V.
KCL:
i o = i1 + iD = i1
KVL:
vi = 103 i1 + 103 io = 2 × 103 io
→
io = i1 = 0.5 × 10−3 vi
vo = 103 io = 0.5vi
To check the region of validity of our assumption we need to calculate vD :
vD = vi − vo = vi − 0.5vi = 0.5vi
vD < vγ = 0.7 V
→
0.5vi < 0.7
→
vi < 1.4 V
So, if vi < 1.4 V, the diode will be OFF and vo = 0.5vi .
In summary, for vi < 1.4 V, vo = 0.5vi and for vi > 1.4 V, vo = vi − 0.7 V.
Solution of ECE65 Final (Winter 2006)
7