Switched Mode Power Conversion
Indian Institute of Science
P
C3
im
D3 C1
Dp
i refl
S1
S3
L
L LK
Vo
IL
Co
R
Vpri
Ipri
VDC
C4
Lm
L LK
Dn
S4
D4
Fig. 5a
n:1:1 Q
IL
IL /n
A
Vpri
VDC
C1
L+L LK
+
_
Vpri/n
Lm
Io
Fig 5b
Co
B
C4
Table I
Sequence and governing equations of the inverter intervals
U Devices ON From
To
VC1
VC2
VC3
VC4
Vpri
1 S3 S4
S3 On S4 Off VDC
VDC
0
0
VDC
2 S3 C4 C1
S4 Off S1 On VDC - VC4
VDC
0
i
dV = pri VC1
2C
dt
3 S3 D1
S1 On S3 Off 0
VDC
0
VDC
0
4 D1 C3 C2
S3 Off S2 On 0
VDC - VC3
i
dV = pri
2C
dt
VDC
-VC3
5 S1 S2
S2 On S1 Off 0
0
VDC
VDC
-VDC
6 S2 C1 C4
S1 Off S4 On
0
VDC
VDC - VC1 -VC4
7 S2 D4
S4 On S2 Off VDC
0
VDC
0
8 S4 C2 C3
S2 Off S3 On VDC
−i
dV = pri
2C
dt
VDC - VC2 0
EE
−i
dV = pri
2C
dt
155
0
VC2
V. Ramanarayanan
Table II
Sequence and governing equations of the secondary rectifier intervals
U Devices
1 Dp
From
iD
n
≤ 0
2 D p , D n V sec ≤ L Lk d i
2 d t Dp
3 Dn
iD
p
≤ 0
4 D p , D n V sec ≥ −L Lk d i
2 d t Dn
iD
To
L
V sec ≤ Lk d i D
2 dt p
iD
p
≤ 0
V sec ≥
iD
n
−L Lk d
i
2 d t Dn
≤ 0
p
iD
n
V in
L∗
iL
0
V sec
L + L Lk
iL − i D
n
d i = −V sec
dt
L Lk
0
L
0
iL
−V sec
L + L Lk
d i = V sec
d t L Lk
iL − i D
0
L
p
The next interval is reached only when the transformer voltage changes polarity and D n gets
forward biased. From Fig. 5a, the condition for D n to be forward biased, can be derived as
−V sec ≥ V sec − L Lk . d i Dp
dt
(9)
During this interval 2, known as the overlap interval, both D p as well as D n conduct,
resulting in zero voltage across P and Q. The current through D p decreases at the rate given
by,
V
d i
= sec
Dp
L Lk
dt
(10)
and when it reaches zero, the next interval begins where D n alone conducts. The equations
valid in each of the four rectifier intervals are listed in Table II. The next section outlines the
design strategy for achieving ZVS.
Design considerations to achieve ZVS
From the analysis of the PMC, it is important to note that there are two types of transitions. One is from the power transfer mode to the freewheeling mode (inverter intervals 2 and
6) and the other from the freewheeling to the power transfer mode (intervals 4 and 8). From
the ZVS viewpoint, these two transitions are quite different. In the transition from power
transfer to freewheeling mode, referred to as the right-leg transition, the reflected load current
is always in the proper direction to discharge the capacitance of the MOSFET to be turned on.
Hence the load current aids the magnetising current in achieving ZVS. In the other transition,
referred to as the left-leg transition, the reflected load current begins to reverse direction, the
rate of reversal being determined by the leakage inductance. Once the load current reverses
direction, it opposes the magnetising current in the discharge of the MOSFET capacitance.
Hence the left-leg transition is more critical from the ZVS standpoint. The design equations
are therefore, derived to achieve ZVS in this transition, which automatically ensures ZVS for
the other transition too.
Apart from the magnetising and leakage inductances, the other parameter which affects ZVS, is the dead time [T Delay ] allowed between the turn-off of a MOSFET and the
subsequent turn-on of the other MOSFET in the same arm. All these parameters along with
their qualitative effects on ZVS, are given in Table III.
156
Switched Mode Power Conversion
Indian Institute of Science
Table III
Parameters affecting ZVS and their qualitative effects
Variable
Positive effect
Negative effect
Magnetising
current
Aids ZVS
Higher current stress and conduction loss
Leakage
inductance
Aids ZVS, by
reducing the rate of
reversal of the primary
current in the
intervals 4 and 8.
Reduces the maximum effective duty ratio; hence
poor VA utilisation and more conduction loss.
Results in higher ringing and dissipation in the
secondary rectifiers
T Delay
Large TDelay aids ZVS Large TDelay reduces the effective duty ratio and is
particularly undesirable at very high switching
at light loads and
frequencies
affects adversely at
high loads.
Capacitance
across the
MOSFET- CDS
Large CDS aids in
lossless turn- off
Large CDS demands more energy to be stored in
the transformer inductances, to be fully
discharged, hence bad for ZVS
From the equations valid for the fourth inverter interval (left-leg transition which is the crucial
one for ZVS) the following expression can be derived, for the voltage V C2 across the
MOSFET to be turned on.
VC
= VDC − (i m + i refl )
2
Leq
sin ω t
2C
(11)
where,
ω =
1
2C.Leq
L eq = L ∗Lk L m
; ( L ∗Lk - leakage inductance referred to the primary)
The above expression gives the following two conditions to achieve ZVS at any given load.
1. (i m + i refl )
2. T Delay = π
2
L eq
2C
≥ V DC
2C.L eq
(12)
(13)
The first condition ensures that the peak of the sinusoidal component of Eq. (11) is atleast
equal to V DC , so that V C2 eventually reaches zero. The second condition ensures that the
MOSFET is switched on when V C2 is zero. Hence the design strategy is to,
1 Select T Delay considering the switching frequency and the MOSFET
characteristics.
2 Calculate the value of L Lk from Eq. (13), with the above value of T Delay .
3 With the above value of L Lk , calculate from Eq. (12), the peak magnetising
current required at any load down to which ZVS is required.
EE
157
V. Ramanarayanan
The full system may be numerically simulated with the help of equations listed in Tables I and
II, and using the above values for delay time, magnetising current and leakage inductance as
initial estimates. From repeated simulation runs, more satisfactory design values for all the
parameters may be found.
Development Examples
The following specifications refer to two PMC rated for 560W and 30W respectively
developed at the Indian Institute of Science.
Model 1
Model 2
Input
: 150-270V ac, 50Hz
30 - 52 V dc
Output voltage
: 28V
5V
Maximum output current
: 20A
6A
Output regulation
: 0.1%
0.1%
Output ripple (peak to peak)
: 0.5%
0.5%
Switching frequency
: 250 kHz
500 kHz
Efficiency
: 82%
Power Density
84%
3
: 5 W/inch
3
7.5 W/inch
Conclusions
The various technologies which are evolving in the area of soft switching converters,
are the resonant load, resonant switch and the resonant transition converters. The first two
were briefly reviewed and the third was covered in detail. With its ZVS characteristics and
constant-frequency control, the phase-modulated full-bridge converter is well suited for
high-voltage and high-power applications. Results obtained on a 560W/250kHz off line converter, and a 30W/500kHz dc to dc converter are presented to substantiate this claim.
The advantages of PMC are more striking in applications where the range of input
variation is not too wide. One such important application area is in high-power converters
with front end power factor control [PFC] scheme.
158