Overview
Advanced AD/DA converters
• 2nd-order CT modulator
Example of CT ΔΣ Modulator
Pietro Andreani
Dept. of Electrical and Information Technology
Lund University, Sweden
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2nd-order DT modulator (already treated)
Example of CT ΔΣ modulator
2
2nd-order CT modulator
Microphone front-end, micropower operation (50μA, 1.8V), no pre-amp
and anti-alias Æ CT DSM with input range of ±20mV, OSR≈300 –
we want to achieve an SNR of 80dB
a = 0.2653,
0.2212
b = 0.2653,
0,
c = 0.3185,
0
5.5874 (c2 is not important in a single-bit quantizer)
Rounding Æ
a1 = 1/4, a2 = 1/4, b1 = 1/4, c1 = 1/3
From simulations, effective quantizer gain (including c2) is approx. 16/3,
and the NTF is
2
⎛ z −1 ⎞
NTF ( z ) = ⎜
⎟
⎝ z −1 3 ⎠
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Example of CT ΔΣ modulator
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Example of CT ΔΣ modulator
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2nd-order CT modulator – II
Coefficient values
2nd-order single-bit, OSR=300 Æ SQNR > 100dB, good margin for
achieving an overall SNR of 80dB
Determination of CT coefficients – we start setting c1 and c2 to unity in
the DT modulator (they only affect internal signal scaling) – the new a1,
a2 coefficients in the DT modulator become
1 116 4
c1 = 1
a1 ( = b1 ) = a1c1c2 =
= = 0.4444
43 3 9
1 16 4
c2 = 1
a2 = a2c2 =
= = 1.3333
43 3
CIFB topology avoids peaking in the STF
DAC timing: [0.5 1.5] Æ duration of one clock cycle, with a delay of ½
clock cycle Æ enough for quantizer to resolve its input and for DAC
setup time (overkill in this case, but example of a typical choice)
We start with the same NTF as in the previous DT modulator:
We have already described the algorithm to find a1,CT and a2,CT from a1
and a2. However, in this case the input pulse that determines the CT
impulse response is still developing when the first sample is taken at t=1
(since the input pulse stops at t=1.5) Æ two CT coefficients are not
enough to establish the identity between DT and CT!
2
⎛ z −1 ⎞
NTF ( z ) = ⎜
⎟
⎝ z −1 3 ⎠
?
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Example of CT ΔΣ modulator
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Coefficient values – II
Simple calculations yield
2
⎧1
⎪ 2 a1,CT (1− α1 ) + a2,CT (1− α2 ) = a2,DT
⎪⎪
⎨⎧ a1,CT ( β1 − α1 ) = a1,DT
⎪⎪⎨
2
2
⎪⎪a1,CT α1 − β1 + a2,CT ( β2 − α2 ) = −a1,DT + a2,DT
2
⎩⎪⎩
nd
integrator
DT
DAC pulse
→
a2,DT
→ a1,DT ( n −1)
⎧⎡ 1 −sα T −sβ T ⎤ a2,CT
⎪⎢ ( e 2 − e 2 ) ⎥ ⋅
⎦ s
⎪⎣ s
⎪⎪
CT ⎨
⎪⎡ 1 −sα1T −sβ1T ⎤ a1,CT
− e )⎥ ⋅ 2
⎪⎢⎣ s ( e
⎦ s
⎪
⎩⎪
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1st
output of
integrator
→
→
if n = 1
if n ≥ 2
Three equations, two variables Æ cannot be satisfied Æ the extra
equality at n=1 requires an extra variable, a3,CT, which only affects the
impulse response at n=1!
⎧⎪ a2,CT (1−α2 ) if n = 1
⎨
⎪⎩a2,CT ( β2 −α2 ) if n ≥ 2
2
⎧1
if n = 1
⎪ 2 a1,CT (1−α1 )
⎪
⎨
2
2
⎪a1,CT ⎡⎢( β1 −α1 ) n + α1 − β1 ⎤⎥ if n ≥ 2
⎪⎩
2 ⎦
⎣
Example of CT ΔΣ modulator
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Coefficient values – III
Conversion equations again, but here we have to make a special case
for the sample at n=1
output of 2
⎧ a2,DT
⎪ z −1
⎪
⎨ a
⎪ 1,DT 2
⎪⎩( z −1)
Example of CT ΔΣ modulator
!
7
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Example of CT ΔΣ modulator
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Coefficient values
Also with the Toolbox
New equations:
2
⎧1
⎪ 2 a1,CT (1− α1 ) + a2,CT (1−α2 ) +a3,CT = a2,DT
⎪⎪
⎨⎧ a1,CT ( β1 − α1 ) = a1,DT
⎪⎪⎨
2
2
⎪⎪a1,CT α1 − β1 + a2,CT ( β2 − α2 ) = −a1,DT + a2,DT
⎪⎩⎩
2
This can be accomplished also with Matlab code using several functions
in the DS toolbox
if n = 1
% Desired NTF and its impulse response
NTF = zpk([1 1], [1/3 1/3], 1, 1);
% zpk (zeros, poles, gain, sampling period)
n_imp = 3;
% 3 samples to determine 3 aCT coefficients
y_desired = impL1(NTF, n_imp);
% impulse response of L1, 3 samples
% State-space description of CT loop filter as a 3-input, 1-output system
Ac = [0 0; 1 0];
Bc = [-1 0 0; 0 -1 0];
Cc = [0 1];
Dc = [0 0 -1];
td = 0.5;
% input delay from DACs
⎧x = Ax + Bu
sys_c = ss(Ac, Bc, Cc, Dc);
% sys_c embodies the CT state-space system ⎨
set(sys_c, 'InputDelay', td*[1 1 1]);
⎩ y = Cx + Du
% CT-to-DT conversion and associated impulse response
sys_d = c2d(sys_c, 1);
% c2d(sys_c, sampling period, conversion method)
imp_res = impulse(sys_d, n_imp); % impulse responses, one from each of the 3 inputs
yy = squeeze(imp_res);
% 3 response columns merged into a single array
% Solve for coefficients aCT Æ aCT= yy-1*y_desired
% The first row in yy and y_desired is zero (sample for n=0) and must be removed
aCT = (yy(2:end, 1:end))^(-1)*y_desired(2:end);
if n ≥ 2
With α1 = α2 = 0.5, β1 = β2 = 1.5 , we obtain
4
a1,CT = = 0.4444
9
4
a2,CT = = 1.3333
3
11
a3,CT = = 0.6111
18
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Example of CT ΔΣ modulator
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State-space formulation of CT modulator
0
x1
Ideal implementation Æ attenuation for frequencies aliasing to the
passband is over 130dB! – finite DC gain in the loop filter makes the STF
larger, but an alias suppression larger than 80dB is easily achievable
⎡ x1 ⎤
⎢ ⎥
⎡ x1 ⎤ ⎡0 0 −1 0 0 ⎤ ⎢ x2 ⎥
⎢
⎥
⎢ x ⎥ = 1 0 0 −1 0 ⎢ v ⎥
⎥ 1
⎢ 2⎥ ⎢
⎢ ⎥
⎢⎣ y ⎥⎦ ⎢0 1 0 0 −1⎥ ⎢v2 ⎥
⎣
⎦
⎢⎣ v3 ⎥⎦
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x1
x2
x2
y
Example of CT ΔΣ modulator
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Anti-aliasing
State-space formulation of the CT modulator – we put all c’s to unity and
consider the three a’s as three separate inputs, y being the output
⎧x = Ax + Bu
⇒
⎨
⎩ y = Cx + Du
Example of CT ΔΣ modulator
STF = L0c ( s ) NTF ( z )
v
11
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Example of CT ΔΣ modulator
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Component values in active-RC design
Component values in active-RC design – II
We start assuming C1 = 1pF; C2 = 0.1pF; I3 = 1μ A
We can find R1 with bV
1 fs =
Vfs
bV
1 fs =
(with Vfs=1 in a 1-b modulator) Æ
R1 fclk C1
Vfs
R1 fclk C1
→ R1 =
1
b1 fclk C1
;
aV
1 ref =
Vref
RDAC1
⋅
I
1
≡ 1 → I1 = aV
1 ref fclk C1
fclk C1 fclk C1
Vref = 1 in a 1b quantizer
this equates the output of the 1st DT integrator with the output of the 1st
CT integrator after a sampling period of 1/fclk
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Example of CT ΔΣ modulator
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Component values in active-RC design – III
R1 =
1
b1 fclk C1
I2 = a2 fclk C2 = 0.87μ;
≈ 346k;
R2 =
R3 =
Dynamic range scaling could be done using the DT model of the
modulator, but it would be valid only at the sampling instants Æ
simulation on a behavioral model of the CT modulator is better
a3
= 611k
c2 I3
Simulations show peak values of 1.6V and 3.5V at the output of the first
and second integrator, while we desire maximum peak swings of 0.5V
1p
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Example of CT ΔΣ modulator
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Dynamic range scaling
I1 = a1 fclk C1 = 2.88μ
1
= 1538k;
c1 fclk C2
Example of CT ΔΣ modulator
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0.1p
346k
1538k
2.88μ
0.87μ
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611k
1μ
Example of CT ΔΣ modulator
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Dynamic range scaling – II
Dynamic range scaling – III
Scaling for maximum peak swings of 0.5V yields
1p
0.1p
346k
1538k
2.88μ
0.87μ
346k
Increase I1 to 10μ (good for noise performance), and I2 to 1μ for simplicity,
and re-scale:
3.2 p
0.7 p
346k
481k
87.3k
611k
2.88μ
1μ
1p ⋅ (1.6 0.5) = 3.2 p 0.1p ⋅ ( 3.5 0.5) = 0.7 p
481k
87.3k
2.88μ
0.87μ
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346k ⋅ ( 2.88 10) = 100k
1μ
Example of CT ΔΣ modulator
10μ
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Dynamic range scaling – IV
100k ⋅ ( 25m 1) = 2.5k
10μ
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1μ
1μ
1μ
1μ
Example of CT ΔΣ modulator
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Complementary DAC (3dB noise advantage on non-complementary, as it
only needs half as much current); current source are implemented with
large and long MOS, with as high an overdrive as possible (leaving just
enough range at the output) to minimize their noise contribution – in fact:
the noise of the MOS current source is in2 = 4kBTγ gm Æ gm must be
minimized for a given current
2I
gm = ds minimized Æ the overdrive must be maximized (as Ids is given)
Vod
DAC
0.81p
417k
0.7 p ⋅1 0.87 = 0.81p
417k
87.3k
C1 is 11pF Æ rather large area Æ C1 is inversely proportional to the clock
rate Æ favorable having a relatively high clock frequency!
1μ
11p
11p
1μ
Implementation issues
Finally, setting the FS input level 25% higher than the desired FS=20mV,
the input resistance is rescaled as below:
11p
0.81p
100k
417k
87.3k
10μ
0.87μ
87.3k
non-complementary DAC
Latch
1μ
Example of CT ΔΣ modulator
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Example of CT ΔΣ modulator
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Implementation issues
Implementation issues – II
Furthermore: very long MOS have a low 1/f noise (which decreases
with L2 ); in this design, the DAC1 white current noise density is
I DAC1,noise = 0.4 pA
2
⎧
⎫
⎛
⎞
0.5( 20 ⋅10−3V )
0.5Vsig2 ,FS
⎪
⎪
⎟
SNR = 10log ⎜
10log
=
⎨
⎬ = 87dB
2
2
2
4
−9
⎜ ( 2 ⋅ R1 ⋅ I DAC1,noise )2 + 4kBT ( 2R1 ) ⎟
⎡
⎤
2
9
10
V
Hz
10
Hz
+
⋅
⋅
⎪
⎪
(
)
(
)
⎝
⎠
⎦⎥
⎩ ⎣⎢
⎭
Hz
which across the input resistances becomes
VDAC1,noise = 2 ⋅ R1 ⋅ I DAC1,noise = 2 nV
Hz
This is much lower (i.e. poorer) than the SQNR Æ doubling the DAC1
current (and C1) would halve R1, and the SNR would improve by 3dB
(since I DAC1,noise increases by 3dB) – however, we cannot afford this,
since most of the current will be needed in the first opamp (remember
that our budget is 50uA), which must be low noise and capable to
source/sink the sum of the input current and DAC1 current
This should be compared to the noise of the input resistors,
VR1 ,noise = 4kBT ( 2R1 ) = 9 nV
Hz
Thus, DAC1 noise is 12dB below the input noise; the SNR due to input
resistors and DAC1 only is
2
⎧
⎫
⎛
⎞
0.5( 20 ⋅10−3V )
0.5Vsig2 ,FS
⎪
⎪
⎜
⎟
SNR = 10log
= 10log ⎨
⎬ = 87dB
2
2
2
4
−9
⎜ ( 2 ⋅ R1 ⋅ I DAC1,noise )2 + 4kBT ( 2R1 ) ⎟
⎡
⎤
⎪ ( 2 + 9 ) ⋅ (10 V ) Hz ⎥ ⋅10 Hz ⎪
⎝
⎠
⎦
⎩ ⎢⎣
⎭
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Example of CT ΔΣ modulator
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Implementation issues
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Implementation issues
Assuming that a class-A opamp is used, the bias current in each output
leg must be at least 5uA to match DAC1 – to reduce the maximum-tominimum current ratio in the output devices, 10uA is a more reasonable
value
Assuming the input-referred noise of the opamp to be the same as that
of the input resistors, and that its 1/f noise is negligible, we must have for
each MOS in the input pair:
2
1 1
= 9 nV Hz
→ gm = 270 μ A V
4γ kBT
Input-referred
gm 2
voltage noise
(
Example of CT ΔΣ modulator
Two-stage architecture is needed – output stage is cascoded, so that the
output resistance is comparable (hopefully higher) to R2=420K
(compensation and common-mode feedback are not shown)
The second amplifier in the modulator is required to supply currents that
are approx. 10% of those of the first amplifier Æ scaling down the first
amplifier by a factor 10 yields a second amplifier with negligible noise
and distortion contributions
)
Assuming a square-law MOS, and an overdrive of 100mV, we obtain
gm = 2I D Vod
→ I D = 14μ A
In a single-stage amplifier the current in the input differential pair flows in
the output legs as well, which might seems a good feature to achieve
both low noise and adequate output current – unfortunately, the
transconductance of the input pair is gm 2 = 135 μ A V Æ the differential
voltage at the opamp input corresponding to an output current of 5uA will
be close to 20mV, which is the assumed full-scale input (i.e., no margins)
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Example of CT ΔΣ modulator
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Example of CT ΔΣ modulator
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Implementation issues
Low-power comparator – 1uA of bias current, since speed requirement
are relaxed, and the modulator is tolerant to the comparator offset
Power consumption of 5uW with a clock of 6.5MHz.
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Example of CT ΔΣ modulator
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