A Wide-Band Low Noise
Amplifier Synthesis
Methodology
Abhishek
Jajoo
2005
Advisor: l~rof. Mukherjee
A Wide-Band Low Noise Amplifier Synthesis
Methodology
by
ABHISHEKJAJOO
Athesis submittedin partial fulfillment of the requirements
for the
degree of
Master of Science
August 2005
Departmentof Electrical & ComputerEngineering
CarnegieMellonUniversity
Pittsburgh, Pennsylvania, USA
Advisor: Dr. Tamal Mukherjee
Second Reader: Professor C. Patrick Yue
Abstract
Three generations of a wide-band LowNoise Amplifier (LNA)are designed in a 0.35 p.m
BiCMOS
technology. Thetopology chosen is a noise-canceling topologywith shunt resistive feedbackfor
wide-band matching to 50 D_. The second generation design was fabricated and measured. It had a
measured gain of 17 dB and a bandwidth of 2.6 GHz. Its Noise Figure is below 3 dB over the LNA
bandwidth, with minimum
value of 2.4 dB. It draws 13mAcurrent from a 2.5 V supply. This LNAhas an
excellent figure of merit FOM
= ($2|
x BW)/(NF x PDC)
comparedto the other wide-bandLNAs.
Basedon the experience gained from the first two design generations, a synthesis-based design
strategy is developed.Athird generation LNA
is synthesizedusing this strategy. It optimizesbetweenthe
various noise sources affecting NFwith the other parametersinvolved in the FOM,leading to a LNAthat
outperformsearlier designs by about 2x.
Acknowledgement
EventhoughI amthe author, I don’t deserve the entire credit for this work.Several others have
contributedtowardsits completionandthey, at the least, deservethanksand mention.First of all, 1 would
like to thank myadvisor Dr. TamalMukherjeenot only for his availability for discussions but also his
painstaking efforts in pointing out holes and raising questions during the course of this work, without
whichthis work wouldnot have been possible. He also reviewedthis report and his feedback, led to
significant improvements.
I wouldalso like to thank Professor C. P. Yuefor taking time out of his busy
schedule to read mythesis and suggest improvements.
MaryL. Moore, the executive administrator of Carnegie Mellon MEMS
Laboratory, deserves
special thanks for her effort in smoothingout administrative issues during the time involved in this
research. Shewasalso kind enoughto take time out, at very short notice, of her busyscheduleto proofread
this report.
I have learnt a lot from discussions with mycolleagues - Altug Oz, UmutArslan, Chiung-Cheng
Lo, Hasan Akyol, Fang Chen, Michael Vladimer, Sarah Bedair, Peter Gilgunn, AmyWung,Michael
Sperling, Ryan Magargle, Sounil Biswas - and would like to thank them. They always kept the
environment
very cheerful and werereadily available for discussions andany kind of help.
Finally, I wouldlike to thankmyparents for instilling a senseof self, honestyandlove for learning
in me. I wouldalso like to thank mybrother and all myfriends and relatives whoshowedtheir love, moral
support and encouragement
throughoutthe course of this work.
This workwas funded in part by C2S2,the MARCO
Focus Center for Circuit & SystemSolutions,
under MARCO
contract 2003-CT-888and by the ITRI Lab at Carnegie Mellon.
ii
Table of Contents
Abstract
...........................................................................................................................
i
Acknowledgement
.........................................................................................................
ii
Table
of Contents
.........................................................................................................
iii
Listof Figures
.................................................................................................................
v
Chapter
I Introduction
.............................................................................................................
1
1.1 Narrow-band
vs. Wide-band
LNA
..................................................................................
2
1.2Wide-band
Amplifier
Design
..........................................................................................
3
1.3Technology
Choice
.........................................................................................................
4
1.4LNA
Specifications
.........................................................................................................
4
1.5Figure
of Merit
................................................................................................................
5
1.6LNA
Synthesis
................................................................................................................
6
1.7Report
Outline
.................................................................................................................
6
Chapter
2 LNA
Topology
..........................................................................................................
2.1Topology
Choice
.............................................................................................................
2.2NoiseCancelling
Principle
...........................................................................................
7
7
10
Chapter
3 CircuitSynthesis
....................................................................................................
13
3.1Complexities
in RFDesign
..........................................................................................
13
3.2Automated
Synthesis
...................................................................................................
14
Chapter
4 Results
.....................................................................................................................
21
4.1 First andSecond
Generation
LNA
Designs
..................................................................
21
4.2Measurement
Results
....................................................................................................
24
4.2.1S-Parameters
.....................................................................................................
25
iii
4.2.2Noise
Figure
.......................................................................................................
26
4.2.31 dBInputCompression
Point(ICP)................................................................
27
4.2.4Input-Referred
ThirdOrderModulation
Point(IIP3).......................................
28
4.3Second
Generation
Design
ResultSummary
................................................................
29
4.4ThirdGeneration
Design
..............................................................................................
30
4.4.1NeoCircuit
Synthesis
Results
............................................................................
33
4.4.2Analysis
of the 3rdGeneration
Synthesized
LNAs
...........................................
34
4.4.3Simulation
forExtracted
Circuits
.....................................................................
37
Chapter
5 Conclusion
andFuture
Work
...............................................................................
39
References
.....................................................................................................................
40
Appendix:
Signitieaneeof 3 dBNoiseFigure............................................................
42
iv
List of Figures
Figure 1-I
Multi-band radio receiver front end with (a) narrow-band LNAand (b) wide-band
LNA
................................................................................................................
2
Figure 2-1
Shunt-feedback
common
emitterschematic
...................................................
8
Figure 2-2
LNA
withemitterfolloweras secondstage ....................................................
9
Figure 2-3
Noisecancelingprinciplewithfirst amplifierstage .....................................
10
Figure 2-4
Noisecancelingprinciplewithboth amplifierstages...................................
10
Figure 2-5
Finaltopology
...............................................................................................
11
Figure 3-1
NeoCircuitsimulation time summary
for two point synthesis .....................
15
Figure 3-2
NeoCircuitsimulation time summary
for entire band synthesis ...................
15
Figure 3-3
Smallsignalmodel
of HBT
..........................................................................
16
Figure 3-4
Screenshots of NeoCircuitresults showingthe values of specifications for the best
synthesis
........................................................................................................
20
Figure 4- I
Gain matchingrequirement for maximum
first stage noise cancelling ........
21
Figure 4-2
NeoCircuitvariables andgoals for the first generationdesign.....................
22
Figure 4-3
Measured
S-Parameters
................................................................................
25
Figure 4-4
Noise-Figure
measurement
results................................................................
26
Figure 4-5
Compression
pointplot.................................................................................
27
Figure 4-6
IIP3Plot........................................................................................................
28
Figure 4-7
Wide-band
LNAFigure of Merit vs. Lithographicfeature size ...................
30
Figure 4-8
grn/Icvs. Ic forHBT
.....................................................................................
32
Figure 4-9
NeoCircuitgoals window
with equalweightson all goals ...........................
33
Figure 4-10
NeoCircuitSynthesis results for the (a) first NeoCircuitrun with equal weights (3rd
generation (Initial)
design) and (b) second run with modified weights (3rd genera-
tion(Final)design)
........................................................................................
34
Figure 4-11
NeoCircuitgoals windowwith weights on somegoals changed..................
34
Figure 4-12
ComparingminimumNFand normalized error in first
stage noise cancellation
acrossthreethedesigns
.................................................................................
35
Figure 4-13
Comparisonof gain from transistor Q1 and Q2 across the three designs ..... 36
Figure 4-14
Normalizedtransconductance of transistors
Figure 4-15
Normalizedcollector current IC and (grn/IC) for transistor Q 1 across the three de-
Q1 and Q2 across the three designs 36
signs
..............................................................................................................
37
vi
1
Introduction
Wireless communication
systemsuse electromagneticsignals, with frequenciesin the range of hundreds of kilohertz to several gigahertz, for the transmissionand receptionof informationthroughair. Frequenciesin this range are called radio frequency(RF). In anywireless system,informationto be sent (e.g.,
voice) is first modulated,then put onto the radio frequency(RF)carrier and amplifiedbefore transmission.
Onthe other end, received RFsignals are amplified, convertedto lower frequenciesand then demodulated
to obtain the information (voice) that had been sent. For modem
wireless systems, the wireless channel
interface (also knownas the front end) typically has to deal with GHzfrequencyRFsignals. Althoughsubblocksfor these front ends are analog in nature, their designis muchmorecomplicatedthan classical lowfrequencyanalogdesign. Several factors, such as the ability to operate at low signal powerlevels, high
dynamic-range,impedancematching,coupling and circuit parasitics, makethe design of such front-end
blocks complicated.
Traditional wireless communication
systems are designed for only one communicationstandard.
However,the demandfor convergenceof wireless services, in whichusers can access different standards
fromthe samewireless device, is driving development
of multi-standardand multi-bandtransceivers. Thus,
future RFfront-ends will needto operate over multiple frequencybands. This report focuses on the design
of a sub-block called low-noise amplifier (LNA)for use in a multi-band multi-standard complimentary
metal-oxide semiconductor(CMOS)
integrable receiver front end for portable applications. A typical
receiver front-endlooks likes one of the multipleparallel armsshownin Figure1-1. In addition to the LNA,
the front-end is comprisedof an antenna, a band-passfilter (BPF), a voltage-controlled oscillator (VCO)
and a mixer. TheLNA
is required to amplifythe signal in the bandselected by the BPF,from a widerange
of frequencies. Theamplifiedsignal from the LNA
can then be convertedto a lowerfrequencyby the mixer.
Antenna
~
Mixer
BPF
Antenna
Narrowband
, LO,. ’~
Antenna
~
~)
VCOn
Mixer
BPF
Narrowband
, Lo,l ]"
Figure 1-1 Multi-bandradio receiver front end with (a) narrow-bandLNAand (b) wide-band
For any RFfront-end, several design decisions need to be made.The first is the overall architecture.
Oncethe architecture is selected, the circuit topologies for various sub-blocks need to be designed, next is
the choice of fabrication technology. The issues involved in these decisions are outlined in the following
three sections. They are followed with a definition of the key LNAspecification parameters. Target values
for these specifications will also be decided. Next, these specifications will be combinedto a single parameter, called the figure-of-merit (FOM).
1.1 Narrow-band vs. Wide-band LNA
The optimal LNAshould add only the minimumamountof noise as it amplifies the signal, increasing the overall signal-to-noise ratio after it is done. This noise performancecharacteristic of an LNAis measured by its noise figure (NF). The lower the NFthe better the LNA,as it meansless noise is added by the
LNAcompared to its gain. LNArequirements for the multi-band multi-standard receiver described in the
previous section could be satisfied in two ways. First, it could be accomplishedby using multiple input stage
for each frequency band of interest.
This will require multiple classical narrow-bandLNAs[ 1 ] as done in
[2] and shownin Figure 1-1 (a). The second option is to use a wide-bandLNAin conjunction with a tunable
BPFas shownin Figure 1-1 (b).
The advantage of the first approach is that the performance of each front-end can be optimized for
each frequency band. However,as each of the LNAsis typically LCtuned and integrated inductors are the
most area consuming on-chip components, a large amount of chip area is required. This increased area
implies high cost. On the other hand, the second option of using a wide-band LNAallows some hardware
sharing and has the area, hence cost advantage. Wide-band LNAbased RF front-end with multiple BPF
have been reported in [3] and [4]. In these examples, the LNAis shared, however, the BPFfilters
The obvious extreme end for this trend is sharing both the LNAand the filter,
are not.
as shownin Figure 1-1(b).
Such an architecture is nowfeasible with the potential for a CMOS
compatible tunable BPF[5]. As a result
of these advantages and trends, this report focuses on a single wide-bandLNAarchitecture.
1.2 Wide-band Amplifier Design
A variety of wide-band amplifier designs have previously been proposed. One approach is the distributed amplifier, in which several lumpedinductor and capacitor elements interconnect simple amplifier
topologies as in [6]. In this approach, each stage adds to the gain. Dueto the multiple stages, there is a high
componentcount. Each of the manyactive and passive devices introduce noise into the system, which adds
up to an overall NFthat is too large for LNAapplications. To reduce the noise from the active devices, the
number of the active devices can be reduced. Thus, fewer amplifier stages are desirable. Although ideal
(loss-less) inductors have no noise sources, practical inductor implementationshave loss, and therefore, also
act as a noise source. Inductor noise can be completely eliminated by using an inductor-less topology. This
also substantially reduces the circuit area, as on-chip passives occupy larger chip area comparedto active
transistors.
The resulting noise in these inductor-less topologies is solely from the transistors. To further
reduce this noise, an approach that removessomeof the injected transistor noise in the widebandLNAsis
desired. This report uses one such inductor-less, noise cancelling topology [7].
1.3 Technology Choice
RF front-ends have been designedin a wide variety of technologies, including GalliumArsenide
(GaAs), Silicon Bipolar Junction Transistor (BJT), RF CMOS
and Silicon Germanium
(SiGe) BiCMOS.
The desire for integration with CMOS
baseband componentslimits our choice to RF CMOS
and SiGe
BiCMOS
technologies. The advantage of such an integration will be reduced system size and cost (both
reducedas there are fewerdiscrete components
to assembleon a board). SiGebipolar transistors, also called
HBTs(HetrojunctionBipolar Transistors), have higher gm/! and better noise characteristics comparedto
CMOS
transistors [8]. This higher g,~/I implies moregain for the sameamountof bias current (which is
directly proportional to powerconsumption).Thehigh gain can be traded off to improvethe NF,by burning
less current whichwill reducethe shot noise generatedby the transistors, as shot noise is proportionalto the
bias current. Also, the HBThas better parametricyield as its performance
dependson the vertical diffusion,
a geometricalparameterthat is less variable than the CMOS
lateral gate length. Therefore,the LNA
will be
designed in a SiGe BiCMOS
technology.
1.4 LNASpecifications
Performancespecifications used to characterize a LNAinclude noise, power gain, impedance
matching,powerconsumptionand bandwidth.In this section wedefine the LNAspecifications and specify
their target values.
Noiseaddedby any circuit or systemis characterized by a term called NF.It can be shownthat NF
of 3 dBmeansthat the signal-to-noise ratio (SNR)degradesby factor of two. Asderived in detail in the
appendix,this wouldmeanthat the noise poweraddedby the systemwill be sameas the noise at the input
amplified by the amplifier gain. Thus,the target value for the NFis set to be below3 dBover the entire
bandwidth.
Havinga high power-gainis equally important as having low noise. In RF terminologygain is
reported as S:1. In the overall systemNFexpression,noise of the followingstages in the cascadeare divided
by the powergain of the LNA.This means that high gain LNAwill reduce the ability of the following stages
to degrade the systemSNR.Basedon [ 1], [6], [7], the target value of the $21 is set to be greater than 15 dB.
50 f~ is a standard impedancefor most of the RF waveguides used to connect LNAchips with offchip filters
or mixers. For maximum
power transfer, most RF circuits are designed to have input and output
impedancesof 50 V~. Whenthe interconnect is on-chip (meaningthat they are muchshorter than the wavelength at the desired frequency of operation) the interconnect does not behave as a waveguideand matching
to 50 f~ is not required for maximum
power transfer. However,as the LNAwill be tested stand alone using
50 f~ RF measurementcables and test equipment, the input and output impedance are designed to match to
50 f~. $11 and $22 are measures of the input and the output match. A value of-10 dB means matching to
within 20 %. Therefore the target value for Slz and S:2 is set to be below -10 dB over the entire usable bandwidth.
The bandwidth (BW)of the amplifier was set by the range of frequencies that the multi-band
receiver front-end has to support. The target value for the bandwidthis set to be 2.5 GHzso that LNAcovers
AMPS,PCSand ISMbands. Another goal was to minimize the power consumed to enable long operational
life in a limited battery powerportable application.
1.5 Figure of Merit
One LNAcircuit
mayhave a larger BW,while another may have a larger gain, making comparison
between different LNAsdifficult.
To enable such a comparison, designers typically mapthe multitude of
circuit specifications into a single scalar figure of merit. For the case of the wide-bandLNAthe FOMis
defined as:
FOM -
$21 x BW
NF x P DC
(~.~)
It takes into account the power gain ($21), bandwidth (BW), noise figure (NF) and power consumed
(PDc)" It is inspired by expression for FOMfor narrow-band LNAsin [9] but includes the BWterm as this
report focuses on wide-band LNAs.Clearly the best circuit will have the highest FOM.
1.6 LNASynthesis
The need to simultaneously meet multiple specifications
makes RF circuit design complicated. To
managethe design complexity, we use an automated circuit synthesis approach similar to [6]. Individual
design constraints for each specification is combinedwith FOMmaximization to obtain the best possible
design.
1.7 Report Outline
Chapter 2 discusses the LNAtopology choice and principle of operation. Chapter 3 describes the
design methodologyusing automated design tool NeoCircuit®. Chapter 4 presents the results (synthesis,
simulation and measurement)and their comparisonto the literature.
Chapter 5 concludes the thesis and out-
lines future plans.
6
LNA Topology
The architecture and technology decisions in the previous chapter constrain us to a widebandLNA
implemented in SiGe BiCMOS
technology. Wenow need to select the circuit
topology before we can size
and bias the transistor schematic. This chapter will start by describing the design issues affecting the LNA
topology, and lead to the choice of the noise-cancelling topology for the LNAdesigned in this report.
2.1 Topology Choice
ManycormnonLNAtopologies are ruled out either because of their inability to provide impedance
match over the wide range of frequencies or their inability
to provide wide bandwidth with low NF[7].
Therefore, we start with a basic single-stage amplifier topology and expandon it to arrive at the final topology by considering requirements for the LNAone at a time. Each time we fail to meet the desired requirement, a topology change will be instituted
to help extend the LNA’sperformance.
Power gain is a primary performance specification for the LNA.Our starting point is one of the
three simple single-stage amplifier topologies, namely common-emitter(CE), common-collector (CC)
common-base(CB). Of these, the common-emitter(CE) is the only topology with both voltage and current
gain. This meansthat it is capable of giving powergain, in presence of either current or voltage as input.
Unfortunately, the CEtopology has an input impedancethat is too large for RF applications. A resistive
shunt feedback as shownin Figure 2-I can reduce the input impedance to achieve 50 ~ over a wide range
of frequencies.
Assuming thin
(a) the extrinsic base resistance %,
-y
JBias
R~
VOUT
R$
Figure 2-1 Shunt-feedbackcommonemitter schematic
(b) the feedbackresistance RF,~ ro (the transistor output resistance)
(c) current gain 13 is large
then the small signal gain, input and output impedanceof the circuit in Figure 2-1 are given by [ 10]:
Setting
AV = -(gmlRF - 1)
(2.l)
Rin = 1/gml
(2.2)
Rout = (R S+ RF)/2
(2.3)
Rin = RS = 50~ = Rout in equation
(2.2)
& (2.3)
grnl = 1/(50~). Plugging gml and RF into equation (2.1) unfortunately
leads
RF = 50~2
and
implies zero gain, because
impedancematching (input and output) conditions are both coupled to the gain. In the above equations there
are three constraints (gain, input and output impedance)and two variables or degrees of freedom (gm 1 and
RF). Therefore the three constraints cannot be met independently. Decoupling these three constraints
requires adding one more variable. Wecan obtain that by adding a second stage, as shownin Figure 2-2.
For implementingthe current source, lej~s , in Figure 2-1 a p-type metal oxide semiconductorfield
effect transistor
(MOSFET
or MOS)is preferred over BJT. This is because MOScurrent sources require
less voltage headroomcomparedto BJT current sources. In a PNPtype BJT the emitter-base (EB) junction
has to be forward biased and the base-collector (BC) junction has to be reverse biased. The voltage head-
Q3
RF
VOUT1
CHp
R
S
VB~s2
Figure2-2 LNAwith emitter follower as secondstage.
roomneeded by such a PNPsource, is set by the emitter-collector
(EC) voltage. This ECvoltage has to
more than the EBvoltage. In a PMOS
current source, the voltage between source and drain, which is the
voltage headroom, has to be greater than gate-source voltage, minus the threshold voltage. This means the
source-drain voltage can be less than gate-source voltage and the device will still work as a current source.
Furthermore, the HBTturn-on emitter-base voltage is higher than the CMOS
gate-source threshold voltage.
Thus, MOScurrent sources require less voltage headroomcomparedto HBTcurrent sources. Moreover, the
PNPtype HBTis typically
not available in SiGe BiCMOS
processes.
The high-pass filter constituted by R~ze and C~ze is used to independently bias the two stages. This
new second stage decouples the gain and the output impedancematch requirements, as output impedanceis
now determined by the output impedance of the emitter follower (second stage). However,this is at the
expense of the added noise from the additional devices in the second stage. Note that this second stage does
not provide any additional gain, but does add to the noise. Somenoise reduction is possible by modifying
this circuit to cancel someof the generated noise. This approach is described in the next section.
Figure2-3 Noisecancelingprinciple with first amplifier stage
2.2 Noise Cancelling Principle
The noise cancelling principle [7] is explained using Figure 2-3 and Figure 2-4. It takes advantage
of the resistive feedback through Re, to cancel the noise from the transistors Q1and el. The noise originating in these transistors appears at the output of the first stage ( Four~). The resistor RF causes this noise to
appear at the input (FtN) with some attenuation. The exact value of this attenuation can be calculated
using the small signal modelof the first stage. A detailed derivation of the expression of the attenuation
factor ,4 can be found in [10]:
Figure2-4 Noise canceling principle with both amplifier stages
10
Figure2°5 Final topology
A = R--F+ 1
RS
(2.4)
Theinput signal at v~uis amplifiedto the first stage outputaccordingto equation(2.1). Sincethe
valueof the gain is negative,the amplifiedsignal at Vo~.rlwill be out of the phasewith the input signal. As
the valueof the attenuationfactor is positive, the attenuatednoise at the input will be in phasewiththe noise
at Vouv~,as shownin Figure2-3. This property of the circuit can be exploited to cancel someof the noise
originating in transistors
QI
and P/-
Noisecancelling can be achievedby connectingan inverting amplifier of gain -,4, whichis negative
of the attenuation factor seen by the noise at Vourlas it is fed backto vtN, and summing
its output with
Vo~r~,as shownin Figure2-4. In this amplifier, both the desiredsignal andthe attenuatednoise at the input
are amplified and undergophase inversion. It can be easily seen (and is shownin Figure 2-4) that when
inverting amplifier output is summed
with the signals at Vo~r~,the noise gets cancelledand desired signals
add up.
Atransistor implementationof the conceptdemonstratedin Figure 2-4 is shownin Figure 2-5. The
reasoningfor the sizing relationships betweenthe deviceshas beenarrived at previously[ 10]. Thesumming
circuit is implemented
using transistor Q3.Inverting amplifier is implemented
using transistor Q_,. In order
11
to set its gain to be -/1 the ratio gmQ2/gmQ3
has to be set to be equal to -A. The current source is implementedby transistor P~, in Figure 2-5. It robs current from ~73 and helps set this ratio. This device (~o,,) adds
somenoise of its own.However,as it appears after the first gain stage, its noise contribution is not as critical
as the componentsof the first stage. It is shown[10] that the NFof topology in Figure 2-5 is better than that
in Figure 2-2.
The next chapter describes the complexities of designing a wideband LNA.The formulation of a
widebandLNAsynthesis problem is then described, followed by the use of an automated synthesis tool for
synthesizing the amplifier.
12
Circuit Synthesis
Withthe fabrication technology,architecture and transistor schematictopologyselected, the next
task is to determinethe devicesizes andcircuit bias point neededto achieve the desired performance.In
case of RFcircuit designthis couldbe an extremelychallengingtask. This chapter beginswith a description
of the challengesin RFcircuit design, leading to the argumentfor the use of the automatedsynthesis tools
for sizing andbiasing. Followingthis is a descriptionof the synthesis tool usedas well as the formulation
of the wide-bandLNA
design problemfor efficient circuit synthesis.
3.1 Complexities in RF Design
There are manycompetingspecifications like power,noise, gain, linearity and impedance
matching
for RFsub-blocks. At high frequencies device and interconnect parasitic haveto be considered, as they
adversely affect circuit performance.EventhoughRFcircuits have fewer devices comparedto the conventional analog circuits, these factors makeRFdesign extremelycomplex.In such a situation manualoptimization of circuit becomesintractable.
Fierce market competitionand rapidly evolvingstandards are resulting in shorter design cycles.
However,the time required for designinga typical RFcircuit, even for an experienceddesigner, remains
constant, on the order of a few weeks.
Automated
synthesis tools are nowavailable with the promiseof being able to search the design
space faster and moreexhaustivelythan an experienceddesigner. Thedesignsin this report exploit onesuch
commerciallyavailable synthesis tool: NeoCircuit.
13
3.2 Automated Synthesis
Synthesistools suggest a design candidate, evaluate the circuit performance,and then perturb the
design candidate iteratively to improvethe design. NeoCircuitemployssimulation for performanceevaluation and uses an optimization-based
synthesis engineto search the designspace. NeoCircuitusers enter the
circuit topologyand setsup the circuit testbenchesandthe simulationneedsfor evaluatingthe candidatecircuit’s performance.Also, the list of circuit designvariablesandthe list of perforrnancespecifications must
be entered into the software.
NeoCircuitis the circuit optimizationenginefor the customIC designsuite in Cadence.It interfaces
to CadenceVirtuoso SchematicEditor (where the circuit topology is entered by the user) and employs
CadenceSpectreRFto evaluate the performanceof candidate circuits that it considers as it traverses the
design space while sizing and biasing the schematic. TheNeoCircuitUser Interface uses a single window
that is partitionedinto a pagefor eachtype of objectthat the user specifies. Thevariablespageis usedto set
the devicerelationships and independentvariables. At the simulationpage, one specifies simulationinformationand extracts simulationoutput. Computations
on the simulationoutput are entered in the goals page
andusedto define the designgoals. Theresults of the synthesis run can be viewedat the results page.
Thetime required to synthesize a design is governedprimarily by the amountof the time required
to simulateeach candidatedesign. Therefore,one needsto set up the simulationenvironment
carefully. Circuit evaluation of the wide-bandLNA
is ideally performedover the entire desired bandwidth.Frequency
analysis in a circuit simulationrequires time-consuming
matrixinversions for each frequencypoint in the
analysis. So, evaluation over the entire bandwidthbecomescomputationallyexpensive.Asthe Bodeplot of
the frequencyresponseof the noise cancelling LNA
topologyis flat betweenthe high pass filter cutoff frequencyand the amplifier -3 dBfrequency,the linear S-parameteranalysis for the input and output match,
gain and noise specification is performedonly at two frequencypoints in the desired bandwidth.Toverify
this short-cut simulation approach, several synthesis runs weredone with simulation performedover the
entire desired LNA
bandwidthand only at two frequencypoints. These experimentsconfirmedthat simuo
14
Diagnostics
Summary
I Po~nts
[Total NOOSES
Machines
Simulations
7.43
Figure3-1 NeoCircuitsimulationtime summary
for twopoint synthesis
lating at only two frequencypoints leads to less overall synthesis time compared
to whenthe simulationis
done over the entire LNA
bandwidth.Figure 3-1 and Figure 3-2. showNeoCircuitscreenshots for the twofrequencyandmulti-frequencysynthesis runs. Toensure that the flat-gain assumptionin the two-frequency
case remainscorrect duringthe synthesis, the cutoff frequencyof the high-passfilter is constrainedto be
smaller than the lower of the two frequencypoints. Thehigher of these two points is the maximum
input
signal frequencythat needsto be amplifiedby the specified gain.
Diagnostics
Summary
Simulations
Machines
garcia.ece.cmu.edu
hoIIy.ece.crnu.edu
joplin.ece.cmu.edu
jennings.ece.cmu.edu
entwhJstle.ece.crnu
edu
.edu
cobain.ece.cmu.edu
Figure3-2 NeoCircuitsimulationtime summary
for entire bandsynthesis
15
Collector
+
gmV~
[ Emitter
Figure 3-3 Small signal modelof HBT
Non-linear analysis takes muchmore time per candidate evaluation than linear analysis, and hence
is only performed at one of the two frequencies. The frequency dependence of IIP3 can be understood from
the ratio of the Taylor’s series coefficients of the collector current ofa HBT.Gain is proportional to gmRo,t,
where Ro,, is the output resistance of the PMOS
load transistor.
As the MOStransistor is more linear than
the HBT,the non-linearity will be dominated by HBT’snon-linearity. HBTsare more linear at higher frequency, as shown by analyzing the small signal model of an HBT(as shown in Figure 3-3.). Weneed
obtain the relation betweenthe input voltage (Vbe) and output current (I c ), and then use this relation to find
the frequency dependence of IIP3.
The output current I c dependson the effective base-emitter voltage V~r as given by equation (3.1).
in turn, the V~r dependenceon the externally applied voltage Vbe can be obtained by a voltage divider as
shownin equation (3.2).
I c = Ic, sat¯ e
(3.1)
Vbe
~ " 1 + Sr~rC
(3.2)
rb + 1 + sr~rC~r
Gr+ r~, + sr~r~,C~ = H(s)v~
16
TheTaylor series expansionof I c in equation(3.1) is shownin equation(3.3) and also expressed
in termsof vt,
e,
I c = Ic, sat ¯ 1 + V’- T + ~.\"~-/ + .~.\Vr~ + ...
[
= I~
’
s~t"
vx
l(V~_)e
l(Vx)S
V[1
T
+~v bVT? 1
e+~
(~2
Vbe+~ e
]
1
VT)
(3.3)
(~ Vbe+’"~
For time-variant, memo~-lesssystemswith input (x), and ou~ut ~) wecan assumethat [1
y = ao+a 1 .x+a2.x2+a3.x3+
...
(3.4)
and for this systeminput IIP3 is definedas [11],
¯ la31
(3.5)
Onsimilar lines IIP3 for HBT,using expressionof 1c fromequation(3.3), after somesimplification
becomes,
IIP3 -
r2 ~l~ V
H(s)
(3.6)
Pluggingthe expression for H(s), it can be seen that IIP3 improveswith frequency. Thus, liP3
needsto evaluatedonly at the lowerfrequencypoint for the candidatedesignsduringsynthesis. If the liP3
specification is met at the lowerfrequencypoint, it wouldbe met over the entire band.
It should be noted though, that the aboveanalysis considers only the low frequencynon-linearity
behaviour.Theexact frequencydependenceof the I1P3 mustbe considered using Volterra Series with frequencydependentcoefficients [ 12]. Neverthelessfor the objective of setting the optimizationconditionthe
aforementioned
analysis is sufficient as the desired frequencyrange is small to haveanysignificant IIP3
variation.
17
NeoCircuit creates candidate designs are by iteratively changing the value of the device parameters
that had been declared as design variables during the setup process. For the LNAin this report, the variables
used during the synthesis include device geometries (lengths and widths of the MOSgates, polysilicon resistors and MIMcapacitors), device multiplicity as well as the bias current. The technology used is Jazz’s
0.35 ~tm BiCMOS
process with 60 GHZfTSiGe devices. A few select HBTemitter lengths and widths are
available in this technology. NeoCircuit can handle both continuous or discrete parameter sets for design
variables. However,in the Jazz design kit, changes to the HBT’semitter length, width and numberof emitter
require changes to the model namesin the final circuit netlist.
As NeoCircuit cannot change device model
namesduring synthesis, these parameters can’t be set as design variables. Therefore, we manually identified
an emitter geometry such that the HBT’sfr is about 10x the maximumintended frequency of operation
while burning minimumcurrent. Thus, the sole design variable related to the HBTsin the LNAis the device
multiplicity.
The LNAperformance targets also has to be specified during NeoCircuit setup. Goals can be specified as constraints or design optimization objectives. Constraints can be single-sided, specified as an inequality (either less than or greater than a certain value) or double-sided (requiring the parameterto lie in
range). Optimization objectives can be either maximizedor minimized. NeoCircuit allows users to prioritize
betweenthe goals by setting weights. In the presence oftrade-offs amongvarious specifications, optimizing
synthesis by focusing on individual specification can be an impossible task. Therefore, the LNAFOMis
used as a design optimization objective (to be maximizedas described in Section 1.5). Once NeoCircuit
meets the individual performancespecification goals, it will work at improving the critical
goals that are
aggregated in the FOMexpression, thereby improving FOM.The overall synthesis effort can also be set to
be low, mediumor high. Weight and synthesis effort settings affect the way the design space is searched
and determines the outcomeof the synthesis. Therefore, it is important to knowhowto use these features to
get goodsynthesis results. The designs in this report used the following strategy.
18
- Set up the goals to have a weight of one. Synthesize for maximumFOMwith mediumeffbrt.
The
synthesis results help determine if targeted goals are achievable.
- If all goals are met during the first
synthesis run then a second synthesis run with higher
specifications for the critical goal can be attempted
- 1fall goals are not met during thefirst ru, increase the weight on the goals that did not meet the
specified target values. This will force NeoCircuit®to work harder at meeting those goals at the
cost of the other goals. If amongthese ’other’goals there are certain critical
goals which one
would like to be compromisedleast, then one should increase their weights too. For example, if
NeoCircuit®is failing to meet $11 during the first run, then its weight should be increased during
the second run. But if the designer would like to prevent NeoCircuit from trading off the tougher
$1~ specification
with $21, NF and FOM,so weights on these critical
goals should also be
increased This time, synthesize with high effort.
- If goals are still not met then re-synthesize with either of following, until the goals are met:
- Revise target values. They are infeasible for the circuit topology and the fabrication
process.
-lncrease the weights further
To establish the validity of the idea that setting FOMas a goal to be maximizedwill improve the
synthesis results,
two synthesis runs were done: one with FOMas a design optimization objective and
another without it. For these runs, the NeoCircuit synthesis FOMwas defined as
$21
NF × IDC
(as a BWupto
3 GHzwas desired and VDCis a constant, these terms were excluded from the definition in equation (1.1)).
Screenshots of NeoCircuit results for these are shownin Figure 3-4(a) and Figure 3-4(b) respectively.
FOMfor circuit with results in Figure 3-4(b) is 637mcomparedto 937mfor that in Figure 3-4(a). This
idates the claim that setting FOMas a design optimization objective improvesthe synthesis results.
19
Results
Results
Goals
(a)
Figure3-4 Screenshotsof NeoCircuitresults showingthe values of specifications for the best synthesis
20
Results
Three generations of the noise cancelling LNAhave been designed for the 0.35 p.m Jazz BiCMOS
process. The LNAwas sized, either using NeoCircuit or manually. The layout of the sized circuit was then
manually drawn. The first and second generation designs were the initial
forays into using NeoCircuit for
wide-band LNAdesign and are discussed together below. They have been fabricated
and their measured
results are presented. The third generation design used the synthesis strategy described in the previous chapter. It has not yet been fabricated, so only simulation results (after layout extraction) are presented.
4.1 First and Second Generation LNADesigns
Design details for the first generation design are reported in [10]. Althoughit used NeoCircuit for
synthesis, only a few device parameters were considered design variables due to the combination of a lack
of designer experience with NeoCircuit, and a limited amountof design time till the tapeout deadline. Also,
only S-parameters and NFwere defined as goals. The device sizes for this design were related as shownin
Figure 4-1 and described in [ 10] in order to get completefirst stage noise cancellation. As the synthesis strat-
Figure 4-1 Gain matchingrequirementfor maximum
first stage noise cancelling
21
Goals
Design
Device
~ ~
~ F
F F
~ ~...
j DV(~amp 1,an ) F
~ :~A
r r
Name:
(NF’_i2G
...........
~Sl
[S0~:25U:BC0U)
mbl~s2 [3.2m:0,1m:~,0m]
~Li
[2u:l
u,,l
0u)
CHP
2p
~~.j.~
=.~._~
.~,
v~
1
Qsu~MuR
~G ~210~O,E
~LNA_SP,SP
Sll))
:~e~
~sP~Rf/Z 10~O,E O( LNA_SP,SP_SZ 1 ))
~,seFigS~RR120OOOOOOo,Eo
LNA_SP,NOISE, lessthan
(a)
14.5
(b)
Figure4-2NeoCircuit
variablesandgoalsfor the first generation
design
egy describedin the previouschapterhadnot yet beenformulated,FOM
wasneither evaluatednor optimizedduringsynthesis.Thesecharacteristicscan be seen in the screenshots of the NeoCircuit
variablesand
goalswindows
shownin Figure4-2 (a) &(b). In this synthesis, the valueof the feedbackresistance,RF, is
set by an analytic constraint, pResF= (pA + 1)’50. F is t ied t o t he multiplicity o f t ransistor Q2
(Qamp2)
throughvariable pA. This way,the multiplicity of Q2is changedwith the value of RF, so that
the productof gain throughRF andQ2is one, whichis assumedto be the gain throughemitter-follower
(EF). Thusthis assumption
related to completefirst stage noise cancellationconstrainsthe device sizes.
When
the fabricatedcircuit wastested, its measured
NFrose above3 dBwithin3 dBgain bandwidth.
Thus,
the overall usablebandwidth
of this LNA
is limited by the NFandnot by the gain bandwidth.
Thegoal of the secondgenerationdesignwasto solve this problem.Simulations
of the first generation designshowedthat, for the circuit synthesizedby the NeoCircuit,gains of the twopaths, fromthe
outputof the first stage, vovrl, to the overall circuit output,Vou
r (labelled as "Path1" and"Path2" in
Figure4-1), werenot equal. Theattenuationfactor analysis assumed
an ideal emitterfollower gain of 1.
Thus,usingthis analysisin the NeoCircuit
constraintsled to a largergainin "Path2" compared
to "Pathl".
22
Completenoise cancellation of the first stage noise takes place whengains of these two paths are identical.
To keep the NFbelow 3 dB over the entire 3 dB gain bandwidth, the second stage design focus was to match
the gains in these two paths. Reductionin the difference betweenthe gains can be achieved by reducing g,,~,
the transconductance of transistor Q3. This, in turn can be achieved by increasing the current through e.,,
thereby robbing Q3of somecurrent reducing its transconductance. It will not affect the biasing of the transistor Q2, as its biasing point is set by the DCvoltage at node r m. Whichmeansthe current through second
stage will not change. To understand howthis changes the gain difference we will do a first order approximations of the gains through transistors
Q2
and Qj to understand their dependenceon g,~s.
Gain of path "Path 1" is gain through RF multiplied by the gain of the CEstage formed by transistor Q,, with 1/gm3 in parallel with output 50 f~ as load (output impedanceof P2 is assumedto be very large
and therefore ignored). The gain of this CEstage will be:
-gin2" 50
1 + 50. gin3"
(4.1)
It can be easily seen that this will increase with a decrease in gra3" ASattenuation through R
F
depends only on its value [10] it will remain constant. Thus the gain of"Path 1" will also increase with a
decrease in gm3"For "Path 2" the transistor Qj forms an emitter-follower whosegain is given as [ 13]:
1
(4.2)
r ~r +Rs
1+
(flo + 1).
L
r~
Here Rs which is source resistance will be zero, (flo + 1)
r~
1
and RL ~- 50~ since
~ flo - gm3
output impedanceof Q_, will be very large comparedto 50 f~. Plugging these values in equation (4.2) simplifies the EF gain expression to:
1
1+ 50. gin3
(4.3)
23
Table 4.1: MeasuredLNAresponse
Specification
Value
S21 [dB]
17
S ll [dB]
< -8.9
$12 [dB]
<-25.3
S22 [dB]
<-6
BW[GHz]
2.6
NF[dB]
3
ICP [dBm]
-16.5
IIP3 [dBm]
-l. 1
Power [mW]
32.5
2]
Area [~m
90x70
Technology
0.35 ~mSiGe
FOM
0.46
This will decrease with gin3" Thus, as gin3 is decreased, the gain of"Path 2" will decrease and the
gain of "Path l" increases, decreasing the difference between the gains. As output match depends on gin3
[ 10], only a small decrease in g,,3 should be attempted.
Based on this analysis, size ofP2 was changed in order to increase its current. Manualtweaking of
the circuit topology was done to arrive at a design free from the problemobserved in the first generation.
There was no other change madein the first generation topology to create the second generation. It was fabricated and following fabrication, it has been characterized. Its measuredresponse, reported in the next section shows that NFis below 3 dB over the entire 3 dB gain bandwidth.
4.2 Measurement Results
Measurementswere made using high-frequency rated coaxial cables paired with shielded GroundSignal-Ground (GSG)probes on a Cascade Microtech Probe station. Results from the testing of the secondgeneration circuit are listed in Table 4.1. The numbersrepresent the worst case value of each specification
24
within the pass bandof the amplifier, except for the
$21 ,
IIP3 and ICP. $21 is the maximum
value in the
passband,which is itself set by the frequencywherethe gain equals $2/-3 dB. ICPis measuredat 1.5 GHz
and lIP3 with tones at 1.5 GHzand 1.51 GHz.All measurementswere taken with circuit biased at 13 mA
from2.5 V supply. Details concerningmeasurement
setup and calibration can be found in [ 10].
4.2.1 S-Parameters
S-Parameterswere measuredusing an Agilent E8364ANetworkAnalyzer, following calibration of
the high-frequencycables and probes. MeasuredS-Parametersplots are shownin Figure 4-3. $// is shown
$11
II
,!
(a)
J
(d)
Figure 4-3 MeasuredS-Parameters
25
M= andGain
~ NF --
Gain
3dB ~ Poly. (Gain)
20
10
.......
0
~
....
0
~0000000
~ 000000000
~ ~)000000
200000O000
2500000000
3000000000
Frequency
Figure4-4 Noise-Figuremeasurement
results
in Figure4-3(a) S~: in Figure4-3(b), $21 in Figure 4-3(c) and $22 in Figure 4-3(d). Frommarkersin
$21
plot, it can be seen that 3 dBgain bandwidthis 2.64GHz.
4.2.2 Noise Figure
The NF was measured using an Agilent E4440APerformance Spectrum Analyzer (PSA) and
external Agilent 346Bnoise source. ThePSAhas a built-in Noise-Figurepersonality whichdisplays both
gain andNF.As with the S-parametermeasurement,
the test fixture cables and probeswerecalibrated first.
However,since the PSAis a scalar measurementdevice, only the loss amplitude can be removedduring
calibration. This is comparedto vector calibration (available only in the NA)whichtakes both gain and
phaseinto account.This results in the ripples seen in the measuredgain as shownin Figure 4-4. Thepolynomialapproximationof the measuredgain has a maximum
close to 17 dB, whichis in agreementwith $21
results obtained fromthe NA.In the figure the bottom-mostsolid plot is of NFwhichhas been recorded
26
ICP Moa~Jremont
Figure4-5 Compressionpoint plot.
upto 2.7 GHz(beyond the -3 dB BW),and is shown against the -3 dB NFdotted line to indicate that the
measured LNANFis below 3 dB over the entire operating BW.
4.2.3 1 dB Input CompressionPoint (ICP)
ICP is a measureof linearity of the device and is defined as the input powerthat causes a 1 dB drop
in the linear gain due to device saturation. The ICP was measuredusing the PSAwith a 1.5 GHztest signal
from an Agilent E8251 performance signal generator (PSG).
The input compressionpoint plot is shownin Figure 4-5. The curve in the solid line is the measured
gain compressioncharacteristic of the amplifier. The dotted line, whichis parallel to the characteristic at
low input power, is 1 dB below it at low input powerlevels. The crossover point, defined as the 1 dB input
compression point, is -16.5 dBm.
This plot also shows that when the input power is -37 dBm,the output poweris -20 dBm,implying
a gain of 17 dB. This input poweris low enoughto assumesmall signal nature of the circuit. Therefore, ICP
27
Input Power
I * Firstorcler
---4~-Third
Order
- - - Linear
(First
order
) - - - Linear~Third
Order)l
Figure4-6 IIP3 Plot
measurementgives a small signal gain as 17 dB, which is in agreement with the S-Parameter and NFmeasurements.
4.2.4 Input-Referred Third Order Modulation Point (IIP3)
Whena RF circuit is driven with a high-power RF signal, non-linearity causes inter-modulation of
signals at different frequencies generating undesirable spurious signals. IIP3 is a very useful parameter to
predict low-level intermodulation effects. It is measuredby applying two input tones and is defined as the
point at which the powerin the third-order product and the fundamental tone intersect, when the amplifier
is assumedto be linear.
The lIP3 on the LNAwas measured using the PSA. Agilent E8251 and E8241 PSGs were used to
generate the two input tones at 1.5 GHzand 1.51 GHz.The IIP3 plot is shownin Figure 4-6. The solid section of the plots connects measuredpoints and the dotted section is the linear extrapolation. The top line plot
is of the output powerat the fundamentalfrequency and bottomline plot is of the output powerin the third-
28
order intermodulation product vs. powerat input frequency. The equation of the first order extrapolated line
is y = 0.9927x + 16.912 and of the third order extrapolated line is y = 2.8213x + 19.003. Solving for the
crossover point between these lines leads to the lIP3, which occurred at an input power of-1.14 dBm.Ideally slope of the first order line should be 1, because output powerin the fundamentaltone should increases
by the same amountas at the input. The measuredslope is 0.9927. Gain is given by y-intercept of the line,
which is 16.91 dB and is in agreement with all previous measurements.Since powerin the third-order modulation product increases by three times the amountof increase in the input power, ideally the slope of the
extrapolated line for the third-order intermodulation should have slope of 3. The measuredslope of 2.83, is
very close.
4.3 Second Generation Design Result Summary
The simulation performance of the extracted
layout and the measured LNAare summarized in
Table 4.2. It can be seen that the measurementresults match the extracted simulation results
Table 4.2: Comparisonof Extraction and MeasurementResults of SecondGeneration LNA
Specifications
Extraction
Measurement
$21 [dB]
18
17
$11 [dB]
-8
< -8.9
S12 [dB]
-23.5
< -25.3
$22 [dB]
-6.7
< -6
BW[GHz]
2.75
2.6
NF
l [dB
2.7
3
ICP [dBrn]
-14.63
-16.5
IIP3 [dBm]
-3.2
-1.1
Power [mW]
29
32.5
FOM
0.63
0.46
Figure 4-7 compares the measured FOMfor the second generation LNAwith that of other wideband LNApapers in the literature.
The FOMdata is plotted against the feature size of the process in which
29
2.5
~
2
Custom
SiGe
1.5
Advanced
Technologies
This work
0.5
[17]
~[6]
0
4~161
!
0
0.2
0.4
0.6
0.8
1
Featuresize [micron]
Figure4-7 Wide-bandLNAFigure of Merit vs. Lithographic feature size
they are fabricated (due to lack offr data). The higher the figure of merit, the better the design. The marker
shape indicates the type of process (square for custom SiGe bipolar technologies without CMOS
integration,
triangle
for foundry SiGe BiCMOS
technologies and diamond for foundry CMOS
technologies).
Our fab-
ricated LNAhas a higher FOMthan all the designs other than those from more advanced foundry technologies or from the custom bipolar processes. Moreover, this 0.35 ~tm BiCMOS
LNAis at least equal in
performance to all the 0.13 and 0.18 ktm CMOS
LNAs.This shows the benefit of combininga scalable noise
cancelling topology with SiGe BiCMOS
technologies.
4.4 Third Generation Design
Eventhough the first generation synthesis madeuse of the NeoCircuit, it did so in a very restricted
way. Since it used an analysis equation that related the device sizes in the schematic for first stage noise
cancellation, NeoCircuit couldn’t bias and size the schematic freely. Moreover,there was no constraint on
the power. So, while the manually modified second generation circuit
met the gain, BWand NFrequire-
ments, and showedthe potential for the noise-cancellation topology, it is not an appropriate design for multiband radios described in Chapter 1. For example,like the first generation design, it has no powerconstraint.
30
Therefore, the noise cancellation in the second generation design wasaccomplishedprimarily by burning
power.Oneapproachto preventingfree use of powerwouldhavebeen to add a constraint on the power,or
a minimizationobjective to the powerspecification. However,this had not beendonein the first generation
design.
In the third generationdesign, circuit powerconsumption
is capturedin the FOM
expression,which
is optimized.Byusingan aggregateof several circuit specifications for the optimizationobjective, the synthesis can trade off betweenthe objectives, ensureingthat the constraints are met, andpoweris minimized.
To understandthe difference betweenthe secondand third generation designs, weneedto consider
the relationship betweencircuit powerand noise cancellation. Theimpedance
lookinginto the emitter of the
transistor
Q3
determinesthe output impedance,as output impedancesof 02 and P2
are
very large and thus,
can be ignored. This impedance
(at the emitter of Q.~ ) dependson its transconductance
g,,3. Therefore,g,,3
is set by the outputmatchcondition.This sets the gain of the EFamplifier("Path 2" in Figure1-1) (equation
(4.3)). The gain of "Path 1" is the gain through Q2 divided by the attenuation through RF (which is
(1 + RF/Rs)). Toincrease this gain to that of the "Path 2", either gain throughO., shouldbe increased or
attenuation throughRE shouldbe decreased. Toreduce the attenuation, RF will haveto be reduced, thereby
reducingthe gain of the first stage (equation (2.1)). Since the overall LNA
gain comesprimarily from
first stage, this cannotbe done.Theother alternative, increasinggain throughQ2(given by equation(4.1)),
requires a lot of current. This increasein current increases the noise generatedby the CEstage, whicheventually becomesmoreimportantthan the reduction in the noise dueto noise cancellation [7]. Therefore,complete first stage noise cancellationconditionrequires a lot of poweranddoesn’tnecessarilylead to the best
overall NF.This condition wasremovedfor the third generationdesign.
Theoverall required gain is sharedby the first CEstage (with resistive feedback)and the second
CEstage (Q2). Thegain of the first CEstage is -gin I " R F (from eq
uation (2.1)) and that of thr
is given by equation(4.1). Since RE ~ 50~, investing current into Q1rather than Q2 in order to improve
gmzinstead of gin2 will lead to the mostpowerefficient wayto achievegain. Onthe other hand, the gain
31
F’xpressions
37,@
36,~
34,~)
33.e
..........................................................
1~)0u
280u
460u
640u
821~u
1,l~rn
I
Figure 4-8 gm/Ic vs. I c for HBT
through Q2 needs to be close enough to the gain through the emitter follower to achieve some amount of
noise cancellation.
Figure 4-8 shows the simulation plot of the transconductance ofa HBTper unit biasing current vs.
different values of the biasing currents. Ideally it should be a constant as grn = Ic/I"T" But, due to second
order effects we get more gm per unit biasing current whenHBTis biased at lower current. Thus, one would
like to bias transistors at lower current and use moretransistors in parallel to achieve the samenet transconductance. However,this increases device parasitics at the input which will affect the input matching and
thus, $21, as less of the input signal will get transmitted into the circuit to be amplified.
For optimumpower efficiency to get the desired gain and NF, the circuit has to be designed in
accordance with the trade-offs discussed in the previous three paragraphs. NeoCircuit was used to locate
this optimum.Unlike the first generation design, more device parameters were madevariables to give NeoCircuit more freedomwhile sizing and biasing the circuit. In the next section NeoCircuit synthesis results
are presented for the third generation LNA.In the section following the next we will analyze the synthesis
results to validate our trade-off hypothesis presented.
32
Figure4-9 NeoCircuitgoals windowwith equal weights on all goals
4.4.1 NeoCircuit Synthesis Results
The synthesis strategy presented in Chapter 3 was used for the third generation design. A target gain
BWof 3 GHzwas used during synthesis. This allows for enough over design to compensate for BWreduction due to interconnect parasitics whichare not considered during the circuit simulation used for synthesis.
Following synthesis an extraction-based simulation will be used to ensure that the BWis greater than
2.5 GHz.The supply voltage used was 2.5 volts. The variables and simulation environment were initialized
as outlined in Chapter 3. The goals, shownin Figure 4-9, were set with target values in accordance with the
LNAspecifications
(Section 1.4). The FOM(Section 1.5) was marked as a parameter to be maximized
the target value being the second generation measured LNAFOM.
As described in the synthesis strategy (Chapter 3), the first NeoCircuit run used a weight of 1 on all
the goals as shownin Figure 4-9. Wewill refer to this as the third generation (Initial).
The synthesis results
are shownin Figure 4-10 (a). The columnlabelled "Current" shows the values for the corresponding goals
achieved. Comparingthe values in this columnwith those in the "Target" column, indicates that the targets
are reasonable for this topology and process. "NFhigh"(which is NFvalue at higher frequency) is narrowly
missed, and the remaining goals are all met.
So, in the secondrun the weights on someof the goals are altered, as shownin Figure 4-11. A higher
weight is used for "NFhigh". Since BW,"NFlow" and FOMare critical
goals, their weights are also
33
Results
Results
Goals
Goals
i current
<
~11low <
~-’111high<
18r~
-11
-11
cun, e~t <
S1110W <
~llhigh I <
SIZIow <
S2Zhigh <
- 11
SIZIow <
SZ21~gh
$21 low
>
G.,5678m
’
-11
-17.3648
-11
17
SZ1 ~ >
NFIow <
<
Nl~gh
FOM ’m~,~
NFIow
NFhigl~
FOM
Z.8
L6
400~
(a)
-16.1770
-18.9647
17.00:33
Z.5153
2.4528
2.7843
931;.530Gm
Figure 4-10 NeoCircuit Synthesis results for the (a) first NeoCircuit run with equal weights (3rd generation (Initial)
design) and (b) second run with modified weights (3rd generation (Final) design).
increased.
Also, the target
value of altered
FOMwas also changed to the FOMachieved in the first
NeoCir-
cuit synthesis run. The second synthesis run results are shown in Figure 4-10(b). Wewill refer to this design
as the third generation
(Final).
This time all the goals were met and the FOMachieved is about is -2.5x
better than the second generation design.
4.4.2 Analysis of the 3rd Generation Synthesized LNAs
If incomplete cancellation
of the noise from the first
claimed above, then there should be two differences
generation one. First,
stage improves the overall
in the third generation circuits
circuit
NF, as
compared to the second
there should be a difference in the gains between the two noise cancellation paths, sec-
sP aramRf(3eg,EO(SP,SP_S17))
~BW ~ sParamRZleg,EO(SP,SP_321))sParamRf(3eg,EO(SP,SP_SZ1))
~fioise~igSparamRf(1
...........................................................................................
eg,EO(SP,SPNOISE_SP_NF))
: lessthan-Z5
Z
!lessthan3
j~e~-~-fi
~5~~-~.
...........
~~....
..........................
~- - ~ ................................................
:_.:.._i
...................
:__~
........
~
~sParamRf(leg,EO(SP,SP
SZl)y(no=seF~gSparam~(3e9,EO(SP,SPNOISE
SP NF))’magnmtulm~mm~ze’0.7
Figure 4-11 NeoCircuit goals windowwith weights on somegoals changed
34
~MinirnumNF
SecondGeneration
I~1N°rrealized
er r°r in t heNFcance~lat
i°n Path
331irdGenerat
ion( Int ial)
ThirdGenerat
ion (Final)
Figure 4-12 Comparingminimum
NFand normalizederror in first stage noise cancellation across three the designs
ond, the third generation designs should have should have better NF. Figure 4-12 compares magnitude of
the difference in the gain between "Path 1" and "Path 2" (normalized to that for the second generation
design) and the minimumNFacross the three designs. It can be seen that the minimumNFhas improved,
even though the error in the noise cancellation path has increased for the third generation designs. The error
in the noise cancellation paths increased between the third generation (Initial)
designs while the NFdecreased. Also, going from the third generation (Initial)
and the second generation
to the third generation (Final)
designs, both the error in gain matching between the noise cancellation paths and the NFdecreased. This
meansthat there is an optimal error in the noise cancellation for best minimumoverall NF.
Gains provided by the first CEstage (with resistive feedback) and the second CEstage (Q~,) for
three designs are normalized to the value for the second generation and comparedin Figure 4-13. NeoCircuit synthesized circuits,
comparedto hand-designed second generation have more gain for the first CE
stage and less gain through Q2- Gains for the third generation (Final) are slightly less than the gains for the
third generation (Initial),
as the overall gain was reduced by the NeoCircuit to just meet the target value.
35
l
mNorrnatlzed
gaint hrough
Q1IR Norm~llized
gaint hroug~l
Q2
2~47
0
Second
Gener
at ion
ThirdGener
at ion(Int ial)
ThirdGenerat
ion(Final)
Figure4-13 Comparison
of gain fromtransistor QI andQ2across the three designs.
Also, the normalizedtotal gmof transistors Q1and Q2 are comparedin Figure 4-14. Since gain is directly
proportionalto gin, this plot confirmsthe gain distribution hypothesis.
NeoCircuitbiased the HBTsfor the third generation designs at lower currents as comparedto the
second generation hand design thus improvingthe gin~1C. This is shownin Figure 4-15 which plots the
normalizedcollector current 1C and gm/1Cfor the transistor Q/ across the three designs.
Second
Generation
Third
Generat
ion( Inti a I)
Third Ge
nerat
ion( Fi hal)
Figure4-14 Normalized
transconductance
of transistors Q!andQ2across the three designs
36
l~
Norrnalizedlc¢~Normalizecl(gm/Ic)
0.8
0.6
0.4
0.2
SecondGeneration
"~lirdC~neration(Intial)
~irdGeneration(Final)
Figure4-15 Normalized
collector current I C and (gm/]C)for transistor QI across the three designs.
Thus, analysis of the synthesized results shows that NeoCircuit synthesizes improved the LNA
design by optimizing in the directions suggested at the beginning of this section.
4.4.3 Simulation for Extracted Circuits
As the third generation design has not yet been fabricated, the extraction simulation results are
shown in Table 4.3 to allow comparison with the second generation extracted and measured datasheet
Table4.3: Extraction Results
Specifications
Third Generation
S2! [dB]
17.21
Si1 [dB]
-11.2
SI2 [dB]
-27.21
$22 [dB]
-
BW[GHz]
2.88
NF[dB]
2.85
ICP [dBm]
- 18.4
IIP3 [dBm]
-7.4
Power [mW]
16.55
2]
Area [lam
118x78
FOM
1.05
14
37
shownin Table 4.2. The extracted circuit includes interconnect parasitics. This together with the quality of
the device modelsavailable in the Jazz design kit lends credibility to the potential for achieving these targets
whenthe design is fabricated. If we derate the FOMobtained from extracted circuit simulation by the ratio
of the measuredto extracted FOMin Table 4.2, the resulting FOMwill still
be higher than all the advanced
CMOSLNAs shown in Figure 4-7.
38
Conclusion and Future Work
AnLNA
design for application in multi-bandwireless transceivers has been presented. Thedesire
for monolithic integration of the RFfront end with CMOS
basebandprocessing led to the choice of the
wide-band LNA(comparedto multiple parallel narrow-band LNAs),and SiGe BiCMOS
technology (over
CMOS).
Selected specifications and RFissues, such as impedancematchingand low NFover wide band of
frequency,droveto the choiceof wide-bandnoise cancellation topology[7].
Three generations of the selected topology have been designedin the Jazz 0.35 ~tm BiCMOS
process. Thefirst two generationsof these havebeenfabricated andcharacterized. Athird generationdesign
wasautomaticallysynthesized, and its physical design completed.
The best fabricated LNAhas measuredgain of 17 dB and a bandwidthof 2.6 GHz.The NFis less
than 3 dBover the LNAbandwidth, with minimum
value of 2.4 dB. It draws 13mAcurrent from a 2.5 V
supply. Simulation, following layout extraction, of the third generation LNAsuggests that a gain of
17.21 dB and bandwidthas 2.9 GHzis achievable. The worst NFover this band is 2.85 dB. These were
obtained by burning 6.62 mAcurrent from a 2.5 V supply. This design shows a FOM
improvementof-2x
comparedto the extracted simulation results of the secondgeneration design, showingthe effectiveness of
NeoCircuit.Furthermore,if wederate the extracted simulationresults of this designby whatwassee for the
second generation, we anticipate being able to measurea circuit whichoutperformsall the CMOS
widebandLNAs
in the literature.
Future workincludes fabrication and testing of this LNAand comparingit with previous generations. Additionally, narrow-bandLNAtopologies that havetunable matchingnetworkswill be explored for
use in multi-bandradio front ends.
39
References
[1]D. K. Shaeffer and T. H. Lee, "A 1.5-V, 1.5-GHz CMOS
low noise amplifier,"
IEEE JSSC, SC-32(5),
May 1997, p. 745.
[2]R. Magoonet. al., "A single-chip
quad-band (850/900/1800/1900 MHz)direct conversion G SM/GPRS
RF transceiver with integrated VCOsand fractional-n
synthesizer," IEEE JSSC, SC(37) 12, Dec. 2002, pp.
1710 - 1720.
[3]Adiseno, M. Ismail and Hakan Olsson, "A Wide-Band RF Front-End for Multiband Multistandard
High-Linearity Low-IF Wireless Receivers," IEEEJSSC,SC(37)9, Sept. 2002, pp. 1162-1168.
[4]C.-S. Wang, W.-C. Li and C.-K. Wang, "A Multi-band Multi-standard RF Front-end for IEEE 802.16a
and IEEE 802.11 a/b/g application," ISCAS 2005.
[5]D. Ramachandran, A. Oz, V. K. Saraf, ~ K. Fedder and T. Mukherjee, "MEMS-EnabledReconfigurable VCOand RF Filter,"
Proc. IEEE RFICSymp., June 6-8, 2004, p. 251.
[6lB. M. Ballweber, R. Gupta, and D. J. Allstot,
"A Fully Integrated
0.5-5.5-GHz CMOS
Distributed
Amplifier," IEEE JSSC, SC-35(2), February 2000, pp. 231-239.
[7IF. Bruccoleri, E. A. M. Klumperink, and B. Nauta, "Wide-band CMOS
low-noise amplifier exploiting
thermal noise canceling," 1EEEJSSC,SC-39(2), Feb. 2004, pp. 275-282.
[8]D. L. Harame, et. al. "Current status and future trends of SiGe BiCMOS
technology," 1EEETransactions on Electron Devices, vol. 48, no. 11, Nov. 2001, pp. 2575-2594.
[9]K. W. Kobayashi, A. K. Oki, L.T. Tran, and D. C. Streit,
"Ultra-low dc power GaAsHBTS- and C-band
low noise amplifiers for portable wireless applications," 1EEEM77~,vol. 43, no. 12, Dec. 1995, pp. 30553061.
[10]M. Sperling,
"SiGe BiCMOSRF Circuit Design: A Wideband LNAExample," Masters Thesis, Carn-
egie Mellon University, August 2003.
[ 11 ]B. Razavi, RFMicroelectronics, Prentice Hall, pp 20.
[12]S. Narayanan, H. Poon, "An analysis of distortion in bipolar transistors using integral charge control
model and Volterra series," IEEE Transactions on Circuits and Systems, vol. 20, no. 4, Jul. 1973, pp. 341351.
[13]R R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, John Wiley & Sons,
third edition, pp.211.
[14]H. Knapp, et. aL, "15 GHzWidebandAmplifier with 2.8 413 Noise Figure in SiGe Bipolar Technology," RFIC 2001, pp. 287-290.
40
[15]H. Schumacher, et. al.,
"A 3 V supply voltage,
DC-18 GHzSiGe HBTwideband amplifier,"
BCTM,
1995, pp. 190-193
[16]J. Janssens,
M. Steyaert and H. Miyakawa, "A 2.7 Volts CMOS
Broadband Low Noise Amplifier,"
1997 Symposiumon VLSI Circuits,
pp. 87-88.
[17] P. I. Sullivan, B. A. Xavier and W. H. Ku, "An integrated CMOS
distributed amplifier using packaging inductance," ~ vol. 45, no. 10, Oct. 1997, pp. 1969-1975.
[18]H. Ahn. and D. J. Allstot, "A 0.5-8.5-GHz fully differential
CMOS
distributed amplifier," IEEEJSSC,
SC(37)8, Aug. 2002, pp. 985-993.
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41
Appendix: Significance of 3 dB Noise Figure
Input and output SNRis denotedby:
SNRi,
- Ni
n
Sin
Sour
SNRout - Nout
(1.1)
whereS denotes signal powerand N denotes noise power. If gain of amplifier is denoted by G
and noise addedby it as Nadde
d then:
Sout = G. Sin
(A.2)
Nout = G. Nin d+ Nadde
(A.3)
G. Si,
SNR°ut = G. Ni, + N,,aaed
(A.4)
f SNRin’~
NF = 10. log,0(.S--~o~
(A.5)
NFis definedas:
For given expressions of SNRinand SNRou
t it becomes:
NF= 10. lOglo((G.
Si,,/ Ni,,
Sin)/-~:~+
~
Nadded
(1.6)
+ Nadde~
10.1og~0 (G" Ni.j_n
G" Nin
For NFof 3 dB:
3 = 10" log, o(G’Ni-’n’+=Naddea)
}
G ¯ Nin
(A.7)
which, on simplification gives:
Nadded = G" Ni,
(A.8)
Thus, for NFof 3 dB, the noise poweradded by the system is same as the noise at the input
amplifiedby the amplifier gain.
42