Laboratory Experiment #7: Memory Modeling Ari Mahpour ECE 526 Lab Student ID #: 101146706 Table of Contents Purpose ....................................................................................... 3 Test Strategy ............................................................................... 4 Results ........................................................................................ 5 Conclusion .................................................................................. 5 Waveform Diagram .................................................................... 6 Purpose The purpose of this lab was to implement and observe the behavior of a memory module, more specifically, a RAM (Random Access Memory) module. The RAM module had a few inputs and one output that functioned both as an input and output. The first input was an address line consisting of 5 bits. This would specify where on the memory block the information was either to read from or written to. The other three inputs consisted of a single binary digit, them being a read, write, and enable function. All these input were being written to a 32 by 8 memory block which was instantiated within the module itself. All information was being taken in and out of this memory block. The last output/input was of data type “inout.” It was nor a type “reg” or “input.” It would read data in and also output data but it had to either be implemented using an assign statement or tri‐state buffer. The whole purpose behind doing this was to ensure that high impedance was set in certain situations. When writing in data into the memory module, we had to ensure that the input side of the inout wire was set to high impedance. Likewise, when writing data, the output side has to be set to high impedance. If both where trying to pass values the circuit would essentially “blow up” which is something we don’t want to experience. Though the simulation output could be unpredictable (but possibly work), this lab focuses on synthesis rather than just simulation, therefore, this circuit has to be completely prepared to be used as hardware. Test Strategy The test vectors in this laboratory experiment were specifically stated within the laboratory manual itself, therefore, they were quite straightforward. There were two series of tests that had to be performed, each in a separate test module. The first part of the first test bench module was to write and read from every memory location. Afterwards we were instructed to demonstrate an individual and block read, demonstrate the specified timings for read and write, test both enabled and disabled memory states, show that the databus was in the high impedance state when necessary, show that there were 32 locations in the memory, and show that there were no shorts or stuck‐at conditions. The second test bench was to implement the function “$readmemh.” This was to read a text file that consisted of memory addresses and values. We were to demonstrate that the memory had been successfully initialized and that the unspecified locations had stayed as undefined. Afterwards, we were to scramble the memory data write it to the memory block and then read it from the memory block to ensure that it was properly scrambled. The memory text file has been attached to the report for proper analysis of this report. Results For the first test bench, all the test vectors were accomplished simply by toggling enable on and off in two different loops that would traverse through the memory block (i.e. 32 times ‐ going through each address). All values had been written correctly with no issues and then read properly, once again with no issues. The output log file documents each state when a value has been registered into and pulled from the memory block. The output waveform file does the same but is a bit easier to observe. For the second test bench all memory allocations had to be done using the “$readmemh” function and a memory text file. All the address and data were properly written and read with an output log file to document its procedure and process. The memory bytes had been properly scrambled, written, and reread proving to be a success. All documentation, including printouts, has been included in this laboratory report. Conclusion In the laboratory experiment we explored many different functions that we had learned in the corresponding lecture course. All of these were very important to not only learn but to be put into practice. Functions such as “$readmemh” and creating tri‐state buffers were just a couple of ideas that had to be put into practice. When running simulation, it is important to have in mind that this will eventually become a circuit and not a bunch of test vectors on the screen. With that, we must understand the importance of components such as tri‐state buffers. Though the simulation might run without them, we know that a circuit such as this lacking tri‐
state buffers will break. Synthesizing a circuit doesn’t necessary mean creation of a circuit based off some code, rather it is a fusion of theory and practicality, all built into one circuit.
Page 1 of 4
Test Bench A
Ari Mahpour
Baseline = 0
Cursor = 830ns
Baseline = 0
Cursor-Baseline = 830ns
0
data_out[7:0]
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xx
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Printed on Mon Nov 09 06:01:22 PM PST 2009
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Printed by SimVision from Cadence Design Systems, Inc.
Page 2 of 4
Test Bench A
Ari Mahpour
Cursor = 830ns
Baseline = 0
Cursor-Baseline = 830ns
0ns
data_out[7:0]
'h00
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'h20
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i
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read
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Printed on Mon Nov 09 06:01:22 PM PST 2009
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Printed by SimVision from Cadence Design Systems, Inc.
Page 3 of 4
Test Bench A
Ari Mahpour
Cursor = 830ns
Baseline = 0
Cursor-Baseline = 830ns
420ns
data_out[7:0]
'h00
zz
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'h20
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Printed on Mon Nov 09 06:01:22 PM PST 2009
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Printed by SimVision from Cadence Design Systems, Inc.
Page 4 of 4
Test Bench A
Ari Mahpour
Cursor = 830ns
Baseline = 0
Cursor-Baseline = 830ns
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TimeA = 830ns
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Printed on Mon Nov 09 06:01:22 PM PST 2009
12
Printed by SimVision from Cadence Design Systems, Inc.
ncverilog: 08.20-s012: (c) Copyright 1995-2009 Cadence Design Systems,
Inc.
TOOL: ncverilog
08.20-s012: Started on Oct 31, 2009 at 20:33:21 PDT
ncverilog
tb_mem.v
MEM.v
-l
tb_MEM.log
Loading snapshot worklib.tb_mem:v .................... Done
ncsim> source /opt/cadence/IUS0820/tools/inca/files/ncsimrc
ncsim> run
0 Address=xx data_in=xx data_out=xx Data=xx read=x write=x
5 Address=xx data_in=xx data_out=xx Data=xx read=x write=0
10 Address=xx data_in=xx data_out=zz Data=xx read=0 write=1
15 Address=00 data_in=00 data_out=zz Data=00 read=0 write=1
20 Address=00 data_in=00 data_out=zz Data=zz read=0 write=0
25 Address=00 data_in=00 data_out=zz Data=00 read=0 write=1
30 Address=01 data_in=01 data_out=zz Data=01 read=0 write=1
35 Address=01 data_in=01 data_out=zz Data=zz read=0 write=0
40 Address=01 data_in=01 data_out=zz Data=01 read=0 write=1
45 Address=02 data_in=02 data_out=zz Data=02 read=0 write=1
50 Address=02 data_in=02 data_out=zz Data=zz read=0 write=0
55 Address=02 data_in=02 data_out=zz Data=02 read=0 write=1
60 Address=03 data_in=03 data_out=zz Data=03 read=0 write=1
65 Address=03 data_in=03 data_out=zz Data=zz read=0 write=0
70 Address=03 data_in=03 data_out=zz Data=03 read=0 write=1
75 Address=04 data_in=04 data_out=zz Data=04 read=0 write=1
80 Address=04 data_in=04 data_out=zz Data=zz read=0 write=0
85 Address=04 data_in=04 data_out=zz Data=04 read=0 write=1
90 Address=05 data_in=05 data_out=zz Data=05 read=0 write=1
95 Address=05 data_in=05 data_out=zz Data=zz read=0 write=0
100 Address=05 data_in=05 data_out=zz Data=05 read=0 write=1
105 Address=06 data_in=06 data_out=zz Data=06 read=0 write=1
110 Address=06 data_in=06 data_out=zz Data=zz read=0 write=0
115 Address=06 data_in=06 data_out=zz Data=06 read=0 write=1
120 Address=07 data_in=07 data_out=zz Data=07 read=0 write=1
125 Address=07 data_in=07 data_out=zz Data=zz read=0 write=0
130 Address=07 data_in=07 data_out=zz Data=07 read=0 write=1
135 Address=08 data_in=08 data_out=zz Data=08 read=0 write=1
140 Address=08 data_in=08 data_out=zz Data=zz read=0 write=0
145 Address=08 data_in=08 data_out=zz Data=08 read=0 write=1
150 Address=09 data_in=09 data_out=zz Data=09 read=0 write=1
155 Address=09 data_in=09 data_out=zz Data=zz read=0 write=0
160 Address=09 data_in=09 data_out=zz Data=09 read=0 write=1
165 Address=0a data_in=0a data_out=zz Data=0a read=0 write=1
170 Address=0a data_in=0a data_out=zz Data=zz read=0 write=0
175 Address=0a data_in=0a data_out=zz Data=0a read=0 write=1
180 Address=0b data_in=0b data_out=zz Data=0b read=0 write=1
185 Address=0b data_in=0b data_out=zz Data=zz read=0 write=0
190 Address=0b data_in=0b data_out=zz Data=0b read=0 write=1
195 Address=0c data_in=0c data_out=zz Data=0c read=0 write=1
200 Address=0c data_in=0c data_out=zz Data=zz read=0 write=0
205 Address=0c data_in=0c data_out=zz Data=0c read=0 write=1
210 Address=0d data_in=0d data_out=zz Data=0d read=0 write=1
215 Address=0d data_in=0d data_out=zz Data=zz read=0 write=0
220 Address=0d data_in=0d data_out=zz Data=0d read=0 write=1
225 Address=0e data_in=0e data_out=zz Data=0e read=0 write=1
230 Address=0e data_in=0e data_out=zz Data=zz read=0 write=0
235 Address=0e data_in=0e data_out=zz Data=0e read=0 write=1
240 Address=0f data_in=0f data_out=zz Data=0f read=0 write=1
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Address=0f
Address=0f
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Address=10
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Address=1a
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Address=1b
Address=1b
Address=1b
Address=1c
Address=1c
Address=1c
Address=1d
Address=1d
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Address=1e
Address=1e
Address=1e
Address=1f
Address=1f
Address=1f
Address=00
Address=00
Address=01
Address=02
Address=03
Address=04
Address=05
Address=06
Address=07
Address=08
data_in=0f
data_in=0f
data_in=10
data_in=10
data_in=10
data_in=11
data_in=11
data_in=11
data_in=12
data_in=12
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data_in=14
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data_in=19
data_in=1a
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data_in=1b
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data_in=1c
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data_in=1d
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data_in=1e
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data_in=1e
data_in=1f
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data_in=20
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data_in=20
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data_in=20
data_in=20
data_in=20
data_in=20
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data_out=zz
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Data=zz
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Data=20
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read=0
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read=1
read=1
read=1
read=1
read=1
read=1
read=1
read=1
read=1
write=0
write=1
write=1
write=0
write=1
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write=1
write=1
write=0
write=1
write=1
write=0
write=1
write=1
write=0
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write=1
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write=1
write=1
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write=1
write=1
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write=1
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write=1
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write=1
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write=1
write=1
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write=1
write=1
write=0
write=1
write=1
write=0
write=0
write=0
write=0
write=0
write=0
write=0
write=0
write=0
600 Address=09 data_in=20 data_out=09 Data=09 read=1 write=0
610 Address=0a data_in=20 data_out=0a Data=0a read=1 write=0
620 Address=0b data_in=20 data_out=0b Data=0b read=1 write=0
630 Address=0c data_in=20 data_out=0c Data=0c read=1 write=0
640 Address=0d data_in=20 data_out=0d Data=0d read=1 write=0
650 Address=0e data_in=20 data_out=0e Data=0e read=1 write=0
660 Address=0f data_in=20 data_out=0f Data=0f read=1 write=0
670 Address=10 data_in=20 data_out=10 Data=10 read=1 write=0
680 Address=11 data_in=20 data_out=11 Data=11 read=1 write=0
690 Address=12 data_in=20 data_out=12 Data=12 read=1 write=0
700 Address=13 data_in=20 data_out=13 Data=13 read=1 write=0
710 Address=14 data_in=20 data_out=14 Data=14 read=1 write=0
720 Address=15 data_in=20 data_out=15 Data=15 read=1 write=0
730 Address=16 data_in=20 data_out=16 Data=16 read=1 write=0
740 Address=17 data_in=20 data_out=17 Data=17 read=1 write=0
750 Address=18 data_in=20 data_out=18 Data=18 read=1 write=0
760 Address=19 data_in=20 data_out=19 Data=19 read=1 write=0
770 Address=1a data_in=20 data_out=1a Data=1a read=1 write=0
780 Address=1b data_in=20 data_out=1b Data=1b read=1 write=0
790 Address=1c data_in=20 data_out=1c Data=1c read=1 write=0
800 Address=1d data_in=20 data_out=1d Data=1d read=1 write=0
810 Address=1e data_in=20 data_out=1e Data=1e read=1 write=0
820 Address=1f data_in=20 data_out=1f Data=1f read=1 write=0
830 Address=00 data_in=20 data_out=00 Data=00 read=1 write=0
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit
TOOL: ncverilog
08.20-s012: Exiting on Oct 31, 2009 at 20:33:21 PDT
(total: 00:00:00)
Page 1 of 4
Test Bench B
Ari Mahpour
Baseline = 0
Cursor = 707ns
Baseline = 0
Cursor-Baseline = 707ns
0
10ns
20ns
30ns
40ns
50ns
60ns
70ns
80ns
90ns
00
01
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58
ED
B7
34
C9
8F
A0
58
ED
B7
34
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8F
A0
5
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9
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11
Address[4:0]
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xx
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xx
data_out[7:0]
No Value A
xx
ena
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cnt
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32
i
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0
j
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8
k
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3
read
No Value A
t[0:7]
[8 bits]
[8 bits]
temp[7:0]
No Value A
xx
write
No Value A
Printed on Mon Nov 09 05:40:37 PM PST 2009
1
2
3
4
100ns
Printed by SimVision from Cadence Design Systems, Inc.
Page 2 of 4
Test Bench B
Ari Mahpour
Cursor = 707ns
Baseline = 0
Cursor-Baseline = 707ns
110ns
120ns
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140ns
150ns
160ns
170ns
180ns
190ns
200ns
210ns
2
Address[4:0]
No Value A
0A
0B
0C
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0E
0F
10
11
12
13
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15
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No Value A
A0
9B
65
11
03
4C
DA
7E
F2
26
86
95
data_in[7:0]
No Value A
xx
data_out[7:0]
No Value A
A0
9B
65
11
03
4C
DA
7E
F2
26
86
95
ena
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cnt
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i
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11
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13
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j
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8
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3
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No Value A
t[0:7]
[8 bits]
[8 bits]
temp[7:0]
No Value A
xx
write
No Value A
Printed on Mon Nov 09 05:40:37 PM PST 2009
Printed by SimVision from Cadence Design Systems, Inc.
Page 3 of 4
Test Bench B
Ari Mahpour
Cursor = 707ns
Baseline = 0
Cursor-Baseline = 707ns
0ns
230ns
240ns
250ns
300ns
310ns
320ns
15
16
17
1C
1D
1E
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95
FD
B1
xx
12
AF
33
xx
data_in[7:0]
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xx
data_out[7:0]
No Value A
95
FD
B1
xx
12
AF
33
xx
ena
No Value A
cnt
No Value A
32
i
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22
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29
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31
j
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8
k
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3
read
No Value A
t[0:7]
[8 bits]
[8 bits]
temp[7:0]
No Value A
xx
write
No Value A
27
1B
290ns
No Value A
26
1A
280ns
Data[7:0]
25
19
270ns
Address[4:0]
Printed on Mon Nov 09 05:40:37 PM PST 2009
18
260ns
28
1F
32
330
00
18
Printed by SimVision from Cadence Design Systems, Inc.
Page 4 of 4
Test Bench B
Ari Mahpour
Cursor = 707ns
Baseline = 0
Cursor-Baseline = 707ns
s
340ns
Address[4:0]
No Value A
00
12
Data[7:0]
No Value A
xx
F2
data_in[7:0]
No Value A
xx
data_out[7:0]
No Value A
xx
ena
No Value A
cnt
No Value A
32
i
No Value A
18
j
No Value A
8
k
No Value A
3
read
No Value A
t[0:7]
[8 bits]
[8 bits]
temp[7:0]
No Value A
xx
write
No Value A
Printed on Mon Nov 09 05:40:37 PM PST 2009
350ns
360ns
370ns
380ns
13
CB
XX
zz
2A
26
zz
19
F2
2X
29
Xx
2X
420ns
86
zz
71
XX
Xx
440ns
17
FD
F7
71
95
zz
21
86
430ns
16
95
29
20
26
410ns
15
86
2A
XX
400ns
14
26
CB
F2
390ns
B1
FX
B1
F7
XX
FD
zz
22
95
FX
23
FD
B1
Printed by SimVision from Cadence Design Systems, Inc.
ncverilog: 08.20-s012: (c) Copyright 1995-2009 Cadence Design Systems,
Inc.
TOOL: ncverilog
08.20-s012: Started on Oct 31, 2009 at 20:33:33 PDT
ncverilog
tb2_mem.v
MEM.v
-l
tb2_MEM.log
file: tb2_mem.v
module worklib.tb2_mem:v
errors: 0, warnings: 0
file: MEM.v
Caching library 'worklib' ....... Done
Elaborating the design hierarchy:
Building instance overlay tables: .................... Done
Generating native compiled code:
worklib.tb2_mem:v <0x71d96b51>
streams:
6, words: 5475
Loading native compiled code:
.................... Done
Building instance specific data structures.
Design hierarchy summary:
Instances Unique
Modules:
2
2
Resolved nets:
0
1
Registers:
12
12
Scalar wires:
3
Vectored wires:
5
Always blocks:
1
1
Initial blocks:
1
1
Cont. assignments:
3
3
Pseudo assignments:
2
2
Simulation timescale: 1ns
Writing initial simulation snapshot: worklib.tb2_mem:v
Loading snapshot worklib.tb2_mem:v .................... Done
ncsim> source /opt/cadence/IUS0820/tools/inca/files/ncsimrc
ncsim> run
Before Initialization
memory[0] = xx memory[1] = xx memory[2] = xx memory[3] = xx
memory[4] = xx memory[5] = xx memory[6] = xx memory[7] = xx
memory[8] = xx memory[9] = xx memory[10] = xx memory[11] = xx
memory[12] = xx memory[13] = xx memory[14] = xx memory[15] = xx
memory[16] = xx memory[17] = xx memory[18] = xx memory[19] = xx
memory[20] = xx memory[21] = xx memory[22] = xx memory[23] = xx
memory[24] = xx memory[25] = xx memory[26] = xx memory[27] = xx
memory[28] = xx memory[29] = xx memory[30] = xx memory[31] = xx
After Initialzation
memory[0] = xx memory[1] =
memory[4] = 58 memory[5] =
memory[8] = c9 memory[9] =
memory[12] = 65 memory[13]
memory[16] = da memory[17]
memory[20] = 86 memory[21]
memory[24] = xx memory[25]
memory[28] = 12 memory[29]
xx memory[2] = xx memory[3] = xx
ed memory[6] = b7 memory[7] = 34
8f memory[10] = a0 memory[11] = 9b
= 11 memory[14] = 03 memory[15] = 4c
= 7e memory[18] = f2 memory[19] = 26
= 95 memory[22] = fd memory[23] = b1
= xx memory[26] = xx memory[27] = xx
= af memory[30] = 33 memory[31] = xx
After Scramble
memory[0] = xx memory[1] = xx memory[2] = xx memory[3] = xx
memory[4] = 58 memory[5] = ed memory[6] = b7 memory[7] = 34
memory[8] = c9 memory[9] = 8f memory[10] = a0 memory[11] = 9b
memory[12] = 65 memory[13] = 11 memory[14] = 03 memory[15] = 4c
memory[16] = da memory[17] = 7e memory[18] = XX memory[19] = 2X
memory[20] = Xx memory[21] = XX memory[22] = fX memory[23] = b1
memory[24] = xx memory[25] = xx memory[26] = xx memory[27] = xx
memory[28] = 12 memory[29] = af memory[30] = 33 memory[31] = xx
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit
TOOL: ncverilog
08.20-s012: Exiting on Oct 31, 2009 at 20:33:34 PDT
(total: 00:00:01)
MEM.v
/**********************************************************************************
***
***
*** ECE 526 L Experiment #7
Ari Mahpour, Fall, 2009 ***
***
***
*** Memory Modeling
***
***
***
***********************************************************************************
*** Filename: MEM.v
Created by Ari Mahpour, 10/27/2009 ***
***
***
***********************************************************************************
*** This module represents a 32 x 8 Memory Module.
***
***********************************************************************************/
`timescale 1 ns / 1 ns
module MEM(data, addr, read, write, ena_low);
inout [7:0] data;
input [4:0] addr;
input read, write, ena_low;
reg [7:0] memory [0:31];
assign data = (read && !ena_low) ? memory[addr] : 8'bz;
always@(posedge write) begin
if (!ena_low && !read)
memory[addr] <= data;
end
endmodule
Page 1
tb_mem.v
/**********************************************************************************
***
***
*** ECE 526 L Experiment #7
Ari Mahpour, Fall, 2009 ***
***
***
*** Memory Modeling
***
***
***
***********************************************************************************
*** Filename: tb_MEM.v
Created by Ari Mahpour, 10/27/2009 ***
***
***
***********************************************************************************
*** This module is the first test bench for the MEM.v module (specified in the ***
*** laboratory manual.
***
***********************************************************************************/
`timescale 1ns/1ns
module tb_mem();
reg [4:0] Address;
reg [7:0] data_in;
reg read, write, ena;
wire [7:0] Data, data_out;
integer i;
MEM UUT(Data, Address, read, write, ena);
assign Data = ((read ==0) & (write == 1)) ? data_in : 8'bZ;
assign data_out = ((read == 1) & (write ==0)) ? Data : 8'bZ;
initial begin
$monitor( " %d Address=%h data_in=%h data_out=%h Data=%h read=%b write=%b",
$time, Address, data_in, data_out, Data, read, write);
end
initial begin
for(i = 0;
#5
#5
#5
end
i < 33; i = i + 1) begin
write = 1'b0;
ena = 1'b0; write = 1'b1; read = 1'b0;
data_in = i; Address = i;
#5 ena = 1'b1;
for(i = 0; i < 33; i = i + 1) begin
#5 ena = 1'b0; write = 1'b0; read = 1'b1;
#5 Address = i;
end
end
endmodule
Page 1
tb2_mem.v
/**********************************************************************************
***
***
*** ECE 526 L Experiment #7
Ari Mahpour, Fall, 2009 ***
***
***
*** Memory Modeling
***
***
***
***********************************************************************************
*** Filename: tb2_MEM.v
Created by Ari Mahpour, 10/27/2009 ***
***
***
***********************************************************************************
*** This module is the second test bench for the MEM.v module (specified in the ***
*** laboratory manual.
***
***********************************************************************************/
`timescale 1ns/1ns
module tb2_mem();
reg [4:0] Address;
reg [7:0] data_in;
reg read, write, ena;
wire [7:0] Data, data_out;
reg [7:0] temp;
reg t [0:7];
integer i,j,k,cnt;
MEM UUT(Data, Address, read, write, ena);
assign Data = ((read ==0) & (write == 1)) ? data_in : 8'bZ;
assign data_out = ((read == 1) & (write ==0)) ? Data : 8'bZ;
task displaymem;
begin
cnt = 0;
for(j = 0; j < 8; j = j + 1) begin
$write("memory[%0d] = %h ",cnt,UUT.memory[cnt]);
cnt = cnt + 1;
for(k = 0; k < 3; k = k + 1) begin
$write("memory[%0d] = %h ",cnt,UUT.memory[cnt]);
cnt = cnt + 1;
end
$write("\n");
end
end
endtask
//initial begin
//$monitor( " %d Address=%h data_in=%h data_out=%h Data=%h read=%b write=%b",
// $time, Address, data_in, data_out, Data, read, write);
//end
initial begin
$display("Before Initialization");
displaymem;
$readmemh("mem.txt", UUT.memory); //initialize memory
$write("\n\n");
$display("After Initialzation");
displaymem;
// Demonstrates the memory has been successfully initialized and that
// the locations that are unspecified are undefined
for(i = 0; i < 33; i = i + 1) begin
#5 ena = 1'b0; write = 1'b0; read = 1'b1;
Page 1
tb2_mem.v
#5 Address = i;
end
for(i = 18; i < 24; i = i + 1) begin
#5 ena = 1'b0; write = 1'b0; read = 1'b1;
#5 Address = i;
#5 temp = data_out; t[0] = temp[7]; t[7] = temp[6];
t[1] = temp[5]; t[6] = temp[4]; t[2] = temp[3];
t[5] = temp[2]; t[3] = temp[1]; t[4] = temp[0];
#5 write = 1'b1; read = 1'b0;
data_in = {t[7], t[6], t[5], t[4], t[3], t[2], t[1], t[0]};
end
$write("\n\n");
$display("After Scramble");
displaymem;
end
endmodule
Page 2
file:///C|/Documents%20and%20Settings/Ari%20Mahpour/Desktop/lab7/mem.txt
@04
58 ED B7 34 C9 8F A0 9B 65 11 03 4C
@10
DA 7E F2 26 86 95 FD B1
@1C
12 AF 33
file:///C|/Documents%20and%20Settings/Ari%20Mahpour/Desktop/lab7/mem.txt [11/9/2009 5:53:21 PM]
I hereby attest that this lab report is entirely my own work. I have not copied either code or text from anyone, nor have I allowed or will allow anyone to copy my work. Name (printed): ______________________________________ Name (signed): ______________________________________ Date: ___________________