“Molded Underfill (MUF) Technology for Flip Chip
Packages in Mobile Applications”
By
Joshi M., Pendse R., Pandey V., Lee T.K., Yoon I.S., Yun J.S.,
Kim Y.C., Lee H.R.
STATS ChipPAC Inc.
Copyright © 2010. Reprinted from 2010 Electronic Components and
Technology Conference (ECTC) Proceedings. The material is posted here by
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Molded Underfill (MUF) Technology for Flip Chip Packages in Mobile Applications
Joshi M., Pendse R., Pandey V., Lee T.K., Yoon I.S., Yun J.S., Kim Y.C., Lee H.R.,
STATS ChipPAC Inc.
Abstract
Increased functionality requirements coupled with
progressively reducing package size have necessitated the
integration of flip chip packages into various baseband and
application processor products in mobile platforms. Such
products use flip chip technology using traditional capillary
underfill (CUF) process on a strip based package which is
subsequently over molded to finish the end-product assembly.
The growing pricing pressures and competitive landscape in
mobile-packaging has made it imperative for assembly
subcontractors to drive the flip chip assembly cost down. To
achieve this without compromising product reliability requires
a fundamental shift in the way these packages are assembled.
Molded underfill (MUF) approach offers such unique solution
with promising advantages over CUF; such as lower material
cost, higher through put and excellent reliability to meet the
overall product needs of today’s evolving mobile market; and
is discussed in this paper.
Capillary Underfill (CUF) has been the cornerstone of
today’s flip chip technology in both flip chip BGA and flip
chip CSP format. Several advancements in CUF materials and
dispense technologies made over years has made CUF the
underfill technology of choice for various flip chip
applications. However as the need for reducing package
assembly cost has grown simultaneously; CUF material and
underfill process comes under scrutiny due to higher material
cost and slow through put process in the flip chip assembly
flow. MUF was explored and found to be a viable lower cost
alternative for mobile products by virtue of lower material
cost and faster throughput due to batch process operation in
strip format. The cost benefit is further complemented by the
capability of MUF to enable finer spacing between die-to-die
and die-to-passives; as well as smaller keep-out zones to
enable reduced die-to-package edge clearance or effectively
shrink the overall package size than that with CUF. Use of
vacuum assisted molding was also found to be capable to fill
very small gap between die and substrate of the order of 50um
without voiding concerns.
This paper outlines the multidisciplinary effort undertaken
to design, develop, and qualify flip chip package with MUF
technology for mobile application; which was successfully
introduced in high volume production with yields and
reliability at parity with an equivalent CUF package. MUF
material with fine filler size was chosen from a material
screening DOE; and was used in series of test vehicles (TVs)
with different package configurations including single die and
multi-die flip chip CSP packages. Process and material
margin studies were conducted to establish process window
for MUF technology with eutectic and Pb-free bump
assemblies. Finally MUF technology was intercepted on
mobile application processor product with fcTFBGA-12x12
mm sq. package and 7.5X7.5 mm2 die towards a successful
introduction into high volume production. MUF challenges as
978-1-4244-6411-1/10/$26.00 ©2010 IEEE
well as known-limitations are also described along with future
plan. Further studies are being conducted to characterize and
qualify MUF on larger die sizes and/or with finer bump
pitches and to establish the process and reliability margins of
MUF with the same.
1.
Introduction
MUF is inherently conducive process for mobile products
as they are often made in CSP format using strip type
substrates which can be molded using traditional mold
systems. Conventional flip chip CSP used in mobile products
use 2 step approach; first using capillary underfill process to
underfill the gap between die and package substrate using
underfill material; and second using standard mold compound
to over mold the package. Mold Underfill (MUF) assembly
concept uses a single step approach to both underfill and over
mold the die during the same mold shot thus making the
process lot simpler and faster than that with CUF. The
schematic exemplifying this primary process difference
between the two is shown in Figure 1.1 below.
CUF
2 step process (Underfill + Mold)
MUF
Single Step Process (Mold Underfill)
Figure 1.1 Comparative Package Schematic Illustration of
Capillary Underfill and Mold Underfill.
Despite continued improvements in both the material
properties as well as dispensing systems and mechanisms;
underfill process still remains as one of the slowest processes
in flip chip assembly flow. This is primarily due to the fact
that it is not a batch process and needs to be done in a unit-byunit manner with typically up to two dispense heads used in
tandem to complete underfilling of multiple units on a boat or
in a strip. Secondly; capillary flow of underfill being surface
tension driven flow; is also slow being dependent on multiple
factors; including the solder mask and die passivation material
types; die size, bump count and pitch, etc.; which adds to the
total underfilling time.
MUF on the other hand can be done as a batch process
molding the entire strip with much faster throughput. Using
vacuum assisted mold system with fine fillers MUF materials;
very small gaps under the die or passives; as well as narrow
spaces between the two die or passives on the package can be
filled without concerns of voids.
Usually highly filled mold materials with relatively finer
filler sizes than those used in over mold compounds are used
for MUF materials. Higher filler loading helps with lowering
the CTE of the material; required to minimize the CTE
mismatch between Silicon die-MUF material-and package
substrate. Figure 1.2 shows the filler distribution of MUF
mold compound filling gap under the flip chip die.
1250 2010 Electronic Components and Technology Conference
Fill
A
B
UF dispensing side
C
C
B
A
Figure 1.2 Cross-sectional View of flip Chip with MUF
By choosing material with finer filler size and optimizing
vacuum mold process for the same; very small gaps of the
order of 50um can also be filled without trapping any mold
void as shown in Figure 1.3.
Figure 2.1 Package Design Rules with Clearance
Requirements for flip chip SiP with CUF.
C
A
B
Figure 2.2 Package Design Rules with Clearance
Requirements for flip chip SiP with MUF.
Design Rules
A Pkg edge to die edge
CUF
MUF
0.4mm - 1.3 mm 0.1mm -0.2mm
B Clearance btw dies
C Bump standoff height
0.8mm -1.0 mm
0.3mm -0.4mm
30um-50um
45um-60um
Table 2.1 Package Design Rules Comparison Between
CUF and MUF.
Figure 1.3 Cross-sectional View of Chip Capacitor with
~50um gap Filled with MUF Material.
2.
Package Design Consideration with MUF
MUF poses some key advantages over CUF when it
comes to designing a flip chip package for a mobile product.
CUF approach; using capillary dispense method forms fillets
around the die along all four sides. The underfill fillet at the
dispense side usually has the largest width. Hence the
package designers are required to keep minimum clearances
between die edge to package edge as well as between two die
or die and a neighboring passive component in case of a SiP
to fit in the underfill fillet.
MUF; due to it’s unique vacuum mold process unlike the
CUF; does not require underfill fillets; allowing the designers
to keep the die and/or the components much closer to each
other; thus offering the following benefits –
i)
Allowing package designers to keep smaller
keep-outs and enabling a smaller package size
with lower package / substrate cost;
ii)
Save real estate on PCB with smaller resulting
packages with MUF;
iii)
Improved electrical performance with lower
inductance path between a capacitor and power
bumps on the die.
Figure 2.1, Figure 2.2, and Table 2.1 illustrate production
compatible package design rules comparison for flip chip
CSP using MUF vs. CUF.
Evolving requirements for mobile products demanding
smaller, faster and cheaper packages have put the overall
manufacturing of the packages under scrutiny and the design
benefits offered by MUF have caught the eyes of product
designers and package assemblers alike.
3.
MUF Materials
Mold materials used as over mold compounds in wire
bonded or flip chip CSP devices are ubiquitous in mobile
packages of today. Their manufacturability as well as
reliability has been proven through field applications over
several years. However the mold materials intended for use as
MUF have not been as common to date; as they are subjected
to more stringent requirements than typical over mold
materials. MUF materials need to flow under flip chip die in
small stand off heights and in between hundreds to thousands
of bumps with a range of bump pitches. Generally flip chip
bump gap with substrates using Solder on Pad (SOP) is <80
um; and with Non-SOP (nSOP) assemblies could go down to
<50um range. Bump pitches for mobile products tend to be
with-in a range of 150um to 180u as of today; but shrinking
rapidly for majority of the products. Hence MUF material
needs to be capable to fill in such fine gaps without trapping
voids under the flip chip die which otherwise could result in
assembly yield loss or worse; a latent failure during board
assembly or in the field.
Other key requirement posed on MUF material is its
coefficient of thermal expansion (CTE); which needs to be
lowered to similar levels as capillary underfill to be able to
minimize CTE mismatch between silicon and substrate.
Hence MUF materials are very highly filled; which helps to
reduce the CTE but makes the mold flow more difficult. To
fulfill these two contradictory requirements posed on MUF; a
1251 2010 Electronic Components and Technology Conference
finer filler size is chosen along with vacuum assisted molding
to help with the mold flow yet keeping the higher filler
loading to maintain the low CTE. Figure 3.1 shows material
property chart showing a generic range of mold material
properties which MUF material is selected from. The range of
filler % content and Tg used to choose MUF materials from is
shown with a rectangular box.
MUF Range
Figure 3.1 MUF Material Properties.
Effect of filler size in MUF on voiding performance was
tested using fcVFBGA-SS3 (3-die side-by-side), 9.0 X
9.0mm Test vehicle with 200u minimum bump pitch and
using four separate MUF materials with range of different
filler sizes from high to low. Impact of stand-off height was
also studied using substrates w/ Cu-OSP (no –SOP) finish and
with SOP finish. Only the MUF materials with finer
(medium-to-Low) resulted into void-free assembly with both
substrate types as shown in Table 3.1
MUF Void
Sources MUF Matl. Filler size T-SAM
Max.
Substrate
Leg#
Leg 1
M1
High
29/35
Leg 2
M2
Medium
0/35
Leg 3
M3
Low
0/35
M4
Low
0/35
Leg 4
S1
Leg 5
M1
High
28/35
Leg 6
M2
Medium
0/35
Leg 7
M3
Low
0/35
M4
Low
0/35
Leg 8
S2
M4-Filler size - High
M4-Filler size - Low
Figure 3.2 X-Section Analysis of Unit Assembled with M1
and M4 MUF materials.
Another consideration when choosing the MUF materials
is its working temperature range. Typically very high mold
temperatures are required to allow good mold flow of MUF
materials. Which could be in the close vicinity of the melting
temperature of eutectic bump (~183 °C). Hence it is preferred
to use a material with wide working temperature range and
that can be molded at as much lower temperature than 183 °C
as possible to avoid melting the bump during mold process
which could otherwise could cause the device chip to de-wet
from the package substrate during molding process.
A controlled experiment was run to find a safe working
temperature range of the chosen MUF material for subsequent
studies. A temperature-viscosity characteristic chart provided
by the MUF material supplier as shown in Figure 3.3 was
used to define the working range of chosen MUF materials
for evaluation purpose.
Working Range.
Figure 3.3 Viscosity vs. Mold Temperature Characteristic
of MUF material.
Table 3.1 MUF Filler Size Impact DOE Results.
Severe mold voids were encountered with material M1
with High filler sizes with both substrate sources. X-section
analysis revealed that mold flow with High filler sized MUF
material (M1) under small gap causes uneven filler
distribution; which might have caused the mold voids to form.
Figure 3.2 shows the filler distribution comparison between
units assembled using M1 (High filler size) vs. M4 (Low filler
size) MUF materials –
The experiment was run using fcVFBGA 12x12 mm2
packages with single flip chip die using eutectic bumps. DOE
with 7 different legs with mold temperatures ranging from
high to low were run. Through scan after mold was used as
response variable to judge the molding process robustness
w.r.t. mold temperatures.
All mold temperatures except High temperature showed
no particular issues with mold flow, or mold voids. However
severe chip-flying accompanied by mold delamination (from
substrate) was observed at high mold temperature as shown in
Figure 3.4. The phenomenon was found to be caused due to
mold temperatures during MUF process reaching close to
eutectic melting point.
1252 2010 Electronic Components and Technology Conference
(High)
(Medium – Low )
Mold Temperature
Figure 4.1 MUF Process Flow for Flip Chip CSP.
Figure 3.4 Flip Chip Solder De-wetting at High Mold
Temperature.
Based on those results, a medium molding temperature
condition with adequate temperature tolerance on either ends
was established as optimal mold temperature range for flip
chip assemblies with eutectic bump using the chosen MUF
material.
Another key material property of MUF material is its
‘Spiral Flow’ property which represents flowability of mold
material under controlled conditions of pressure and
temperature, along a spiral runner of constant cross section.
It’s measured in terms of distance units that mold materials
travels. The mold material of choice needs to be tested for its
flow over the specification range of spiral flow due to
possible variations from different material batches.
A controlled study was run to check the spiral flow
specification range of the chosen MUF material through
assembly and temperature-humidity testing. Table 3.2
summarizes the results of the Spiral flow study experiment
conducted using the MUF material of choice showing no
voids or reliability concerns within the specification range.
EMC Property
Results
Leg#
Spiral Flow
MUF void 85 C/85 RH 85 C/85 RH
8 Hrs
4 Hrs
(T-SAM)
1
USL Spiral Flow:
0/120
0/40
0/40
2
Nominal Spiral Flow
0/120
0/40
0/40
3
LSL Spiral Flow:
0/120
0/40
0/40
Table 3.2 Spiral Flow Study Results.
MUF material batches with target-Nominal spiral
flow as well as those towards upper (USL) and lower (LSL)
end of the specification were tested and found to be robust in
terms of mold flow under the die confirming no voids; as well
as reliability through temperature-humidity testing.
4.
Assembly Process for MUF
MUF package assembly process flow is much simpler
than the conventional - (underfill + over mold) process flow
as MUF material accomplishes underfilling and over molding
functions in single step; thus eliminating pre-underfill plasma,
underfill, and underfill cure processes; making the overall
assembly process time much faster.
Figure 4.1 shows process flow used for MUF assembly of
flip chip CSP.
However optimizing the process parameters for MUF is a
non-trivial task requiring extensive characterization of each
critical assembly process step; to ensure robustness across the
process window. A comprehensive effort was undertaken to
check the robustness of the selected MUF material before
high volume production ramp. Mold parameters, and process
window times were studied as the key factors of MUF
process; besides the MUF material properties as described in
Section 3 of this paper.
MUF Process Parameter Study
A ‘Process FMEA’ (pFMEA) was conducted to identify
key processes to study to establish a robust operating window
for each. Amongst the mold parameters; mold transfer
pressure, mold transfer time and preheat time were chosen to
check the robustness of the chosen MUF material within the
operating window of each key parameter. MUF voids using
through scan (T SAM) and temperature-humidity testing were
used as response variables to ensure no voids and mold
delamination respectively.
Effect of Pre-Bake Window Time
Pre-bake step is done as a default before molding process
to ensure moisture is removed; but the process window time
between pre-bake-out to mold process needs to be controlled
as well to ensure effectiveness of the pre-bake process. Hence
studies to establish process window margin were run with
different window times in a separate study. Impact of these
process window times (i.e. moisture absorbed during pre-bake
and mold) on MUF void performance was checked. Table 4.1
summarizes the results obtained with process window study
run to assess impact of window times within a range of 24hrs
to 60hrs along with different deflux conditions (with (A) and
without (B) saponifier) as below.
Results
Process window time
Window MUF void
Deflux
Leg # Condition Pre-Bake Time (Hrs) (T-SAM)
1
A
C
24
0/120
2
A
C
48
0/120
3
A
C
60
1/120
4
B
C
24
0/120
Table 4.1 Pre-Bake-Mold Window Time Study.
As seen from the results; 24hrs and 48hrs window time
showed no mold void, however 60hrs window time leg
resulted in a mold void on one unit. Figure 4-2 shows the
1253 2010 Electronic Components and Technology Conference
TSAM image of mold void trapped near the center of the die;
and parallel-lap analysis reveled the void without presence of
any contaminant indicating potential moisture induced void
due to extended prebake window time of 60hrs.
T-SAM of Mold Void
P-Lap of Mold Void
Figure 4.2 TSAM and P-Lap of Mold void.
Package Warpage with MUF
Package warpage is another major consideration for
mobile packages to allow card attach assembly with very fine
BGA pitches of the order of 0.4mm. Warpage over the reflow
range is also critical to manage stress of silicon inner layers
and low-k as well as on substrate features. Hence it’s
imperative to assess impact of MUF on package warpage to
ensure compliance with maximum warpage criteria set by the
end-product user.
Package coplanarity analysis using RVSI technique was
conducted on flip chip FBGA with MUF using 12x12 mm2package size with 65N-low K fab node Silicon die of 7.5 X
7.5 mm2 size with eutectic bump. Figure 4.3 shows 3D
warpage plot and warpage readings obtained ensuring
compliance to the end-customer’s warpage specification of
max. (80u).
S/S
Criteria
Min
Max.
80 units 80um 32.7um
Max
Avg
St.Dev.
67.3um
48.1um
6um
X-Scale
#1
#2
#3
#4
#5
MUF -Package Warpage Over Reflow Range
150'C 220'C 260'C 220'C 150'C
2
3
4
5
6
20
39
51
41
22
19
40
48
42
21
22
43
53
46
25
24
43
57
52
30
18
37
45
40
23
Reliability Results:
Figure 5.1 shows flip chip Land Grid Array (fcLGA) test
vehicle (TV1) with two die side-by-side with passive
components using MUF. JEDEC standard reliability tests
were conducted and passed with no failures. More stringent
temperature cycle condition “C” was used; although passed
successfully along with other reliability tests. The reliability
results for TV1 are summarized in Table 5.1.
Test Mode & Condition
30'C/60% 192hr + 3x Reflow @ 260
130'C/85%RH With Precon-L3,
u/HAST
(Hrs)
Condition "C"(-65'C~150'C) With
Temp. Cycle
Precon-L3 , (# cycles)
150'C With Precon-L3 (Hrs)
HTST
MRT-L3
Shadow Moiré analysis was also conducted to check
warpage behavior change over the reflow temperature range
to sight any abnormal change in warpage with MUF and was
confirmed to be a non-issue. Figure 4.4 shows Shadow Moiré
warpage plots over the reflow temperature range; showing no
abnormal readings.
25'C
1
-48
-41
-41
-45
-48
Reliability Testing with MUF
Reliability of CUF has been proven through extensive
reliability testing through years of development and
qualification as well as field use. On the contrary; there is
limited reliability data and field experience with flip chip
using MUF; and hence ensuring its reliability performance
parity with CUF is of utmost importance to material suppliers
and assembly subcontractors as much as to the end-product
users.
A series of reliability testing was conducted with flip chip
devices using various different package configurations
typically used in mobile applications. Robustness of MUF
with both eutectic and pb-free bump was checked to ensure
compliance to ROHS and fully “green” requirements. Effect
of different die passivation materials including Silicon Nitride
and Polyimide and that of substrate solder resists on MUF
reliability was also checked to find MUF’s compatibility with
a variety of die passivation & substrate solder mask materials
being used in the industry. Open–short testing, as well as
through scan (TSCAN) was done after every read-point to
check for any failures. Upon completion or reliability testing;
cross-section analysis was done on sample units from each
test to specifically check for any anomaly like bump cracks or
silicon –low-K damage etc.; but none was found.
Figure 5.1 Schematic of TV1 using MUF
Figure 4.3 Room Temperature Warpage Analysis for Flip
Chip Package with MUF.
UNIT
5.
30'C
7
-51
-48
-42
-47
-50
Figure 4.4 Shadow Moiré Warpage Readings for Flip
Chip Package with MUF.
MRT-L3
0/537
192
N/A
1000x
N/A
0/180
0/180
NA
0/178
N/A
0/178
0/179
N/A
0/179
Table 5.1 Reliability Results with TV1 using MUF.
An extensive development effort was undertaken to
qualify MUF technology for TV2 (12x12 mm2-fcVFBGA
with 65N-low K fab node Silicon die – 7.5 X 7.5 mm2 with
eutectic bump) for an application processor product. Series of
DOEs followed by reliability testing was conducted to
generate assembly and reliability data prior to a successful
qualification. Figure 5.2 shows package schematic of TV2
which was qualified and introduced in high volume
production environment successfully with excellent field
performance.
1254 2010 Electronic Components and Technology Conference
Figure 5.2 Package Schematic of TV3 (fcFBGA with
Large Die; Eutectic Bump with 180u Bump Pitch)
Reliability margin testing was also conducted to check
MUF package robustness with more stringent test conditions
than those used during qualification. Much harsher moisture
preconditioning test (MSL2aA), temperature shock testing
condition “C” and Multi-reflow test with 270 °C was run as
part of the reliability margin testing. Specific improvements to
substrate solder mask, chip-attach flux, and deflux process
condition were made to meet more stringent MSL2aA
condition with MUF. Table 5.2 summarizes reliability margin
test results for TV2; which passed without any issues.
Test Mode & Condition
20X
MRT-L2aA 60 °C/60% 192hr + 3x Reflow @ 260 °C
20x Reflow, Peak Temp.- 270 °C
0/45
Multi-Reflow
130'C/85%RH With Precon-L3,
u/HAST
(Hrs)
Condition "C"(-65°C~150 °C) With
Temp. Cycle
Precon-L3 , (# cycles)
Condition "C"(-65°C~150 °C) With
Temp. Shock
Precon-L3 , (# cycles)
150 °C
HTST
MSL
0/50
N/A
192 1000
N/A 0/50
N/A N/A
0/45
0/45 N/A
0/45
N/A 0/45
0/45
N/A 0/45
N/A
N/A 0/45
Table 5.2 Reliability Results of TV2
Subsequent development effort was undertaken using TV3
(11X11 mm2 fcVFBGA with 65N-low K fab node with
Eutectic bump) to extend MUF capability to a relatively
larger die large die (9.3X 9.3 mm2) and finer bump pitch(180u). Similar JEDEC standard reliability conditions were
used to evaluate the robustness of this large die flip chip TV3.
Moisture preconditioning level “MSL3” was applied before
subsequent reliability testing. The qualification was
completed with passing all the tests as summarized in Table
5.3 below.
Test Mode & Condition
30'C/60% 192hr + 3x Reflow @ 260
130'C/85%RH With Precon-L3,
u/HAST
(Hrs)
Condition "B"(-55'C~150'C) With
Temp. Cycle
Precon-L3 , (# cycles)
150'C With Precon-L3 (Hrs)
HTST
MRT-L3
MRT-L3
0/68
192
N/A
1000
N/A
0/22
0/22
NA
0/23
N/A
0/23
0/22
N/A
0/22
temperature cycle condition “C” to induce failures; however
were found to pass the same without any failures thus further
substantiating the MUF package integrity with pb-free bump.
The reliability results of TV4 study are summarized in Table
5.4 below.
MUF Substrate
MRT
uHAST TC "B" TC "C"
HTS
Leg # Supplier MSL2aA MSL3 192 Hrs 1000x 500 x (Extn) 1000 Hrs
1
S1
0/78
0/156
0/78
0/78
78
0/78
2
S2
0/78
0/156
0/78
0/78
78
0/78
Table 5.4 Reliability Results of TV4 with MUF & Pb-Free
Bump.
Independent studies have been completed to check the
MUF compatibility with finer bump pitches (up to 150u
Bump pitch) and with Cu-column bump structure using pbfree solder cap. Other flip chip CSP test vehicles with 45N
fab node devices using Ultra Low K die-electric and Cucolumn bump at 150u bump pitch have been successfully
tested through assembly and reliability with excellent results.
[1], [2].
Board Level Reliability
TV2 (12x12 mm2-fcVFBGA with 65N-low K fab node
Silicon die – 7.5 X 7.5 mm2 with eutectic bump) was also
subjected to drop test to assess any significant impact of MUF
on board level reliability. Two separate solder ball alloy
compositions were used in the test; to choose the superior one
for adopting into end product. Assembled components of TV2
were then mounted on test boards for drop test and failures
were measured using event detector unit up to total 300 drops.
Table 5.5 shows drop test results summary for TV2 with
MUF with two solder ball alloy compositions.
TV De tails
MUF Le g 1 MUF Le g 2
Substrate Finish
Cu-OSP
Cu-OSP
Solde r Ball (0.5mm Pitch) / Alloy
A
B
0/30
0/30
Drop Te st Re sults
1-30 drops
1-300 drops
# Drops for 1st failure
4/30 (13%) 5/30 (16%)
196
66
Table 5.5 Drop test Results with TV2 using MUF.
Table 5.3 Reliability Results of TV3 (fcFBGA with Large
Die; Eutectic Bump with 180u Bump Pitch)
Reliability robustness of MUF with Pb-Free Bumped flip
chip was checked using TV4 (fcVFBGA 7X7 mm2, pb-free
bump composition -Sn2.5%Ag; with 180u bump Pitch). Same
mold compound that was previously qualified with eutectic
bump was applied although making necessary assembly
process changes to cater to pb-free bump reflow and deflux
requirements. The parts were assembled using substrates from
two different suppliers with pb-free SOP (SAC305 alloy).
JEDEC standard reliability testing was done to check the
reliability results. Upon passing 1000x Temperature cycle B;
the parts were subjected to additional 500 cycles of
Both the legs met the success criteria of ‘No failure within
min. 30 drops’ and showed low failure rate upto 300 drops
confirming no adverse impact of MUF on drop test reliability.
Alloy A; being more compatible with Cu-OSP substrate finish
showed later onset of failure as compared to alloy B; and
hence was chosen for the end-product.
6.
MUF Challenges and Limitations
Molding process is quite mature and established over
years of experience in use with wire bonded and flip chip
over molded packages. However MUF materials having
unique material properties catered towards substituting
underfill in a flip chip package pose unique challenges and
hence require special controls during high volume
manufacturing. Waxing frequency control for MUF and mold
flash control were particularly addressed during production
mode to improve overall assembly yield with MUF process.
1255 2010 Electronic Components and Technology Conference
Waxing process done to clean the mold chase cavity
before the mold shot is quite typical for any molding process.
However the frequency of waxing needs to be established for
specific mold material including that for MUF. Insufficient
and/or infrequent waxing could lead to difficulties in the
release function of the molded strip from the mold cavity
surface thus posing risk of damaging the device or package
itself.
Similarly; the mold flash needs to be controlled by proper
mold design; and substrate strip design. More uniform flow is
achieved if the mold underfill suction holes are kept along the
entire length of the cavity bar. Figure 6.1 shows a photo of
molded strip with mold flash at the air vent area caused due to
non-optimized top cavity tool design. Top cavity design was
modified adjusting the air vent depth and width to improve
the mold flash issues.
nature of CUF materials requiring more expensive ingredients
like base resin chemicals and hardeners and more complex
manufacturing process itself. Finer filer versions of MUF
materials do tend to be more expensive than the standard filler
sized versions; yet beating the capillary underfill cost by a
good margin. However one needs to take into account the
total volume of MUF material used is much higher than that
of CUF for the same package and die size as MUF material is
also used to over mold the package unlike the CUF material.
Hence specific cost savings only due to MUF materials is
dependent on die size, package size, mold cavity and most
importantly properties of specific MUF and CUF materials
under consideration.
As described in section 2.-‘Package Design
Considerations’; MUF enables a smaller keep outs between
die and die-and passives and die-package clearance
requirements as compared to conventional CUF. This allows
designers to design a flip chip CSP or SiP with a reduced
package size than with MUF; which indirectly helps in saving
package cost. This also helps in consuming lesser real estate
on the PCB card. Higher cost savings can be realized with SiP
or CSP with multiple die which would allow higher package
size reduction using MUF. Figure 7.1 shows the cost
comparison of the MUF and CUF process for different flip
chip packages sizes.
Limitation of MUF technology lies in its relatively narrow
scope to encompass a wide range of die and package sizes as
compared to CUF. MUF has not been widely used for very
large die sizes in mobile applications nor does extensive
reliability data exist to justify MUF viability for the same. Its
use in 3D applications with stacked die or with PiP/PoP
formats also remains limited; although prior work has shown
some promising results in other studies. [3]. Lastly; although
MUF using finer filler size mold materials and vacuum
assisted molding can fill small gaps; it still can not reach
parity with CUF owing to significantly small filler sizes used
in CUF materials. Hence very fine pitch, high bump density
applications with extremely small gap heights still require use
of CUF approach. Hence further development work is needed
to expand the scope of MUF to larger die sizes, finer bump
pitches and 3D packages to cater to a wider spectrum of flip
chip offerings in mobile packages.
7.
Cost Benefits with MUF
The molding system for MUF uses a vacuum mold to
ensure void free filling with distributed gate/vent design and
using mold compound with fine filler sizes. As explained
earlier; MUF can provide significant cost savings in the
assembly especially for over molded packages as it achieves
both underfill and over molding in a single batch process
unlike the convention CUF which is done in a unit-by-unit
manner even on a strip. Thus MUF makes the overall
assembly process faster with higher UPH than with CUF; and
thus helping with the process cost.
MUF materials tend to be lower in cost as compared to
CUF materials in general; due to inherently more complex
Assembly Cost (Normalized)
Figure 6.1 Mold Flash Issue at Air vent Area.
MUF
CUF
<20%
20-25%
>25%
7x7
Body Size (mm)
12x12
15x15
Figure 7.1 Relative cost comparison between MUF and
CUF for a single die flip chip CSP.
MUF offers significant assembly cost savings over CUF
as confirmed with a range of mobile products with different
package body sizes. However, the cost benefits of MUF
reduce with increasing package sizes due to strip size and
resulting strip utilization with specific package sizes. Higher
savings are achieved with smaller packages with more
number of units per strip thus increasing potential savings
with MUF. Nevertheless MUF cost benefits over CUF across
the overall range of mobile products remain promising.
8.
Summary & Conclusions
This paper provides a holistic view of Molded Underfill
(MUF) technology to the readers and package end-users
interested in adopting MUF for mobile applications. MUF
offers very promising packaging solution for mobile products
of today with several advantages over CUF; such as lower
material cost, higher process through put and excellent
reliability. A number of design, process and reliability
1256 2010 Electronic Components and Technology Conference
considerations with MUF; as well as its challenges and
limitations were discussed in this paper.
A material screening DOE was run to short-list workable
MUF materials to make a void-free and reliable MUF
packages. MUF materials with finer filler sizes using vacuum
assisted molding process were found to be robust in meeting
both assembly and reliability needs of the end-product. A
series of systematic experiments spanning different package
structures; die & package sizes; substrate and assembly
materials; as well as bump metallurgies were run to establish
substantiating assembly and reliability data with MUF.
Extensive reliability testing using JEDEC standard test
conditions was done thus confirming reliability robustness of
MUF with single-tier flip chip packages. In certain cases;
reliability testing was extended beyond the minimum
qualification requirements to ensue adequate reliability
margin with MUF. Board level drop testing was also
performed and excellent drop test performance was
confirmed.
All the learning gained through assembly development
and process and materials characterizations of MUF were
applied to the targeted mobile product in production. Design
and process improvements were made continuously to
establish a robust process for high volume manufacturing.
Assembly yield of >99.9% was achieved in production
scenario thus confirming the production readiness of MUF
technology.
Finally the design and cost benefits with MUF were
weighed against its technology limitations to establish best-fit
package scope for MUF and to define future work.
Acknowledgments
The authors would like to thank Mr. Young Whan Kim,
Sungji Trading Co. Ltd., for helping to provide material
property study details of the MUF material used during the
development of MUF technology.
References
[1] “Low Cost Flip Chip (LCFC): An Innovative Approach
for Breakthrough Reduction in Flip Chip Package Cost”;
Pendse R., et al, Stats ChipPAC Inc., ECTC 2010
Conference Paper. (to be published)
[2] “Innovative Approaches in Flip Chip Packaging for
Mobile Applications”; Pendse R; et al, Stats ChipPAC
Inc., ECTC 2009 Conference Paper.
[3] “Molded Underfill Development for FlipStack CSP”
Lee J.Y., et al, Amkor Technologies Ltd., ECTC 2009
Conference Paper.
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