5
4
CONTENT
D
2
1
SHEET
Cover Sheet
1
Block Diagram
2
Clock Distribution
3
Power Delivery Map
4
Platform Sequence
5
Reset Map
6
CK505 ClockGen
7
VRD11.1-ISL6334
8
LGA775 -1~3
9~11
Eaglelake -GMCH-1~4
C
3
12~15
DDRII-CHA/DIMM 1
16
DDRII-CHB/DIMM 2
17
DDRII-Termination
18
ACPI FOX-ONE
19
Power_3D3V_CL
20
VGA / DVI Connector
21
PCI-E16X Slot / GenII Switch
22
ICH10-1~4
23~26
RTL8101E/8111B
27
HDA Codec ALC888S
28
Super I/O -IT8720F
29
PCI Express x1 Slot
30
PCI Slot
31
ATX, FP, MISC Connector
32
CPU / System / NB Fan
33
KB/MS, TPM
34
LAN / USB Connector
35
Front USB Connector
36
HDA Audio Port
37
Reserved-1
38
Searl&Parallel Port/VIDO
39
GPIO / IRQ / IDSEL Map
40
History
41
B
G43M01
uATX
CPU:
(Version: 0A)
D
Intel Conroe, Wolfdale, Yorkfield processors in LGA775 Package.
System Chipset:
North Bridge ... G43
South Bridge ... ICH10R
Main Memory:
Dual Channel / DDR-II * 2 (Maximum to 8GB)
On Board Device:
Clock Generator ... ICS9LPRS919HKLF-T
Super I/O ... IT8720F
HDA Codec ... ALC888S
BIOS ... SPI Flash ROM
Expansion Slots:
PCI EXPRESS 16X SLOT *1
PCI EXPRESS 1X SLOT * 1
PCI SLOT * 2
PWM Controller:
Controller ...ISL6334 (3Phase)
C
Board Stack-up
(1080 Prepreg Considerations)
1.9mils Cu plus plating
B
Solder Mask
PREPREG 2.7mils
1 oz. (1.2mils)
Cu Power
Plane
CORE 47mils
1 oz. (1.2mils)
Cu GND
Plane
PREPREG 2.7mils
Solder Mask
A
1.9mils Cu plus plating
Single End 50ohm Top/Bottom : 4mils
USB2.0 - 90ohm : 15/4.5/7.5/4.5/15
SATA - 95ohm : 15/4/8/4/15
PCIE - 95ohm : 15/4/8/4/15
DMI - 95ohm : 15/4/8/4/15
A
FOXCONN PCEG
Title
Cover Sheet
Size
C
Date:
5
4
3
2
Document Number
Rev
A
G43M01S1
Sheet
Monday, August 11, 2008
1
1
of
41
5
4
3
2
1
VRD 11.1
3 Phase PWM
LGA775 Processor
Socket T
D
D
CK-505 Clock Generator
FSB
800/1066/1333
VGA
Connector
8 Lanes
PCI-E X16
GFX Connector
DDRII 667/800
Channel A DDRII
DIMM1
4 Lanes
GMCH
PCI-E Gen2
Switch
4 Lanes
Eaglelake-Q
DDRII 667/800
C
Channel B DDRII
C
DIMM2
Level
Shifter
DVI-D Connector
DMI I/F
4 Lanes
Back Panel
Contorl Link
USB2.0 Port 1
USB2.0 Port 2
USB 2.0
USB2.0 Port 3
USB2.0 Port 4
USB2.0 Port 5
PCI I/F
PCI Slot 1/2
ICH-10
USB2.0 Port 6
SATA I/F
B
RTL8111B/C
PCI-E X1
Serial ATA
B
SATA Connector 1
SATA Connector 2
Front Panel
PCI-E X1 Slot 1
PCI-E X1
SATA Connector 3
USB2.0 Port 7
HD Link
USB2.0 Port 8
Intel HD Audio
Realtek ALC888S
SATA Connector 4
SATA Connector 5
USB2.0 Port 9
TPM 1.2
SATA Connector 6
USB2.0 Port 10
LPC I/F
USB2.0 Port 11
SPI I/F
Super I/O
USB2.0 Port 12
BIOS
SPI Flash 8Mb
IT8720F
A
A
PS2
Floppy
Keyboard / Mouse
Drive Connector
COM1/COM2 Header
LPT Port
FOXCONN PCEG
Title
Block Diagram
Size
C
Date:
5
4
3
2
Document Number
Rev
A
G43M01S1
Sheet
Monday, August 11, 2008
1
2
of
41
5
4
3
2
1
14.318MHz
CPU
CPU 200/266/333 MHz Diff Pair
D
D
MCH 200/266/333 MHz Diff Pair
DDRII 2 Slots 6 Diff CLKs
PCI Express 100 MHz Diff Pair
Channel A DDRII DDRII 667/800
PCI Express x16 Gfx
DIMM1
GMCH
DOT 96 MHz Diff Pair
Eaglelake
Channel B DDRII DDRII 667/800
DIMM2
PCI Express/DMI 100 MHz Diff Pair
CK-505
C
C
PCI Express/DMI 100 MHz Diff Pair
USB/SIO 48 MHz
ICH 33 MHz
REF 14 MHz
ICH10
Azalia Bit Clock
PCI 33 MHz
B
PCI Slot 1
PCI 33 MHz
B
PCI Slot 2
32.768KHz
TPM 33 MHz
TPM 1.2
HD Audio
Super I/O
SIO 33 MHz
SATA 100 MHz Diff Pair
PCI Express 100 Mhz Diff Pair
PCI Express x1 Slot 1
A
A
PCI Express 100 Mhz Diff Pair
RTL8111B/C
FOXCONN PCEG
Title
Clock Distribution
Size
C
Date:
5
4
3
2
Document Number
Rev
A
G43M01S1
Sheet
Monday, August 11, 2008
1
3
of
41
5
4
3
2
1
3.3V
ATX P/S
Super I/O
3.3V
Icc(Max)=50mA
Proceessor
5V
D
5VSB
Vccp (CPU Vcore)
Voltage=1.15~1.5V
Icc(Max)=70A
4-Phases Swithing
VRD 11.1
Switching
4 Phase
12V
5VDUAL
Icc(Max)=
4.345A(S0,S1)
22mA(S3)
DDR2 Channel A
Vdd (Core)=1.8V
Ivdd(Max)=4.7A(per channel)
3.3SBV
Icc(Max)=50mA(S0)
3.3SBV
Icc(Max)=38mA(S3)
1.1V FSB
Vtt=5.3A
USB2.0
Vtt (Core)
0.9V
Ivterm(Max)=200mA
(per channel)
DDR2 Channel B
FSB_Vtt
1.1V FSB Vtt
Icc(Max)=1.3A
Linear 1.8V
to 1.1V
6A
D
5VSB
5VDUAL
Icc(Max)=
4.345A(S0,S1)
22mA(S3)
12 Ports
+5V DUAL=5A(S0, S1)
+5V DUAL=20mA(S3)
Eaglelake GMCH
Single Phase Switch
5V to 1.8V
Ivdd(Max)=14A
Ivdd(Max)=650mA(S3)
LDO
1.8V to 0.9V
Ivterm(Max)=1.2A
5V
PS2
+5V DUAL=345mA(S0, S1)
+5V DUAL=2mA(S3)
1.5V VCCSM
1.5V VCC_SMCLK
Vdd (Core)=1.8V
Ivdd(Max)=4.7A(per channel)
GMCH 1.1V
21.34A
Switching
Vtt (Core)
0.9V
Ivterm(Max)=200mA
(per channel)
Vcore (Core Logic)
1.1V
Icc(Max)=13.8A(Integrated)
*1.25V (DMI&PCIe)
VCCA_EXP 2.47A
1.1V
VCC_CL 4.3A
C
PCI Express X16
slot (1)
3.3VSB
Icc(Max)=0.375A(wake)
Icc(Max)=0.02A(no wake)
C
+3.3V=3A
3.3V VCCA_DAC 66mA
3.3V VCC3_3 15.8mA
3.3V
12V
+12V=5.5A
PCI Express X1
Per slot (2)
HDA Codec
Vcc
5V
Icc(Max)=200mA
LDO
12V
to 5V
+12V=0.5A
3.3VSB
Icc(Max)=0.375A(wake)
Icc(Max)=0.02A(no wake)
ICH10
Vcc
3.3V
Icc(Max)=40mA
1.1V VCCDMI 41mA
+3.3V=3A
Linear 1.8V
to 1.05V
V_1P05V_ICH
2A
B
1.1V VCC_CPU_IO 14mA
1.05V (Core) VCC1_05
1.43A
1.5V (USB &SATA) VCC1_5A
1.652A
1.5V (PCIe)VCC1_5B
0.646A
1.5V VCCGLAN1_5
80mA
Linear 1.8V
to 1.5V
V_1P5V_ICH
2.2A
RTC
Battery
5VSB
PCI Slot
-12V
Icc(Max)=0.1A
5V
5V_STBY to 3.3SB
1.5A
3.3V
B
5V
Icc(Max)=5A
3.3V
Icc(Max)=7.6A
RTC=5uA
3.3V
3.3V
3.3V
3.3V
3.3V
-12V
12V
Icc(Max)=0.5A
VccCL3_3 19mA
VccSUS3_3 212mA
VccLAN (10/100) 19mA
VccSUSHDA 32mA
VCC3_3 308mA
3.3VSB
Icc(Max)=0.375A(wake)
Icc(Max)=0.02A(no wake)
3.3V VccGLAN3_3 1mA
3.3V VccHDA 32mA
Boazman GbE Lan
3.3V STBY
IO LED 15.5mA
A
1.8V ANALOG 418.2mA
A
BJT
CK505
1.0V Internal 1.8
to 1.0 VR core
277.2mA
Vdd (Core)
3.3V
Ivdd(Max)=250mA
FOXCONN PCEG
Title
Power Delivery Map
Size
C
Date:
5
4
3
2
Document Number
Rev
A
G43M01S1
Sheet
Monday, August 11, 2008
1
4
of
41
5
4
3
2
1
D
D
C
C
B
B
A
A
FOXCONN PCEG
Title
Platform Sequence
Size
C
Date:
5
4
3
2
Document Number
Rev
A
G43M01S1
Sheet
Monday, August 11, 2008
1
5
of
41
3
2
CPU
LGA775 processor
D
1
CPURST#
4
CPU_PWRGD
5
D
ATX
Power
PWRGD_PS
Translation
Circuitry
PWRGD_3V
PWROK
PS_ON#
CPURST#
GMCH
Eaglelake
RSTIN#
Buffer
RST# PCI-E X16
C
C
PCI-E X1
RST# Slot 1
Buffer
Slot 2
ICH_PWRGD
PLTRST#
Buffer
RST#
TPM 1.2
ICH10
PCIRST#
Front Panel
RST# PCI Slot 1
PWROK
FR_RST
SYS_RESET#
PWRBTN#
SLP_S3#
RSMRST#
AC_RST#
SW_ON
B
RST#
HD Audio
B
RCIN#
RST#
Power on/off
circuit
KBRST
RSMRST#
Super IO
SLP_S3#
PSIN
PSOUT#
A
A
RSMRST circuit
FOXCONN PCEG
Title
Reset Map
Size
C
Date:
5
4
3
2
Document Number
Rev
A
G43M01S1
Sheet
Monday, August 11, 2008
1
6
of
41
5
4
3
2
1
3D3V_CLK
X3
*
1
23
R107
CK_14M_ICH
33
33+/-5%
33M_PCI1
R111
33+/-5%
33M_PCI2
ICS_FSBSEL2
3
5
7
ICS_FSBSEL0
SEL24_48
+/-5%
+/-5%
96M_P_GMCH
96M_N_GMCH
2
4
6
8
SATA_100M_P_ICH
SATA_100M_N_ICH
0 Ohm
+/-5%
C
PCI-E x1 (Slot1)
R151
R155
R159
23 CK_PWRGD
30 CK_PE_100M_P_1PORT_1
30 CK_PE_100M_N_1PORT_1
PCI-E JMicron 368
0
0
0
+/-5%
+/-5%
+/-5%
PE_100M_P_1PORT
PE_100M_N_1PORT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
3D3V_CLK
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
FSLB/PCICLK4_2X
VDDPCI
PCICLK5_2X
PCICLK6_2X
VDD48
FSLA/USB_48
*SEL24_48#/24_48Mhz
GND
DOT96T_LR/PCIeT_LR10
DOT96C_LR/PCIeC_LR10
GND
SATACLKT_LR
SATACLKC_LR
VDDSATA
GND
Vtt_PwrGd/PD#/WOL_STOP#
PCIeT_LR0
PCIeC_LR0
3D3V_CLK
ICS9LPRS919
4.7K
CPUT_L1F
CPUC_L1F
RESET_IN#/RESET#
**RLATCH
GNDA
24.576Mhz
VDDA
GND
25Mhz
VDD
VDD
GND
PCIeT_LR9
PCIeC_LR9
PCIeT_LR8/CPU_STOP#*
PCIeC_LR8/PCI_STOP#*
GND
PCIeT_LR7
+/-5%
200M_P_GMCH
200M_N_GMCH
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
0
Dummy
+/-5%
CK_200M_P_GMCH 12
CK_200M_N_GMCH 12
FP_RSTJ
10,23,32
SLP_S4J
19,23
Close to pin 48, 61
3D3V_CLK_REF_A
3D3V_SYS
L31
3D3V_CLK
3D3V_CLK_REF_A
*
FB 100 Ohm
R154
R157
1K
1K
RN19
PE_100M_N_GMCH
PE_100M_P_GMCH
PE_100M_N_ICH
PE_100M_P_ICH
*internal pull-up resistor
**internal pull-down resistor
RESET pin is 3.3V tolerant
+/-5%
+/-5%
*C165 *
CK_CPU_STOP 23
CK_PCI_STOP 23
0.1uF
C
C187
0.1uF
RN18
*1
3
5
7
2
4
6
8
0 Ohm +/-5%
3
5
7
2
4
6
8
0 Ohm
*1
+/-5%
CK_PE_100M_P_LAN 27
CK_PE_100M_N_LAN 27
CK_REFSSCLK_P_GMCH 12
CK_REFSSCLK_N_GMCH 12
CK_PE_100M_N_GMCH
CK_PE_100M_P_GMCH
CK_DMI_N_ICH 23
CK_DMI_P_ICH 23
12
12
**
SMBus Address :1101-0010
PE_100M_N_16PORT
PE_100M_P_16PORT
3D3V_CLK
B
R162
R161
0
0
+/-5%
+/-5%
CK_PE_100M_N_16PORT
CK_PE_100M_P_16PORT
22
22
Double check???
FSB_VTT
CLK_TURBO1
33+/-5%
33+/-5%
R132
PE_100M_P_LAN
PE_100M_N_LAN
REFSSCLK_P_GMCH
REFSSCLK_N_GMCH
High: 24 MHZ
Low: 48 MHz
R147 Dummy
4.7K
+/-5%
R136
4.7K
+/-5%
R122
R124
ICS9LPRS919HKLF-T
PCI-E x16 Slot
SEL24_48
CK_200M_P_CPU 10
CK_200M_N_CPU 10
1
*1
R106
R115
R135
GND
PCIeT_LR1
PCIeC_LR1
VDD
PCIeT_LR2
PCIeC_LR2
GND
VDD
PCIeT_LR3
PCIeC_LR3
PCIeT_LR4
PCIeC_LR4
GND
PCIeC_LR5
PCIeT_LR5
PCIeC_LR6
PCIeT_LR6
PCIeC_LR7
+/-5%
33
33
33
33
3D3V_CLK
FSLC/PCICLK3_2X
PCICLK2_2X
**SEL_STOP/PCICLK1_2X
PCICLK0_2X
GND
DOC_1**
DOC_0**
REF0/GSEL*
GND
X1
X2
VDDREF
SDATA
SCLK
GND
CPUT_L0***
CPUC_L0***
VDDCPU
U12
GND
Dummy 33 +/-5%
RN15
12 CK_96M_P_GMCH
12 CK_96M_N_GMCH
24 CK_SATA_100M_P_ICH
24 CK_SATA_100M_N_ICH
ICS_FSBSEL1
+/-5%
R133
R139
23 CK_48M_ICH
29 CK_48M_SIO
+/-5%
+/-5%
SMB_DATA_MAIN 33,34,38
SMB_CLK_MAIN 33,34,38
2
CK_33M_PCI2
check value???
33
200M_P_CPU
200M_N_CPU
SEL_PCI_STOP
3D3V_CLK
33
1 COPPER
1 COPPER
1
R113
2
2
CK_33M_PCI1
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
31
R119
R123
#REFDE1
2
#REFDE2
R112
73
31
CK_33M_TPM
CK_33M_SIO
CLK_TURBO1
CLK_TURBO2
3D3V_CLK
4.7K
+/-5%
Please close to each power pin
34
29
2
1
2
2
2
2
2
2
2
2
2
2
2
SEL_STOP: latched input to select pin functionality
1 = Selects pin 41/42 to be PCI_STOP#/CPU_STOP#
0 = Selects pin 41/42 to be PCIEX outputs
R118
D
3D3V_CLK_REF_A
near pin3
CK_33M_ICH
C157
33pF
*
Place near Clock generator
+/-5%
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 4.7uF 0.1uF 4.7uF 0.1uF
25
C158XTAL 14.318MHz
33pF
*
1
1
1
1
1
*C175*C199*C189*C190*C192*C171*C172*C201*C198*C181
1
C197
10uF
1
*
FB 100 Ohm
1
*
*
3D3V_CLK
1
L32
*
GSEL Pin
Hi: pin9&pin10 selects DOT 96Mhz 4.7K
Low:pin9&pin10 selects PCIEX0.
+/-5%
3D3V_CLK
FB 100 Ohm
Dummy
L33
D
R116
**
3D3V_SYS 3D3V_SB
B
CLK_TURBO2
RN54
R114
*1
R101
4.7K
Dummy
4.7K
Dummy
+/-5%
2
4
6
8
3
5
7
+/-5%
FSBSEL0
FSBSEL1
FSBSEL2
*
470 Ohm
+/-5%
FSBSEL1
R96
ICS_FSBSEL1
470 +/-5% R98 Dummy
4.7K +/-5%
To CLK
Dummy
8.2K
Dummy
*
C
R97
FSBSEL2
R95
B
1K+/-5%
CK_33M_TPM
CK_48M_SIO
CK_48M_ICH
C163
10pF
C156
10pF
dummy
*
1
*
C150
10pF
2
dummy
1
C174
10pF
*
2
dummy
1
C151
10pF
*
2
Add for EMI
1
C184
18pF
+/-5%
*
2
dummy
1
C185
10pF
*
2
dummy
1
C162
10pF
*
2
1
A
2
CK_33M_PCI1
CK_33M_SIO
CK_33M_ICH
CK_14M_ICH
CK_33M_PCI2
dummy
*
ICS_FSBSEL0
R126
+/-5%
Gen.
H_FSBSEL1
12
FSBSEL1
Dummy
E
Dummy
*
From CPU
Q23
MMBT3904-7-F
2.2K
+/-5%
FSBSEL0
BSEL TABLE
FS_C FS_B FS_A
FSB Frequency
0
0
1
0
1
0
200MHz(800)
0
0
0
266MHz(1066)
133MHz(533)
1
0
0
333MHz(1333)
1
1
0
400MHz(1600)
10,12
ICS_FSBSEL1
R109
2.2K
+/-5%
FSBSEL1
10,12
ICS_FSBSEL2
R110
2.2K
+/-5%
FSBSEL2
10,12
A
FOXCONN PCEG
EMI CAPS.
Title
CK505 ClockGen
Size
C
Date:
5
4
3
2
Document Number
Rev
A
G43M01S1
Sheet
Monday, August 11, 2008
1
7
of
41
6.2k Ohm
+/-1%
@clone r0402h4
VR601
*
6.8K
+/-1%
@SI r0402h4
VR293
6.2k Ohm
+/-1%
@cloner0402h4
VR602
6.8K
+/-1%
@SI r0402h4
U9
6
PVCC
UGATE
1
PWM PHASE
8
4
GND
5
D
10K
+/-5%
G
R163
2.2
C203
+/-5%
HG2 U14
1 UGATE
2
PWM2 3 BOOT
PWM
4 GND
0.22uF
25V, X7R, +/-10%
8
7
6
5
PHASE
PVCC
VCC
LGATE
R175
2.2
+/-5%
R168 10K
+/-5%
R261
240K
+/-1%
r0603h6
0
*
+/-5%
S
22uF
R105
C154
2.2
+/-5%
HG3 U10
1 UGATE
2
PWM3 3 BOOT
PWM
4 GND
0
+/-5%
0.22uF
25V, X7R, +/-10%
PHASE
PVCC
VCC
LGATE
8
7
6
5
*
22uF
1
*C251 *C242 *C276 *C277
C127
4.7uF
25V, Y5V, +80%/-20%
22uF
22uF
6.3V, X5R, +/-10%
6.3V, X5R, +/-10%
6.3V, X5R, +/-10%
6.3V, X5R, +/-10%
R84
2.2
+/-5%
R87
Q18
AOD452
G
L29
10K
+/-5%
2
LG3
*R80
*C272 *C259 *C271 *C266
1
*
Dummy
*
R584
VIN
R121
2.2
2
Dummy
C585
0.1uF
Dummy
12V_VRM
+/-5% +/-1%
@clone
1
R279
R583 22K
+/-5%
10K
+/-1% 2 @SI
1
0
2
TM
OFS
TCOMP
R260
22uF
Choke 400nH
22uF
1
100KOhm
+/-1%
39
9
18
C
PHASE2
ISEN2
22uF
22uF
2
10nF
c0402h6
*
R258
*
*
C324
TM
OFS
TCOMP
C221
1nF
50V, X7R, +/-10%
1
SS
Q37
AOD472
EC35
820uF
+/-20%
2
FS
35
Q36
AOD472
C216
1uF
*
1
34
SS
240K
r0603h6
*R280
40.2K
G
2
FS
+/-1%
*
9,10,12
EC45
820uF
+/-20%
*
2.2
G
1
Dummy
EC36
820uF
+/-20%
2
Dummy 100KOhm
R259
*
1
Choke 400nH
1
**
R256
EC48
820uF
+/-20%
2
REF
HCPURSTJ
+/-5%
R267
*R180
LG2
V_6334V_6334
0
Dummy
*
L45
2
S
12
37
38
Q30
AOD452
G
D
REF
R264
VR_FAN
VR_HOT
*
C126
4.7uF
25V, Y5V, +80%/-20%
1
*
*
*
R179
2.2
S
DAC
EC32
820uF
+/-20%
*
EC34
820uF
+/-20%
VIN
D
11
DAC
R281
r0402h4 1K
*
*
EC33
820uF
+/-20%
PHASE1
ISEN1
12V_VRM
*
IMON
*
EC46
820uF
+/-20%
C137
1nF
50V, X7R, +/-10%
Q21
AOD472
*
V_6334
*
V_6334
C
10
VCCP
G
Q24
AOD472
ISL6612ACBZA-T
IMON
1
Choke 400nH
2.2
ISL6622CBZ
C159
1uF
2
*R82
LG1
2
PWM4
ISEN4+
ISEN4-
R86
L30
D
25
23
24
LGATE
HG1
D
Q19
AOD452
G
S
*
*
*
* *
*
C308
0.1uF
c0402h6
dummy
VCC
3
*
*
*
VSEN
GND
C313
0.1uF
c0402h6
dummy
VDIFF
41
**
*
R263
100 Ohm
+/-1%
*
RGND
*
PWM3
31
ISEN3+
R250510 Ohm ISEN3
29
ISEN3- C2920.1uF
C285
30
PHASE3
0.1uF
+/-1%
R249
6.8K
C293
+/-1%
Dummy
56pF#VR293#VR602
+/-5%
PWM3
ISEN3+
ISEN3-
*
T
10 P_VSS_SENSE
*
7
C195
4.7uF
25V, Y5V, +80%/-20%
*
10 P_VCC_SENSE
PWM1
PWM2
20
ISEN2+
R253510 Ohm ISEN2
22
ISEN2-C2970.1uF
C287
21
PHASE2
R254
6.8K
0.1uF
+/-1%
Dummy
C296
+/-1%
56pF#VR292#VR601
+/-5%
PWM2
ISEN2+
ISEN2-
FB
R283
68 Ohm C315
470pF @SI
+/-5%@SI
50V, NPO, +/-5%15
VDIFF
R273
1.24K
+/-1%
+/-1%#VR289#VR598
R243
R262
0
#VR288#VR597
@SI
10K
@SI VSEN 17
C310
10nF
RGND
16
*750
R284
*
*
R255
100 Ohm
+/-1%
*
COMP
*
**
VCCP
ISL6334CRZ-T
PWM1
26
ISEN1+
R251510 Ohm ISEN1
28
ISEN1- C2950.1uF
C286
27
PHASE1
R252
6.8K
0.1uF
+/-1%
Dummy
+/-1%
C294
#VR291#VR600
56pF
+/-5%
PWM1
ISEN1+
ISEN1-
*
PSI#_VRM
+/-5%
R282
30K C325
1.5nF
COMP
#VR290#VR599+/-1% #VC601#VC602
50V, X7R,
+/-10%
13
C317
22pF
#VC599#VC600
50V, NPO, +/-5% FB
14
C302
Dummy 120pF
0
Dummy
*
R278
EN_PWR
VR_RDY
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
PSI#
*
PSI#
32
36
40
1
2
3
4
5
6
7
8
VCC
EN_VTT
U18
EN_PWR
10,23 P_VRM_GD
10
VID7
10
VID6
10
VID5
10
VID4
10
VID3
10
VID2
10
VID1
10
VID0
10
PSI#
2
*
19
33
1.24K
+/-1%
r0603h6
0 +/-5%
@clone
r0603h6
@SI
BOOT
*
*
* *
+/-5%
C161
0.22uF
25V, X7R, +/-10%
R83
2.2
+/-5%
D
*
R117
2.2
10,19
S
*
1.2KOhm
C304
VTT_PWRGD
2.2uF
6.3V, Y5V, +80%/-20%
D
C300
0.1uF
+/-5%
S
*R277
680
* *
+/-1%
2.2
12V_VRM
*
R248
C290
V_6334
1uF
16V, Y5V, +80/-20%
D
VTT_OUT_RIGHT
D
VIN
R134
*
D
R257
2.2
+/-5%
S
*
D
*
10K
+/-1%
6.2k Ohm
+/-1%
@cloner0402h4
*
30K
+/-1%
r0603h6
VR599
21K
@clone+/-1%
r0603h6
5V_SYS
*
* *
VR290
@SI
r0402h4
VR597
3KOhm+/-1%
@clone
r0402h4
VR598
VR292
VR600
12V_VRM
R247
750
+/-1%
@SI
VR289
6.8K
+/-1%
@SI r0402h4
1
VC602
*
VR288
VR291
2
*
1.5nF
50V,
c0402h6
X7R, +/-10%
@SI
2.2nF
50V,
c0402h6
X7R,+/-10%
@clone
* *
VC601
* *
22pF
50V,
c0402h6
NPO, +/-5%
@SI
120pF
50V,NPO,+/-5%
c0402h6
@clone
T
VC600
3
*
VC599
4
*
5
2.2
ISL6612ACBZA-T
G
G
6.3V, X5R, +/-10%
6.3V, X5R, +/-10%
6.3V, X5R, +/-10%
6.3V, X5R, +/-10%
C138
1nF
50V, X7R, +/-10%
6.3V, X5R, +/-10%
1
2
1
1
*C258
2
22uF
22uF
6.3V, X5R, +/-10%
2
22uF
5V_SYS
6.3V, X5R, +/-10%
*C250
1
*C264
Q71
B
22uF
6.3V, X5R, +/-10%
2
22uF
22uF
6.3V, X5R, +/-10%
2
2
22uF
1
1
*C241 *C270 *C240 *C257
PHASE3
ISEN3
2
Q25
AOD472
1
C168
1uF
S
Q22
AOD472
S
*
B
5V_SYS
PSI#_VRM
6.3V, X5R, +/-10%
C142
0.1uF
c0402h6
PSI#
*
Q68 Q69
MMBT3904-7-F
MMBT3904-7-F
2
GND
B
22uF
74V1G66CTR
5V_SYS
R100
*
B
C214
10uF
c0805h14
*C275
22uF
6.3V, X5R, +/-10% 6.3V, X5R, +/-10%
6.3V, X5R, +/-10%
3
E
5.1KOhm
+/-1%
*
22uF
C
C
C
R416
E
HCPURSTJ
*
C249
OI 2
4
6.3V, X5R, +/-10%
C265
1
1K
2
*
*R432
1
1K
1
5 VCC
*R397
2
IO 1
*
1K
*
*
C564
100uF
2V,+30/-20%
Dummy
4
Dummy
HCPURSTJ
Input LC circuit
1
1K
3
B R99
E
E
2
C
C
PWR2
Q70
Q72
MMBT3904-7-F
MMBT3904-7-F
B
C565
100uF
2V,+30/-20%
12V_VRM
Header_2X2
*
L28
Add PSI control circuit for Wolfdale and Yorkfield CPU.
050908
2
1
*
VIN
1.2uH@100KHz
C128
0.1uF
16V, Y5V, +80%/-20%
*
EC21
1000uF
+/-20%
*
EC22
1000uF
+/-20%
*
EC23
1000uF
+/-20%
*
EC26
1000uF
+/-20%
Dummy
A
A
FOXCONN PCEG
Title
Size
C
Date:
5
4
3
2
VRD11.1-ISL6334CRZ-T
Document Number
Rev
A
G43M01S1
Sheet
Monday, August 11, 2008
1
8
of
41
5
4
3
HDJ[63..0]
HDJ[63..0]
2
12
12
HAJ[35..3]
HAJ[35..3]
U2A
U2B
D
HDJ0
HDJ1
HDJ2
HDJ3
HDJ4
HDJ5
HDJ6
HDJ7
HDJ8
HDJ9
HDJ10
HDJ11
HDJ12
HDJ13
HDJ14
HDJ15
12
12
12
HDBIJ0
HDSTBNJ0
HDSTBPJ0
HDJ16
HDJ17
HDJ18
HDJ19
HDJ20
HDJ21
HDJ22
HDJ23
HDJ24
HDJ25
HDJ26
HDJ27
HDJ28
HDJ29
HDJ30
HDJ31
12
12
12
C
HDBIJ1
HDSTBNJ1
HDSTBPJ1
2 OF 7
B4
C5
A4
C6
A5
B6
B7
A7
A10
A11
B10
C11
D8
B12
C12
D11
A8
C8
B9
D00#
D01#
D02#
D03#
D04#
D05#
D06#
D07#
D08#
D09#
D10#
D11#
D12#
D13#
D14#
D15#
DBI0#
DSTBN0#
DSTBP0#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
DBI2#
DSTBN2#
DSTBP2#
G16
E15
E16
G18
G17
F17
F18
E18
E19
F20
E21
F21
G21
E22
D22
G22
D19
G20
G19
G9
F8
F9
E9
D7
E10
D10
F11
F12
D13
E13
G13
F14
G14
F15
G15
G11
G12
E12
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
DBI1#
DSTBN1#
DSTBP1#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DBI3#
DSTBN3#
DSTBP3#
D20
D17
A14
C15
C14
B15
C18
B16
A17
B18
C21
B21
B19
A19
A22
B22
C20
A16
C17
HDJ32
HDJ33
HDJ34
HDJ35
HDJ36
HDJ37
HDJ38
HDJ39
HDJ40
HDJ41
HDJ42
HDJ43
HDJ44
HDJ45
HDJ46
HDJ47
HDBIJ2
HDSTBNJ2
HDSTBPJ2
12
12
12
12
12
HAJ[35..3]
TP36
TP24
HREQJ[4..0]
HAJ[35..3]
12
HAJ3
HAJ4
HAJ5
HAJ6
HAJ7
HAJ8
HAJ9
HAJ10
HAJ11
HAJ12
HAJ13
HAJ14
HAJ15
HAJ16
TP_CPU_N4
TP_CPU_P5
HREQJ0
HREQJ1
HREQJ2
HREQJ3
HREQJ4
HADSTBJ0
HAJ17
HAJ18
HAJ19
HAJ20
HAJ21
HAJ22
HAJ23
HAJ24
HAJ25
HAJ26
HAJ27
HAJ28
HAJ29
HAJ30
HAJ31
HAJ32
HAJ33
HAJ34
HAJ35
HDJ48
HDJ49
HDJ50
HDJ51
HDJ52
HDJ53
HDJ54
HDJ55
HDJ56
HDJ57
HDJ58
HDJ59
HDJ60
HDJ61
HDJ62
HDJ63
HDBIJ3
HDSTBNJ3
HDSTBPJ3
1
12
12
12
12
TP26
TP25
HADSTBJ1
L5
P6
M5
L4
M4
R4
T5
U6
T4
U5
U4
V5
V4
W5
N4
P5
K4
J5
M6
K6
J6
R6
A03#
A04#
A05#
A06#
A07#
A08#
A09#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
RSVD1
RSVD2
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
ADSTB0#
AB6
W6
Y6
Y4
AA4
AD6
AA5
AB5
AC5
AB4
AF5
AF4
AG6
AG4
AG5
AH4
AH5
AJ5
AJ6
TP_CPU_AC4 AC4
TP_CPU_AE4 AE4
AD5
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
A32#
A33#
A34#
A35#
RSVD3
RSVD4
ADSTB1#
1 OF 7
D2
C2
D4
H4
G8
B2
C1
E4
AB2
P3
C3
E3
AD3
G7
AB3
U2
U3
ADS#
BNR#
HIT#
FC35
BPRI#
DBSY#
DRDY#
HITM#
IERR#
INIT#
LOCK#
TRDY#
FC36
DEFER#
FC37
FC29
FC30
TP_CPU_H4
TP_CPU_AD3
TP_CPU_AB3
TP_CPU_U2
TP_CPU_U3
F3
G1
C9
G4
G3
H5
HBR0J
BPMB0J
BPMB1J
BPMB2J
BPMB3J
TESTHI_10
FC31
FC32
FC33
FC34
J16
H15
H16
J17
TP_CPU_J16
TP_CPU_H15
TP_CPU_H16
TP_CPU_J17
GTLREF0
GTLREF1
GTLREF2
GTLREF3
H1
H2
F2
G10
FC10
FC15
E24
H29
RESET#
G23
HCPURSTJ
B3
F5
A3
HRSJ0
HRSJ1
HRSJ2
BR0#
BPMB0#
BPMB1#
BPMB2#
BPMB3#
TESTHI_10
RS0#
RS1#
RS2#
HADSJ
HBNRJ
HITJ
TP32
HBPRIJ
HDBSYJ
HDRDYJ
HITMJ
HIERRJ
INITJ
HLOCKJ
HTRDYJ
TP31
HDEFERJ
TP43
TP53
TP56
12
12
12
12
12
12
12
10
24
12
12
HBR0J
BPMB0J
BPMB1J
BPMB2J
BPMB3J
TESTHI_10
10,12
10
10
10
10
10
D
12
TP15
TP14
TP11
TP9
CPU_GTLREF0
CPU_GTLREF1
CPU_GTLREF2
CPU_GTLREF3
TP_CPU_E24
TP_CPU_H29
TP6
TP5
8,10,12
12
12
12
C
Socket-IntelPrescottCPU
Socket-IntelPrescottCPU
VTT_OUT_RIGHT
*
100 Ohm
Dummy
+/-1%
10V, Y5V, +80%/-20%
*
C342
220pF
50V, NPO, +/-5%
12V_SYS
R342
*
*R388
C372
1uF
Dummy
CPU_GTLREF1
10
Dummy
100 Ohm
Dummy
+/-1%
10V, Y5V, +80%/-20%
Dummy
*
2N7002
G
R440
23 CPU_GTLREF_CTRL1
1K B
Q47
MMBT3904-7-F
R422
1.3KOhm
+/-1%
E
Dummy
Q44
1K
ICH_GPIO60 is OD output
*
*
R386
*
R387
100 Ohm
+/-1%
*
CPU_GTLREF2_DIVIDER
*
C351
220pF
50V, NPO, +/-5%
C362
1uF
10V, Y5V, +80%/-20%
Dummy
R378
*
R380
100 Ohm
+/-1%
CPU_GTLREF2
10
*
C341
220pF
50V, NPO, +/-5%
Dummy
R411
*R430
3D3V_SYS
0 CPU_GTLREF2_DIVIDER
Q45
2N7002
1K
*R427
G
1K
R428
23 CPU_GTLREF_CTRL2
12V_SYS
1K B
Q46
MMBT3904-7-F
R423
576
+/-1%
E
10V, Y5V, +80%/-20%
CPU_GTLREF3
10
*
*
CPU_GTLREF3_DIVIDER
C371
1uF
R379
49.9
+/-1%
B
*
VTT_OUT_RIGHT
R389
57.6 Ohm
+/-1%
Old:
GP20(CPU_GTLREF_CTRL2) is used
as funcitonal strap.
1. The status is Low during Reset.
2. The status is High after Reset.
New:
ICH_GPIO32: Default GPO, Core Power
D
VTT_OUT_LEFT
R377
0
S
*
R340
0
C
*
*
B
0 CPU_GTLREF0_DIVIDER
Dummy
1K
*R439
C352
220pF
50V, NPO, +/-5%
R413
*R431
3D3V_SB
D
CPU_GTLREF1_DIVIDER
S
CPU_GTLREF0
10
Dummy
*R375
C361
1uF
Dummy
+/-1%
C
R341
Reserved for CPU_GTLREF Adjusting(Double check)
*R390
57.6 Ohm
Dummy
*
*
CPU_GTLREF0_DIVIDER
*
VTT_OUT_LEFT
GTLREF voltage should be 0.67*VTT
12 mils width, 15 mils spacing
divider should be within 1.5" of the GTLREF pin
0.22nF caps should be placed near CPU pin
place series resistor as close to divider
*
*
R376
57.6 Ohm
Dummy
+/-1%
A
A
FOXCONN PCEG
Title
LGA775 -1
Size
C
Date:
5
4
3
2
Document Number
Rev
A
G43M01S1
Sheet
Monday, August 11, 2008
1
9
of
41
5
4
3
2
1
VTT_OUT_RIGHT
Power team update
01/15/08
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
VID_SELECT
F28
G28
7 CK_200M_P_CPU
7 CK_200M_N_CPU
R381
23 CPU_SKTOCC#
24,29
0
dummy
AE8
G5
PECI
TP_CPU_AL8
TP_CPU_AL7
VCC_SENSE
VSS_SENSE
VCC_MB_REG
VSS_MB_REG
VCCP4
VSS186
TP17
TP20
TP42
TP_CPU_AL3
AL3
VRDSEL
MS_ID1
MS_ID0
C
Stuff it will only support
Conroe and future processor
CPU_BOOT
V1
W1
Y1
HCOMP0
HCOMP1
HCOMP2
HCOMP3
HCOMP4
PM_DPRSTP#
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
F29
G6
AH2
N5
AE6
D16
A20
E23
F23
V2
E7
D14
E6
D1
TP_CPU_F29
TP_CPU_G6
TP_CPU_AH2
TP_CPU_N5
TP_CPU_AE6
TP_CPU_D16
TP_CPU_A20
TP_CPU_E23
TP_CPU_F23
TP_CPU_V2
TP_CPU_E7
TP_CPU_D14
TP_CPU_E6
TP_CPU_D1
FC39
FC26
AA2
E29
TP_CPU_AA2
TP_CPU_E29
FC23
FC22
FC21
FC20
A24
J3
F6
E5
TP_CPU_A24
TP_CPU_J3
TP_CPU_F6
TP_CPU_E5
BOOTSELECT
*R310
4 OF 7
TCK
TDI
TDO
TMS
TRST#
AJ2
AJ1
AD2
AG2
AF2
AG3
BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#
AC2
DBR#
AK3
AJ3
ITPCLK0
ITPCLK1
G29
H30
G30
BSEL0
BSEL1
BSEL2
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
FC40
A29
B25
B29
B30
C29
A26
B27
C28
A25
A28
A27
C30
A30
C25
C26
C27
B26
D27
D28
D25
D26
B28
D29
D30
AM6
VTT_OUT_RIGHT
VTT_OUT_LEFT
VTT_SEL
AA1
J1
F27
TESTHI_M
A13
T1
G2
R1
J2
T2
Y3
AE3
B13
MSID1
MSID0
FORCEPHJ
DPSLP#
23
PM_SLP
12,29
FSB_VTT
U2D
AE1
AD1
AF1
AC1
AG1
HCOMP7
HCOMP8
CPU_PWRGD
R305
HBPM0J
HBPM1J
HBPM2J
HBPM3J
HBPM4J
HBPM5J
23
0
PROCHOTJ 23
THERMTRIPJ 24
7,23,32
FP_RSTJ
7,12
7,12
7,12
FSBSEL0
FSBSEL1
FSBSEL2
FP_RSTJ
PM_DPRSTP# 12,23
PSI#
8
TP4
TP22
TP40
TP30
TP23
TP12
TP10
TP7
TP8
TP48
TP19
TP13
TP28
TP49
FSBSEL0
FSBSEL1
FSBSEL2
VTT_OUT_RIGHT
*R352*R353
*R354 *
Dummy
62
62
62
C353
0.1uF dummy
16V, Y5V, +80%/-20%
D
* R167
0
TPEC_VCC
R370
R371
0
VTT_PWRGD
Dummy 0
VTT_OUT_RIGHT
VTT_OUT_LEFT
VTT_SEL
VTT_SEL
19
*
HTDO
HTDI
R181
R304
R339
R338
62
62
VTT_OUT_RIGHT
Double check???
2
MS_ID0
51 Ohm TESTHI_2_7
R350
R349
*
VTT_OUT_RIGHT
* *
HIERRJ
R374
62
HCPURSTJ
R372
130
+/-1%
dummy
FORCEPHJ
R357
130
+/-1%
dummy
PROCHOTJ
R309
49.9
+/-1%
dummy
PSI#
R313
49.9
+/-1%
dummy
HCOMP7
R373
680
VID_SELECT
1
* * *
62
L34
Dummy
L0805 10uH
HIERRJ
9
HCPURSTJ
8,9,12
R356
* *
R355
62
R344
100 Ohm
dummy
CPU_PWRGD
R343
51 Ohm
TESTHI_10
R345
51 Ohm
dummy
DPSLP#
R346
51 Ohm
TESTHI_M
R337
51 Ohm
dummy
PM_SLP
R347
51 Ohm
TESTHI_1
R303
49.9 dummy
+/-1%
49.9 dummy
+/-1%
HCOMP4
1
*
*******
HVSSA
R301
C202
1uF
10V, Y5V, +80%/-20%
Dummy
2
*
Notes:
1. Cap. should be within 1.5" mils of the VCCA and VSSA pins
2. VCCA route should be parallel and next to VSSA route to minimize loop area
3. VCCIOPLL route should be parallel and next to VSSA route to minimize loop area
3. Min. 12 mils trace from the filter to the processor pins
4. The inductors should be close to the cap.
R336
can be NC for supporting only Core2 Duo, Core2 Extreme,
Wolfdale and Yorkfield family processors (have on-die filter)
R369
0
Dummy
+/-5%
*
Q43
B Dummy
MMBT3904-7-F
0
dummy
VTT_PWRGD 8,19
C360
0.1uF
16V, Y5V, +80%/-20%
dummy
*
51 Ohm
VTT_OUT_RIGHT
VTT_OUT_LEFT
EC39
100uF
+/-20%
Dummy
100 Ohm
B
HVCCIOPLL
HVCCA
*
R368
Dummy
dummy
BOM Note:
1.Stuff R108 for 95W YORKFIELD support
2.Stuff R109 for 65W CONROE/WOLFDALE support
3.Empty Q6 for VTT tool test
4.Reserve R110 and R111 for CPU support before CONROE
HBR0J
**
2
R311
2
1
FSB_VTT
*R351
1K
R308 Dummy
R348
Dummy
51 Ohm
PLL Supply Filter
dummy
E
MS_ID1
placed near pin D23, within 500 mils
0
C
R166
*
51 Ohm TESTHI_0
*
* *
1
*
R165
C206
10nF
25V, X7R, +/-10%
L35 Dummy
L0805 10uH
C343
0.1uF
16V, X7R, +/-10%
dummy
*R312 *R317
10V, Y5V, +80%/-20%
B
*
C
HVCCPLL
*
C345
0.1uF
HTCK
FSB_VTT
*
*
HTRSTJ
1K dummy
1K dummy
51 Ohm
1K dummy
1D5V_ICH
C205
10uF
C344
0.1uF
HTMS
TP37
TP3
Socket-IntelPrescottCPU
0
VTT_OUT_LEFT
8,23
Socket-IntelPrescottCPU
51 Ohm
R164
8,19
VTT_OUT_RIGHT
P_VRM_GD
16V, X7R, +/-10%
8 P_VCC_SENSE
8 P_VSS_SENSE
0 dummy
0 dummy
HTCK
HTDI
HTDO
HTMS
HTRSTJ
16V, X7R, +/-10%
THERMDA
THERMDC
R244
R245
If not used, pull up through 51 to 1k ohm
to vtt_out_right or ground respectively,i.e
reserved the termination circuit
TESTHI_2_7
FORCEPHJ
CPU_PWRGD
PROCHOTJ
H_THERMTRIPJ
PECI
AN3
AN4
AN5
AN6
AL8
AL7
THERMDA
THERMDC
TESTHI_0
TESTHI_1
N1
AL2
M2
VID0
PWRGOOD
VID1
PROCHOT#
VID2
THERMTRIP#
VID3
VID4
COMP0
VID5
COMP1
VID6
COMP2
VID7
COMP3
VID_SELECT
FC3
DPRSTP#
BCLK0
FC17
BCLK1
FC18
COMP8
SKTOCC#
AL1
AK1
**
29
29
AM2
AL5
AM3
AL6
AK4
AL4
AM5
AM7
AN7
F26
W3
F25
G25
G27
G26
G24
F24
AK6
P1
L2
W2
U1
*
8
8
8
8
8
8
8
8
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
VCCA
VSSA
VCCIOPLL
VCC_PLL
3 OF 7
TESTHI_0
TESTHI_1
TESTHI_2
TESTHI_3
TESTHI_4
TESTHI_5
TESTHI_6
TESTHI_7
FC8
DPSLP#
SLP#
TDI_M
TDO_M
*
dummy
dummy
dummy
dummy
dummy
dummy
dummy
dummy
A23
B23
C23
D23
SMI#
A20M#
FERR#/PBE#
LINT0
LINT1
IGNNE#
STPCLK#
**
680
680
680
680
680
680
680
680
*
R408
R407
R406
R405
R404
R403
R402
R401
HVCCA
HVSSA
HVCCIOPLL
HVCCPLL
********
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
D
P2
K3
R3
K1
L1
N2
M3
SMIJ
A20MJ
FERRJ
INTR
NMI
IGNNEJ
STPCLKJ
****
2
4
6
8
RN28
680
+/-5%
5
7
* 13
5
7
* 13
RN29
680
+/-5%
2
4
6
8
U2C
24
24
24
24
24
24
24
VTT_OUT_LEFT
51 Ohm
HBPM5J
51 Ohm
HBPM4J
*R412 *R409*R391 *R385
9,12
51 Ohm 51 Ohm51 Ohm
RN27
*1
3
5
7
TESTHI_10
9
HBPM3J
HBPM2J
HBPM0J
HBPM1J
2
4
6
8
51
+/-5%
RN26
1 Dummy
3
5
7
*
2
4
6
8
51 Ohm
BPMB3J
BPMB2J
BPMB0J
BPMB1J
BPMB3J
BPMB2J
BPMB0J
BPMB1J
9
9
9
9
0
+/-5%
Reserve for Kentsfield CPU support
PM_DPRSTP#
A
*****
A
R228
R307
R302
R306
R219
49.9
+/-1%
49.9
+/-1%
49.9
+/-1%
49.9
+/-1%
24.9
+/-1%
HCOMP0
HCOMP1
HCOMP2
FOXCONN PCEG
HCOMP3
HCOMP8
Title
LGA775 -2
Size
C
Date:
5
4
3
2
Document Number
Rev
A
G43M01S1
Sheet
Monday, August 11, 2008
1
10
of
41
5
4
VCCP
VCCP
U2E
AG22
K29
AM26
AE12
AE11
W23
W24
W25
T25
Y28
AL18
AC25
W30
Y30
AN14
AD28
Y26
AC29
M29
U24
J23
AC27
AM18
AM19
AB8
AC26
J8
J28
T30
AM9
AF15
AC8
AE14
N23
W29
U29
AC24
AC23
Y23
AN26
AN25
AN11
AN18
Y27
Y25
AD24
AE23
AE22
AN19
V8
K8
AE21
AM30
AE19
AC30
AE15
M30
K27
M24
AN21
T8
AC28
N25
AE18
W26
AD25
M8
N30
AD26
AJ26
AM29
M25
M26
L8
U25
Y8
AJ12
AD27
U23
M23
AG29
N27
AM22
U28
K28
U8
AK18
AD8
K24
AH28
AH21
D
C
B
VCCP1
VCCP2
VCCP3
VCCP5
VCCP6
VCCP7
VCCP8
VCCP9
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16
VCCP17
VCCP18
VCCP19
VCCP20
VCCP21
VCCP22
VCCP23
VCCP24
VCCP25
VCCP26
VCCP27
VCCP28
VCCP29
VCCP30
VCCP31
VCCP32
VCCP33
VCCP34
VCCP35
VCCP36
VCCP37
VCCP38
VCCP39
VCCP40
VCCP41
VCCP42
VCCP43
VCCP44
VCCP45
VCCP46
VCCP47
VCCP48
VCCP49
VCCP50
VCCP51
VCCP52
VCCP53
VCCP54
VCCP55
VCCP56
VCCP57
VCCP58
VCCP59
VCCP60
VCCP61
VCCP62
VCCP63
VCCP64
VCCP65
VCCP66
VCCP67
VCCP68
VCCP69
VCCP70
VCCP71
VCCP72
VCCP73
VCCP74
VCCP75
VCCP76
VCCP77
VCCP78
VCCP79
VCCP80
VCCP81
VCCP82
VCCP83
VCCP84
VCCP85
VCCP86
VCCP87
VCCP88
VCCP89
VCCP90
VCCP91
VCCP92
3
1
VCCP
U2F
5 OF 7
VCCP93
VCCP94
VCCP95
VCCP96
VCCP97
VCCP98
VCCP99
VCCP100
VCCP101
VCCP102
VCCP103
VCCP104
VCCP105
VCCP106
VCCP107
VCCP108
VCCP109
VCCP110
VCCP111
VCCP112
VCCP113
VCCP114
VCCP115
VCCP116
VCCP117
VCCP118
VCCP119
VCCP120
VCCP121
VCCP122
VCCP123
VCCP124
VCCP125
VCCP126
VCCP127
VCCP128
VCCP129
VCCP130
VCCP131
VCCP132
VCCP133
VCCP134
VCCP135
VCCP136
VCCP137
VCCP138
VCCP139
VCCP140
VCCP141
VCCP142
VCCP143
VCCP144
VCCP145
VCCP146
VCCP147
VCCP148
VCCP149
VCCP150
VCCP151
VCCP152
VCCP153
VCCP154
VCCP155
VCCP156
VCCP157
VCCP158
VCCP159
VCCP160
VCCP161
VCCP162
VCCP163
VCCP164
VCCP165
VCCP166
VCCP167
VCCP168
VCCP169
VCCP170
VCCP171
VCCP172
VCCP173
VCCP174
VCCP175
VCCP176
VCCP177
VCCP178
VCCP179
VCCP180
VCCP181
VCCP182
VCCP183
VCCP184
2
AK12
AH22
T29
AM14
AM25
AE9
Y29
AK25
AK19
AG15
J22
T24
AG21
AM21
J25
U30
AL21
AG25
AJ18
J19
AH30
J15
AG12
AJ22
J20
AH18
AH26
W27
AL25
AN8
AH14
U27
T23
R8
AK22
AN29
AG11
AK26
J10
AJ15
AG26
AN9
AH15
AF18
AL15
J26
J18
J21
AG27
AK15
AF11
AD23
AM15
AF8
AK21
AG30
AJ21
AM11
AL11
AJ11
K30
AL14
AN30
AH25
AL12
AJ9
AK11
AG14
N29
AL30
AJ25
AH9
J29
J11
K25
P8
K23
AL19
AM8
T26
N28
AH12
AL22
AN15
AJ8
U26
AJ19
T27
AK8
AN12
AG9
N26
AF9
AF22
AH11
AJ14
AH19
AH29
AH27
AG28
AL26
AM12
J24
J13
T28
W28
J12
J27
AG19
AL9
AD30
AF21
Y24
AK14
J9
M27
AF14
J30
AG18
AA8
AG8
AL29
AD29
W8
AH8
N24
AN22
J14
K26
AF19
N8
AF12
M28
AK9
VCCP185
VCCP186
VCCP187
VCCP188
VCCP189
VCCP190
VCCP191
VCCP192
VCCP193
VCCP194
VCCP195
VCCP196
VCCP197
VCCP198
VCCP199
VCCP200
VCCP201
VCCP202
VCCP203
VCCP204
VCCP205
VCCP206
VCCP207
VCCP208
VCCP209
VCCP210
VCCP211
VCCP212
VCCP213
VCCP214
VCCP215
VCCP216
VCCP217
VCCP218
VCCP219
VCCP220
VCCP221
VCCP222
VCCP223
VCCP224
VCCP225
VCCP226
C10
D12
C24
K2
C22
AN1
B14
K7
AE16
B11
AL10
AK23
H12
AF7
AK7
H7
E14
L28
Y5
E11
AL16
AL24
AK13
D21
AL20
D18
AN2
AK16
AK20
AM27
AM1
AL13
AL17
C19
E28
AH7
AK30
D24
VSS1
VSS2
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
U2G
6 OF 7
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
AL23
A12
L25
J7
AE28
AE29
K5
J4
AE30
AN20
AF10
AE24
AM24
AN23
H9
H8
H13
AC6
AC7
AH6
C16
AM16
AE25
AE27
AJ28
AJ7
F19
AH13
AD7
AH16
AK17
E17
AH17
AH20
AE5
AH23
AE7
AM13
AH24
AJ30
AJ10
AF3
AK5
AJ16
AF6
AK29
AJ17
F22
AH3
AK10
AM10
F16
AJ23
F13
AG7
F10
L26
AD4
H11
L24
L23
AM23
A15
AH10
B24
L3
H27
A21
AE2
AJ29
AK27
AK28
B20
AM20
H26
B17
H25
H24
AA3
AA7
H23
AA6
H10
H22
H21
H20
H19
H18
AB7
H17
AJ24
AM17
AC3
H14
P28
V6
AK2
P27
P26
AM28
AJ13
W4
P25
AJ20
W7
P23
AG13
AG16
AG17
C7
Y2
L30
L29
D15
AL27
Y7
L27
AA29
N6
N7
AA28
AN13
AA27
AA26
P4
AA25
AA24
P7
E26
V30
R2
V29
V28
R5
V27
R7
E20
AN10
V25
T3
V24
V23
T6
E25
R29
R28
R27
R26
R25
U7
R24
R23
P30
V3
P29
AF16
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS187
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
7 OF 7
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
AE10
AF13
H6
A18
A2
E2
D9
C4
A6
D6
D5
A9
D3
B1
B5
B8
AJ4
AE26
AH1
V7
C13
AK24
AB30
L6
L7
AB29
M1
AB28
E8
AG20
AN17
AB27
AB26
AN16
M7
AB25
AB24
AB23
N3
AA30
F4
AG10
AE13
AF30
H28
F7
AF29
AF28
AF27
AF26
AF25
AN28
AN27
AF24
AF23
AG24
AF17
AN24
H3
P24
AE20
AE17
E27
T7
R30
AJ27
AB1
AM4
V26
AA23
AL28
AF20
AG23
D
C
Socket-IntelPrescottCPU
B
U16_RM
Socket-IntelPrescottCPU
CPU RM
Socket-IntelPrescottCPU
U16_1
U16_2
U16_3
U16_4
A
A
FOXCONN PCEG
Title
LGA775 -3
Size
C
Date:
5
4
3
2
Document Number
Rev
A
G43M01S1
Sheet
Monday, August 11, 2008
1
11
of
41
4
3
2
Concurrent SDVO and PCI Express:
0 = Only SDVO or PCI Express is operational.
1 = Both SDVO and PCI Express are operating
FSB_REQB_0
FSB_REQB_1
FSB_REQB_2
FSB_REQB_3
FSB_REQB_4
J40
T39
FSB_ADSTBB_0
FSB_ADSTBB_1
HDSTBPJ0
HDSTBNJ0
HDBIJ0
HDSTBPJ1
HDSTBNJ1
HDBIJ1
HDSTBPJ2
HDSTBNJ2
HDBIJ2
HDSTBPJ3
HDSTBNJ3
HDBIJ3
9
9
9
9
9
9
9
9,10
9
9
9
9
9
9
8,9,10
HADSJ
HTRDYJ
HDRDYJ
HDEFERJ
HITMJ
HITJ
HLOCKJ
HBR0J
HBNRJ
HBPRIJ
HDBSYJ
HRSJ0
HRSJ1
HRSJ2
HCPURSTJ
HDBIJ0
HDBIJ1
HDBIJ2
HDBIJ3
TP39
TP_MCH_N25
C39
B39
B40
K31
J31
F33
J25
K25
F26
C32
D32
D30
FSB_DSTBPB_0
FSB_DSTBNB_0
FSB_DINVB_0
FSB_DSTBPB_1
FSB_DSTBNB_1
FSB_DINVB_1
FSB_DSTBPB_2
FSB_DSTBNB_2
FSB_DINVB_2
FSB_DSTBPB_3
FSB_DSTBNB_3
FSB_DINVB_3
J42
L40
J43
G44
K44
H45
H40
L42
J44
H37
H42
G43
L44
G42
D27
FSB_ADSB
FSB_TRDYB
FSB_DRDYB
FSB_DEFERB
FSB_HITMB
FSB_HITB
FSB_LOCKB
FSB_BREQ0B
FSB_BNRB
FSB_BPRIB
FSB_DBSYB
FSB_RSB_0
FSB_RSB_1
FSB_RSB_2
FSB_CPURSTB
N25
RSVD_3
FSB_SWING
FSB_RCOMP
B24
A23
FSB_DVREF
FSB_ACCVREF
C22
B23
HPL_CLKINP
HPL_CLKINN
P29
P30
23
23
23
23
23
23
23
23
F6
G7
H6
G4
J6
J7
L6
L7
N9
N10
N7
N6
R7
R6
R9
R10
U10
U9
U6
U7
AA9
AA10
R4
P4
AA7
AA6
AB10
AB9
AB3
AA2
AD10
AD11
DMI_RXP0
DMI_RXN0
DMI_RXP1
DMI_RXN1
DMI_RXP2
DMI_RXN2
DMI_RXP3
DMI_RXN3
DMI_RXP0
DMI_RXN0
DMI_RXP1
DMI_RXN1
DMI_RXP2
DMI_RXN2
DMI_RXP3
DMI_RXN3
AD7
AD8
AE9
AE10
AE6
AE7
AF9
AF8
D9
E9
7 CK_PE_100M_P_GMCH
7 CK_PE_100M_N_GMCH
21,22 SDVO_CTRLDATA
21,22 SDVO_CTRLCLK
TP55
TP54
R207
R202
0
0
J13
G13
TP_MCH_AB13 AB13
TP_MCH_AD13 AD13
PEG_RXP_0
PEG_RXN_0
PEG_RXP_1
PEG_RXN_1
PEG_RXP_2
PEG_RXN_2
PEG_RXP_3
PEG_RXN_3
PEG_RXP_4
PEG_RXN_4
PEG_RXP_5
PEG_RXN_5
PEG_RXP_6
PEG_RXN_6
PEG_RXP_7
PEG_RXN_7
PEG_RXP_8
PEG_RXN_8
PEG_RXP_9
PEG_RXN_9
PEG_RXP_10
PEG_RXN_10
PEG_RXP_11
PEG_RXN_11
PEG_RXP_12
PEG_RXN_12
PEG_RXP_13
PEG_RXN_13
PEG_RXP_14
PEG_RXN_14
PEG_RXP_15
PEG_RXN_15
DMI_RXP_0
DMI_RXN_0
DMI_RXP_1
DMI_RXN_1
DMI_RXP_2
DMI_RXN_2
DMI_RXP_3
DMI_RXN_3
EXP_CLKP
EXP_CLKN
PEG_TXP_0
PEG_TXN_0
PEG_TXP_1
PEG_TXN_1
PEG_TXP_2
PEG_TXN_2
PEG_TXP_3
PEG_TXN_3
PEG_TXP_4
PEG_TXN_4
PEG_TXP_5
PEG_TXN_5
PEG_TXP_6
PEG_TXN_6
PEG_TXP_7
PEG_TXN_7
PEG_TXP_8
PEG_TXN_8
PEG_TXP_9
PEG_TXN_9
PEG_TXP_10
PEG_TXN_10
PEG_TXP_11
PEG_TXN_11
PEG_TXP_12
PEG_TXN_12
PEG_TXP_13
PEG_TXN_13
PEG_TXP_14
PEG_TXN_14
PEG_TXP_15
PEG_TXN_15
DMI_TXP_0
DMI_TXN_0
DMI_TXP_1
DMI_TXN_1
DMI_TXP_2
DMI_TXN_2
DMI_TXP_3
DMI_TXN_3
EXP_RCOMPO
EXP_COMPI
EXP_ICOMPO
SDVO_CTRLDATA
SDVO_CTRLCLK
EXP_RBIAS
C11
B11
A10
B9
C9
D8
B8
C7
B7
B6
B3
B4
D2
C2
H2
G2
J2
K2
K1
L2
P2
M2
T2
R1
U2
V2
W4
V3
AA4
Y4
AC1
AB2
EXP_TXP0
EXP_TXN0
EXP_TXP1
EXP_TXN1
EXP_TXP2
EXP_TXN2
EXP_TXP3
EXP_TXN3
EXP_TXP4
EXP_TXN4
EXP_TXP5
EXP_TXN5
EXP_TXP6
EXP_TXN6
EXP_TXP7
EXP_TXN7
EXP_TXP8
EXP_TXN8
EXP_TXP9
EXP_TXN9
EXP_TXP10
EXP_TXN10
EXP_TXP11
EXP_TXN11
EXP_TXP12
EXP_TXN12
EXP_TXP13
EXP_TXN13
EXP_TXP14
EXP_TXN14
EXP_TXP15
EXP_TXN15
EXP_TXP0
EXP_TXN0
EXP_TXP1
EXP_TXN1
EXP_TXP2
EXP_TXN2
EXP_TXP3
EXP_TXN3
EXP_TXP4
EXP_TXN4
EXP_TXP5
EXP_TXN5
EXP_TXP6
EXP_TXN6
EXP_TXP7
EXP_TXN7
EXP_TXP8
EXP_TXN8
EXP_TXP9
EXP_TXN9
EXP_TXP10
EXP_TXN10
EXP_TXP11
EXP_TXN11
EXP_TXP12
EXP_TXN12
EXP_TXP13
EXP_TXN13
EXP_TXP14
EXP_TXN14
EXP_TXP15
EXP_TXN15
AC2
AD2
AD4
AE4
AE2
AF2
AF4
AG4
DMI_TXP0
DMI_TXN0
DMI_TXP1
DMI_TXN1
DMI_TXP2
DMI_TXN2
DMI_TXP3
DMI_TXN3
Y7
Y8
Y6
GMCH_EXP_COMP R246
AG1
GMCH_EXP_RBIAS R276
DMI_TXP0
DMI_TXN0
DMI_TXP1
DMI_TXN1
DMI_TXP2
DMI_TXN2
DMI_TXP3
DMI_TXN3
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
TP44
Enable
TLS
R198
1K
*
TP21
TP27
CL_DATA
CL_CLK
24
CL_RST
*R291
10K
TP59
TP60
TP57
TP58
TP38
TP47
TP45
TP50
TP51
TP52
1D1V_MCH TP16
TP18
TP61
49.9
TP62
+/-1%
TP41
RSVD_1
RSVD_2
M17
J17
G20
J16
M16
J15
J20
F20
TP_MCH_J15
TP_MCH_J20
TP_MCH_F20
24
24
23
23
23
23
23
23
23
23
TP_MCH_M17
TLS
TP_MCH_G20
TP_MCH_J16
CL_DATA
AY4
CL_CLK
AY2
CL_VREF_MCH AN13
CL_RST
AW2
PWRGD_3V
AN8
TP_MCH_AR7
AR7
TP_MCH_AN10 AN10
TP_MCH_AN11 AN11
TP_MCH_AN9
AN9
R31
TP_MCH_R32
R32
TP_MCH_U30
U30
U31
R15
TP_MCH_R14
R14
TP_MCH_T15
T15
TP_MCH_T14
T14
TP_MCH_AB15 AB15
TP_MCH_A45
A45
TP_MCH_B2
B2
TP_MCH_BE1
BE1
TP_MCH_BE45 BE45
TP_MCH_L13
L13
TP_MCH_L11
L11
BSEL0
BSEL1
BSEL2
ALLZTEST
XORTEST
RSVD_29
EXP_SLR
RSVD_7
EXP_SM
ITPM_ENABLE
D14
C14
CRT_HSYNC
CRT_VSYNC
CRT_RED
CRT_GREEN
CRT_BLUE
CRT_IRTN
B18
D18
C18
F13
CRT_DDC_DATA
CRT_DDC_CLK
L15
M15
RSVD_8
CEN
BSCANTEST
RSVD_10
RSVD_11
RSVD_12
RSVD_13
DUALX8_ENABLE
DAC_IREF
B15
DPL_REFCLKINP
DPL_REFCLKINN
E15
D15
CL_DATA
CL_CLK
CL_VREF
CL_RSTB
CL_PWROK
+/ -1%
+/ -1%
CK_96M_P_GMCH 7
CK_96M_N_GMCH 7
CK_REFSSCLK_P_GMCH
CK_REFSSCLK_N_GMCH
PLTRSTJ
PWRGD_3V
ICH_SYNCJ
PWRGD_3V
ICH_SYNCJ
stuff for NO HDMI
DDPC_CTRLCLK
DDPC_CTRLDATA
J11
F11
DDPC_CTRLCLK
DDPC_CTRLDATA
SLPB
DPRSTPB
P42
P43
7
7
23,29,34
19,22,23,24,29
23
3D3V_SYS
*R218 *R216
2.2K
dummy
2.2K
dummy
DDPC_CTRLCLK 22
DDPC_CTRLDATA 22
PM_SLP
PM_DPRSTP#
AN17
A44
BD1
BD45
BE2
BE44
B14
B45
AK15
AD42
AN16
W30
AW44
R42
U32
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
D
+/ -1%
Placed close to
GMCH within
250 mils
10,29
10,23
C
Del circuit for HDMI
Eaglelake-Q
HSWING
HRCOMP
Eaglelake-Q
CK_200M_P_GMCH 7
CK_200M_N_GMCH 7
3D3V_SYS
Del Non-Graphic sku pull down components.
3D3V_SYS
*R204
2.2K
FSB_VTT
2.2K
DDCA_CLK
FSB_VTT
DDCA_DATA
*R209
C237
0.1uF
16V, Y5V, +80%/-20%
*
MCH_GTLREF
49.9
+/-1%
*R200
C233
1uF
*
100 Ohm
+/-1%
10V, Y5V, +80%/-20%
HSWING voltage should be 0.25*FSB_VTT
10 mils width, 10 mils spacing
max. 3 inches long
R237
C236
220pF
50V, NPO, +/-5%
dummy
GTLREF voltage should be 0.67*VTT = 0.75V
12 mils width, 15 mils spacing
divider should be within 1.5" of the GTLREF pin
220pF caps should be placed near MCH pin
place series resistor as close to divider
Resistor and Capacitor next to each other
7,10
FSBSEL0
7,10
FSBSEL1
7,10
FSBSEL2
TP_MCH_L13
22
PEG_PINB4
R224
10K
R195
10K
1K
dummy
TP_MCH_K16
1K
dummy
TP_MCH_K16
R212
1K
dummy
TP_MCH_J15
R190
1K
dummy
TP_MCH_J20
R188
1K
dummy
TP_MCH_F20
R196
H_FSBSEL0
H_FSBSEL1
H_FSBSEL1
7
ATX: dummy
BTX: pop
10K
H_FSBSEL2
H_FSBSEL2
R205
10K
dummy
DAC_REFSET
R194
R192
R203
1.02KOhm
+/-1%
*
HSWING
* *
R199
49.9
+/-1%
placed close to GMCH within 500 mils
4 mils width
6 mils spacing to static signals
12 mils spacing to toppling signals
*
*
*
R227
B
3D3V_SYS
57.6 Ohm
+/-1%
301
+/-1%
*
*R217
+/-1%
CK_96M_P_GMCH
CK_96M_N_GMCH
AU4
AV4
AU2
AV1
AU3
680 Ohm
+/-1%
21
21
DAC_REFSET
HDA_BCLK
HDA_RSTB
HDA_SDI
HDA_SDO
HDA_SYNC
RSVD_14
RSVD_15
RSVD_16
RSVD_17
RSVD_18
RSVD_19
RSVD_20
RSVD_21
RSVD_22
RSVD_23
RSVD_24
RSVD_25
RSVD_26
RSVD_27
RSVD_28
21
21
21
*R239
*R238
*R236
150
150
150
DDCA_DATA
DDCA_CLK
AN6
AR4
K15
RSTINB
PWROK
ICH_SYNCB
JTAG_TDI
JTAG_TDO
JTAG_TCK
JTAG_TMS
RED
GREEN
BLUE
CK_REFSSCLK_P_GMCH
CK_REFSSCLK_N_GMCH
G8
G9
DPL_REFSSCLKINP
DPL_REFSSCLKINN
*R210
*R214 *
100 Ohm
21
21
MCH_GTLREF
Eaglelake-Q
B
3V_HSYNC
3V_VSYNC
Follow up DG1.2
*
9
9
9
9
9
9
9
9
9
9
9
9
EXP_RXP0
EXP_RXN0
EXP_RXP1
EXP_RXN1
EXP_RXP2
EXP_RXN2
EXP_RXP3
EXP_RXN3
EXP_RXP4
EXP_RXN4
EXP_RXP5
EXP_RXN5
EXP_RXP6
EXP_RXN6
EXP_RXP7
EXP_RXN7
EXP_RXP8
EXP_RXN8
EXP_RXP9
EXP_RXN9
EXP_RXP10
EXP_RXN10
EXP_RXP11
EXP_RXN11
EXP_RXP12
EXP_RXN12
EXP_RXP13
EXP_RXN13
EXP_RXP14
EXP_RXN14
EXP_RXP15
EXP_RXN15
EXP_RXP0
EXP_RXN0
EXP_RXP1
EXP_RXN1
EXP_RXP2
EXP_RXN2
EXP_RXP3
EXP_RXN3
EXP_RXP4
EXP_RXN4
EXP_RXP5
EXP_RXN5
EXP_RXP6
EXP_RXN6
EXP_RXP7
EXP_RXN7
EXP_RXP8
EXP_RXN8
EXP_RXP9
EXP_RXN9
EXP_RXP10
EXP_RXN10
EXP_RXP11
EXP_RXN11
EXP_RXP12
EXP_RXN12
EXP_RXP13
EXP_RXN13
EXP_RXP14
EXP_RXN14
EXP_RXP15
EXP_RXN15
F17
G16
P15
M20
N17
K16
F15
G15
H17
L17
*
C
HADSTBJ0
HADSTBJ1
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
TP29
5 OF 10
U46E
H_FSBSEL0
H_FSBSEL1
H_FSBSEL2
TP_ALLZTEST
TP_XORTEST
TP_MCH_K16
EXP_SLR
TP_MCH_G15
EXP_SM
ITPM_EN
* * *
9
9
1 OF 10
U46A
PCIE
G38
K35
J39
C43
G39
9
TLS confidentiality enable:
1 = Enable TLS
0 = Disable TLS
Note:
For platforms that do not support Intel
AMT,no action is needed.
update: Ref spec update 1.01
TP35
011808
TP33
HDJ0
HDJ1
HDJ2
HDJ3
HDJ4
HDJ5
HDJ6
HDJ7
HDJ8
HDJ9
HDJ10
HDJ11
HDJ12
HDJ13
HDJ14
HDJ15
HDJ16
HDJ17
HDJ18
HDJ19
HDJ20
HDJ21
HDJ22
HDJ23
HDJ24
HDJ25
HDJ26
HDJ27
HDJ28
HDJ29
HDJ30
HDJ31
HDJ32
HDJ33
HDJ34
HDJ35
HDJ36
HDJ37
HDJ38
HDJ39
HDJ40
HDJ41
HDJ42
HDJ43
HDJ44
HDJ45
HDJ46
HDJ47
HDJ48
HDJ49
HDJ50
HDJ51
HDJ52
HDJ53
HDJ54
HDJ55
HDJ56
HDJ57
HDJ58
HDJ59
HDJ60
HDJ61
HDJ62
HDJ63
*
HREQJ[4..0]
F44
C44
D44
C41
E43
B43
D40
B42
B38
F38
A38
B37
D38
C37
D37
B36
E37
J35
H35
F37
G37
J33
L33
G33
L31
M31
M30
J30
G31
K30
M29
G30
J29
F29
H29
L25
K26
L29
J26
M26
H26
F25
F24
G25
H24
L24
J24
N24
C28
B31
F35
C35
B35
D35
D31
A34
B32
F31
D28
A29
C30
B30
E27
B28
*
9
FSB_DB_0
FSB_DB_1
FSB_DB_2
FSB_DB_3
FSB_DB_4
FSB_DB_5
FSB_DB_6
FSB_DB_7
FSB_DB_8
FSB_DB_9
FSB_DB_10
FSB_DB_11
FSB_DB_12
FSB_DB_13
FSB_DB_14
FSB_DB_15
FSB_DB_16
FSB_DB_17
FSB_DB_18
FSB_DB_19
FSB_DB_20
FSB_DB_21
FSB_DB_22
FSB_DB_23
FSB_DB_24
FSB_DB_25
FSB_DB_26
FSB_DB_27
FSB_DB_28
FSB_DB_29
FSB_DB_30
FSB_DB_31
FSB_DB_32
FSB_DB_33
FSB_DB_34
FSB_DB_35
FSB_DB_36
FSB_DB_37
FSB_DB_38
FSB_DB_39
FSB_DB_40
FSB_DB_41
FSB_DB_42
FSB_DB_43
FSB_DB_44
FSB_DB_45
FSB_DB_46
FSB_DB_47
FSB_DB_48
FSB_DB_49
FSB_DB_50
FSB_DB_51
FSB_DB_52
FSB_DB_53
FSB_DB_54
FSB_DB_55
FSB_DB_56
FSB_DB_57
FSB_DB_58
FSB_DB_59
FSB_DB_60
FSB_DB_61
FSB_DB_62
FSB_DB_63
DMI
HREQJ0
HREQJ1
HREQJ2
HREQJ3
HREQJ4
D
FSB_AB_3
FSB_AB_4
FSB_AB_5
FSB_AB_6
FSB_AB_7
FSB_AB_8
FSB_AB_9
FSB_AB_10
FSB_AB_11
FSB_AB_12
FSB_AB_13
FSB_AB_14
FSB_AB_15
FSB_AB_16
FSB_AB_17
FSB_AB_18
FSB_AB_19
FSB_AB_20
FSB_AB_21
FSB_AB_22
FSB_AB_23
FSB_AB_24
FSB_AB_25
FSB_AB_26
FSB_AB_27
FSB_AB_28
FSB_AB_29
FSB_AB_30
FSB_AB_31
FSB_AB_32
FSB_AB_33
FSB_AB_34
FSB_AB_35
**
L36
L37
J38
F40
H39
L38
L43
N39
N35
N37
J41
N40
M45
R35
T36
R36
R34
R37
R39
U38
T37
U34
U40
T34
Y36
U35
AA35
U37
Y37
Y34
Y38
AA37
AA36
HDJ[63..0]
2 OF 10
U46B
HAJ3
HAJ4
HAJ5
HAJ6
HAJ7
HAJ8
HAJ9
HAJ10
HAJ11
HAJ12
HAJ13
HAJ14
HAJ15
HAJ16
HAJ17
HAJ18
HAJ19
HAJ20
HAJ21
HAJ22
HAJ23
HAJ24
HAJ25
HAJ26
HAJ27
HAJ28
HAJ29
HAJ30
HAJ31
HAJ32
HAJ33
HAJ34
HAJ35
VGA
HDJ[63..0]
HAJ[35..3]
FSB
9
1
PCI Express* Static Lane Reversal:
0 = GMCH PCI Express lane numbers are reversed (BTX)
1 = Normal operation (ATX)
MISC
5
1K
dummy
EXP_SLR
3D3V_SYS
16.5
+/-1%
10 mils width, 7 mils spacing
max. 500 mils
5 on 5 mils in breakout, max 250 mils
R185
*
1D1V_MCH_CL
*R323
1K
*
R226
1K
Dummy
ITPM_EN
R197
Dummy
22
0.35V
EXP_PRSNT
*
HRCOMP
*
2x8 PEG port Bifurcation:
0 = 2x8 PCIe Ports Enabled
1 = 1x16 PCIe Port Enabled
R191
0
10K
EXP_SM
MCH Enable Strap
0: Enable TPM
1: Disable TPM
Update: Ref to spec update SWAT 080430
+/-1%
CL_VREF_MCH
A
*
*R322
464
+/-1%
A
C348
0.1uF
16V, Y5V, +80%/-20%
min. 4 mils width
10 mils spacing
5 mils min. for max. of 300 mils in breakout
Check DG1.2
useR2=464ohm?????
FOXCONN PCEG
Title
Eaglelake -GMCH -1
Size
C
Date:
5
4
3
2
Document Number
Rev
A
G43M01S1
Sheet
Monday, August 11, 2008
1
12
of
41
5
4
U46C
16,18 M_MAA_A[14..0]
M_MAA_A0
M_MAA_A1
M_MAA_A2
M_MAA_A3
M_MAA_A4
M_MAA_A5
M_MAA_A6
M_MAA_A7
M_MAA_A8
M_MAA_A9
M_MAA_A10
M_MAA_A11
M_MAA_A12
M_MAA_A13
M_MAA_A14
D
16,18 M_WE_AJ
16,18 M_CAS_AJ
16,18 M_RAS_AJ
M_BS_A0
M_BS_A1
M_BS_A2
16,18 M_BS_A[2..0]
16,18 M_SCS_A0J
16,18 M_SCS_A1J
16,18 M_SCKE_A[1..0]
16,18 M_ODT_A[1..0]
16
16
16
16
16
16
BC41
BC35
BB32
BC32
BD32
BB31
AY31
BA31
BD31
BD30
AW43
BC30
BB30
AM42
BD28
DDR_A_MA_0
DDR_A_MA_1
DDR_A_MA_2
DDR_A_MA_3
DDR_A_MA_4
DDR_A_MA_5
DDR_A_MA_6
DDR_A_MA_7
DDR_A_MA_8
DDR_A_MA_9
DDR_A_MA_10
DDR_A_MA_11
DDR_A_MA_12
DDR_A_MA_13
DDR_A_MA_14
AW42
AU42
AV42
DDR_A_WEB
DDR_A_CASB
DDR_A_RASB
AV45
AY44
BC28
DDR_A_BS_0
DDR_A_BS_1
DDR_A_BS_2
AU43
AR40
AU44
AM43
DDR_A_CSB_0
DDR_A_CSB_1
DDR_A_CSB_2
DDR_A_CSB_3
M_SCKE_A0
M_SCKE_A1
BB27
BD27
BA27
AY26
DDR_A_CKE_0
DDR_A_CKE_1
DDR_A_CKE_2
DDR_A_CKE_3
M_ODT_A0
M_ODT_A1
AR42
AM44
AR44
AL40
DDR_A_ODT_0
DDR_A_ODT_1
DDR_A_ODT_2
DDR_A_ODT_3
AY37
BA37
AW29
AY29
AU37
AV37
AU33
AT33
AT30
AR30
AW38
AY38
DDR_A_CK_0
DDR_A_CKB_0
DDR_A_CK_1
DDR_A_CKB_1
DDR_A_CK_2
DDR_A_CKB_2
DDR_A_CK_3
DDR_A_CKB_3
DDR_A_CK_4
DDR_A_CKB_4
DDR_A_CK_5
DDR_A_CKB_5
CK_M_200M_P_DDR0_A
CK_M_200M_N_DDR0_A
CK_M_200M_P_DDR1_A
CK_M_200M_N_DDR1_A
CK_M_200M_P_DDR2_A
CK_M_200M_N_DDR2_A
C
Note:
For a single DIMM per channel implementation,
the following second DIMM specific system memory
signals should be tested pointed.
CK/CKB[5:3] - DDR2 Clock Pairs
CK/CKB[3 and 5] - Channel A DDR3 Clock Pairs
CK/CKB[3 and 4] - Channel B DDR3 Clock Pairs
CSB[3:2]
CKE[3:2]
ODT[3:2]
B
DDR_A
3
2
3 OF 10
DDR_A_DQS_0
DDR_A_DQSB_0
DDR_A_DM_0
BC5
BD4
BC3
M_DQS_A0
M_DQS_AJ0
M_DQM_A0
DDR_A_DQ_0
DDR_A_DQ_1
DDR_A_DQ_2
DDR_A_DQ_3
DDR_A_DQ_4
DDR_A_DQ_5
DDR_A_DQ_6
DDR_A_DQ_7
BC2
BD3
BD7
BB7
BB2
BA3
BE6
BD6
M_DATA_A0
M_DATA_A1
M_DATA_A2
M_DATA_A3
M_DATA_A4
M_DATA_A5
M_DATA_A6
M_DATA_A7
DDR_A_DQS_1
DDR_A_DQSB_1
DDR_A_DM_1
BB9
BC9
BD9
M_DQS_A1
M_DQS_AJ1
M_DQM_A1
DDR_A_DQ_8
DDR_A_DQ_9
DDR_A_DQ_10
DDR_A_DQ_11
DDR_A_DQ_12
DDR_A_DQ_13
DDR_A_DQ_14
DDR_A_DQ_15
BB8
AY8
BD11
BB11
BC7
BE8
BD10
AY11
M_DATA_A8
M_DATA_A9
M_DATA_A10
M_DATA_A11
M_DATA_A12
M_DATA_A13
M_DATA_A14
M_DATA_A15
DDR_A_DQS_2
DDR_A_DQSB_2
DDR_A_DM_2
BD15
BB15
BD14
M_DQS_A2
M_DQS_AJ2
M_DQM_A2
DDR_A_DQ_16
DDR_A_DQ_17
DDR_A_DQ_18
DDR_A_DQ_19
DDR_A_DQ_20
DDR_A_DQ_21
DDR_A_DQ_22
DDR_A_DQ_23
BB14
BC14
BC16
BB16
BC11
BE12
BA15
BD16
M_DATA_A16
M_DATA_A17
M_DATA_A18
M_DATA_A19
M_DATA_A20
M_DATA_A21
M_DATA_A22
M_DATA_A23
DDR_A_DQS_3
DDR_A_DQSB_3
DDR_A_DM_3
AR22
AT22
AV22
M_DQS_A3
M_DQS_AJ3
M_DQM_A3
DDR_A_DQ_24
DDR_A_DQ_25
DDR_A_DQ_26
DDR_A_DQ_27
DDR_A_DQ_28
DDR_A_DQ_29
DDR_A_DQ_30
DDR_A_DQ_31
AW21
AY22
AV24
AY24
AU21
AT21
AR24
AU24
M_DATA_A24
M_DATA_A25
M_DATA_A26
M_DATA_A27
M_DATA_A28
M_DATA_A29
M_DATA_A30
M_DATA_A31
DDR_A_DQS_4
DDR_A_DQSB_4
DDR_A_DM_4
AH43
AH42
AK42
M_DQS_A4
M_DQS_AJ4
M_DQM_A4
DDR_A_DQ_32
DDR_A_DQ_33
DDR_A_DQ_34
DDR_A_DQ_35
DDR_A_DQ_36
DDR_A_DQ_37
DDR_A_DQ_38
DDR_A_DQ_39
AL41
AK43
AG42
AG44
AL42
AK44
AH44
AG41
M_DATA_A32
M_DATA_A33
M_DATA_A34
M_DATA_A35
M_DATA_A36
M_DATA_A37
M_DATA_A38
M_DATA_A39
DDR_A_DQS_5
DDR_A_DQSB_5
DDR_A_DM_5
AD43
AE42
AE45
M_DQS_A5
M_DQS_AJ5
M_DQM_A5
DDR_A_DQ_40
DDR_A_DQ_41
DDR_A_DQ_42
DDR_A_DQ_43
DDR_A_DQ_44
DDR_A_DQ_45
DDR_A_DQ_46
DDR_A_DQ_47
AF43
AF42
AC44
AC42
AF40
AF44
AD44
AC41
M_DATA_A40
M_DATA_A41
M_DATA_A42
M_DATA_A43
M_DATA_A44
M_DATA_A45
M_DATA_A46
M_DATA_A47
DDR_A_DQS_6
DDR_A_DQSB_6
DDR_A_DM_6
Y43
Y42
AA45
M_DQS_A6
M_DQS_AJ6
M_DQM_A6
DDR_A_DQ_48
DDR_A_DQ_49
DDR_A_DQ_50
DDR_A_DQ_51
DDR_A_DQ_52
DDR_A_DQ_53
DDR_A_DQ_54
DDR_A_DQ_55
AB43
AA42
W42
W41
AB42
AB44
Y44
Y40
M_DATA_A48
M_DATA_A49
M_DATA_A50
M_DATA_A51
M_DATA_A52
M_DATA_A53
M_DATA_A54
M_DATA_A55
DDR_A_DQS_7
DDR_A_DQSB_7
DDR_A_DM_7
T44
T43
T42
M_DQS_A7
M_DQS_AJ7
M_DQM_A7
DDR_A_DQ_56
DDR_A_DQ_57
DDR_A_DQ_58
DDR_A_DQ_59
DDR_A_DQ_60
DDR_A_DQ_61
DDR_A_DQ_62
DDR_A_DQ_63
V42
U45
R40
P44
V44
V43
R41
R44
M_DATA_A56
M_DATA_A57
M_DATA_A58
M_DATA_A59
M_DATA_A60
M_DATA_A61
M_DATA_A62
M_DATA_A63
M_DQS_A[7..0] 16
M_DQS_AJ[7..0] 16
M_DQM_A[7..0] 16
M_DATA_A[63..0] 16
17,18 M_MAA_B[14..0]
M_MAA_B0
M_MAA_B1
M_MAA_B2
M_MAA_B3
M_MAA_B4
M_MAA_B5
M_MAA_B6
M_MAA_B7
M_MAA_B8
M_MAA_B9
M_MAA_B10
M_MAA_B11
M_MAA_B12
M_MAA_B13
M_MAA_B14
M_DQS_A[7..0] 16
M_DQS_AJ[7..0] 16
M_DQM_A[7..0] 16
M_DATA_A[63..0] 16
17,18
17,18
17,18
17,18 M_BS_B[2..0]
BD24
BB23
BB24
BD23
BB22
BD22
BC22
BC20
BB20
BD20
BC26
BD19
BB19
BE38
BA19
DDR_B_MA_0
DDR_B_MA_1
DDR_B_MA_2
DDR_B_MA_3
DDR_B_MA_4
DDR_B_MA_5
DDR_B_MA_6
DDR_B_MA_7
DDR_B_MA_8
DDR_B_MA_9
DDR_B_MA_10
DDR_B_MA_11
DDR_B_MA_12
DDR_B_MA_13
DDR_B_MA_14
BD36
BC37
BD35
DDR_B_WEB
DDR_B_CASB
DDR_B_RASB
BD26
BB26
BD18
DDR_B_BS_0
DDR_B_BS_1
DDR_B_BS_2
BB35
BD39
BB37
BD40
DDR_B_CSB_0
DDR_B_CSB_1
DDR_B_CSB_2
DDR_B_CSB_3
M_SCKE_B0
M_SCKE_B1
BC18
AY20
BE17
BB18
DDR_B_CKE_0
DDR_B_CKE_1
DDR_B_CKE_2
DDR_B_CKE_3
M_ODT_B0
M_ODT_B1
BD37
BC39
BB38
BD42
DDR_B_ODT_0
DDR_B_ODT_1
DDR_B_ODT_2
DDR_B_ODT_3
AY33
AW33
AV31
AW31
AW35
AY35
AT31
AU31
AP31
AP30
AW37
AV35
DDR_B_CK_0
DDR_B_CKB_0
DDR_B_CK_1
DDR_B_CKB_1
DDR_B_CK_2
DDR_B_CKB_2
DDR_B_CK_3
DDR_B_CKB_3
DDR_B_CK_4
DDR_B_CKB_4
DDR_B_CK_5
DDR_B_CKB_5
AR43
BB40
AT44
AV40
AR6
BC24
DDR3_A_CSB1
DDR3_A_MA0
DDR3_A_WEB
DDR3_A_ODT3
DDR3_A_DRAM_PWROK
DDR3_DRAMRSTB
AN29
AN30
AJ33
AK33
RSVD_4
RSVD_5
RSVD_6
RSVD_7
M_WE_BJ
M_CAS_BJ
M_RAS_BJ
M_BS_B0
M_BS_B1
M_BS_B2
17,18 M_SCS_B0J
17,18 M_SCS_B1J
M_DQS_A[7..0] 16
M_DQS_AJ[7..0] 16
M_DQM_A[7..0] 16
M_DATA_A[63..0] 16
17,18 M_SCKE_B[1..0]
17,18 M_ODT_B[1..0]
M_DQS_A[7..0] 16
M_DQS_AJ[7..0] 16
M_DQM_A[7..0] 16
M_DATA_A[63..0] 16
17
17
17
17
17
17
CK_M_200M_P_DDR0_B
CK_M_200M_N_DDR0_B
CK_M_200M_P_DDR1_B
CK_M_200M_N_DDR1_B
CK_M_200M_P_DDR2_B
CK_M_200M_N_DDR2_B
M_DQS_A[7..0] 16
M_DQS_AJ[7..0] 16
M_DQM_A[7..0] 16
M_DATA_A[63..0] 16
R293
0
DDR3_DRAM_PWROK
*
M_DQS_A[7..0] 16
M_DQS_AJ[7..0] 16
M_DQM_A[7..0] 16
M_DATA_A[63..0] 16
M_DQS_A[7..0] 16
M_DQS_AJ[7..0] 16
M_DQM_A[7..0] 16
M_DATA_A[63..0] 16
MCH_DDR_VREF
BB44
DDR_VREF
MCH_DDR_RPD
MCH_DDR_RPU
MCH_DDR_SPD
MCH_DDR_SPU
AY42
BA43
BC43
BC44
DDR_RPD
DDR_RPU
DDR_SPD
DDR_SPU
M_DQS_A[7..0] 16
M_DQS_AJ[7..0] 16
M_DQM_A[7..0] 16
M_DATA_A[63..0] 16
1
4 OF 10
U46D
DDR_B
AW8
AW9
AY6
M_DQS_B0
M_DQS_BJ0
M_DQM_B0
DDR_B_DQ_0
DDR_B_DQ_1
DDR_B_DQ_2
DDR_B_DQ_3
DDR_B_DQ_4
DDR_B_DQ_5
DDR_B_DQ_6
DDR_B_DQ_7
AV7
AW4
BA9
AU11
AU7
AU8
AW7
AY9
M_DATA_B0
M_DATA_B1
M_DATA_B2
M_DATA_B3
M_DATA_B4
M_DATA_B5
M_DATA_B6
M_DATA_B7
DDR_B_DQS_1
DDR_B_DQSB_1
DDR_B_DM_1
AT15
AU15
AR15
M_DQS_B1
M_DQS_BJ1
M_DQM_B1
DDR_B_DQ_8
DDR_B_DQ_9
DDR_B_DQ_10
DDR_B_DQ_11
DDR_B_DQ_12
DDR_B_DQ_13
DDR_B_DQ_14
DDR_B_DQ_15
AY13
AP15
AW15
AT16
AU13
AW13
AP16
AU16
M_DATA_B8
M_DATA_B9
M_DATA_B10
M_DATA_B11
M_DATA_B12
M_DATA_B13
M_DATA_B14
M_DATA_B15
DDR_B_DQS_2
DDR_B_DQSB_2
DDR_B_DM_2
AR20
AR17
AU17
M_DQS_B2
M_DQS_BJ2
M_DQM_B2
DDR_B_DQ_16
DDR_B_DQ_17
DDR_B_DQ_18
DDR_B_DQ_19
DDR_B_DQ_20
DDR_B_DQ_21
DDR_B_DQ_22
DDR_B_DQ_23
AY17
AV17
AR21
AV20
AP17
AW16
AT20
AN20
M_DATA_B16
M_DATA_B17
M_DATA_B18
M_DATA_B19
M_DATA_B20
M_DATA_B21
M_DATA_B22
M_DATA_B23
DDR_B_DQS_3
DDR_B_DQSB_3
DDR_B_DM_3
AU26
AT26
AV25
M_DQS_B3
M_DQS_BJ3
M_DQM_B3
DDR_B_DQ_24
DDR_B_DQ_25
DDR_B_DQ_26
DDR_B_DQ_27
DDR_B_DQ_28
DDR_B_DQ_29
DDR_B_DQ_30
DDR_B_DQ_31
AT25
AV26
AU29
AV29
AW25
AR25
AP26
AR29
M_DATA_B24
M_DATA_B25
M_DATA_B26
M_DATA_B27
M_DATA_B28
M_DATA_B29
M_DATA_B30
M_DATA_B31
DDR_B_DQS_4
DDR_B_DQSB_4
DDR_B_DM_4
AR38
AR37
AU39
M_DQS_B4
M_DQS_BJ4
M_DQM_B4
DDR_B_DQ_32
DDR_B_DQ_33
DDR_B_DQ_34
DDR_B_DQ_35
DDR_B_DQ_36
DDR_B_DQ_37
DDR_B_DQ_38
DDR_B_DQ_39
AR36
AU38
AN35
AN37
AV39
AW39
AU40
AU41
M_DATA_B32
M_DATA_B33
M_DATA_B34
M_DATA_B35
M_DATA_B36
M_DATA_B37
M_DATA_B38
M_DATA_B39
DDR_B_DQS_5
DDR_B_DQSB_5
DDR_B_DM_5
AK34
AL34
AL37
M_DQS_B5
M_DQS_BJ5
M_DQM_B5
DDR_B_DQ_40
DDR_B_DQ_41
DDR_B_DQ_42
DDR_B_DQ_43
DDR_B_DQ_44
DDR_B_DQ_45
DDR_B_DQ_46
DDR_B_DQ_47
AL35
AL36
AK36
AJ34
AN39
AN40
AK37
AL39
M_DATA_B40
M_DATA_B41
M_DATA_B42
M_DATA_B43
M_DATA_B44
M_DATA_B45
M_DATA_B46
M_DATA_B47
DDR_B_DQS_6
DDR_B_DQSB_6
DDR_B_DM_6
AF37
AF36
AJ35
M_DQS_B6
M_DQS_BJ6
M_DQM_B6
DDR_B_DQ_48
DDR_B_DQ_49
DDR_B_DQ_50
DDR_B_DQ_51
DDR_B_DQ_52
DDR_B_DQ_53
DDR_B_DQ_54
DDR_B_DQ_55
AJ38
AJ37
AF38
AE37
AK40
AJ40
AF34
AE35
M_DATA_B48
M_DATA_B49
M_DATA_B50
M_DATA_B51
M_DATA_B52
M_DATA_B53
M_DATA_B54
M_DATA_B55
DDR_B_DQS_7
DDR_B_DQSB_7
DDR_B_DM_7
AB35
AD35
AD37
M_DQS_B7
M_DQS_BJ7
M_DQM_B7
DDR_B_DQ_56
DDR_B_DQ_57
DDR_B_DQ_58
DDR_B_DQ_59
DDR_B_DQ_60
DDR_B_DQ_61
DDR_B_DQ_62
DDR_B_DQ_63
AD40
AD38
AB40
AA39
AE36
AE39
AB37
AB38
M_DATA_B56
M_DATA_B57
M_DATA_B58
M_DATA_B59
M_DATA_B60
M_DATA_B61
M_DATA_B62
M_DATA_B63
DDR_B_DQS_0
DDR_B_DQSB_0
DDR_B_DM_0
M_DQS_B[7..0] 17
M_DQS_BJ[7..0] 17
M_DQM_B[7..0] 17
M_DATA_B[63..0] 17
M_DQS_B[7..0] 17
M_DQS_BJ[7..0] 17
M_DQM_B[7..0] 17
M_DATA_B[63..0] 17
D
M_DQS_B[7..0] 17
M_DQS_BJ[7..0] 17
M_DQM_B[7..0] 17
M_DATA_B[63..0] 17
M_DQS_B[7..0] 17
M_DQS_BJ[7..0] 17
M_DQM_B[7..0] 17
M_DATA_B[63..0] 17
C
M_DQS_B[7..0] 17
M_DQS_BJ[7..0] 17
M_DQM_B[7..0] 17
M_DATA_B[63..0] 17
M_DQS_B[7..0] 17
M_DQS_BJ[7..0] 17
M_DQM_B[7..0] 17
M_DATA_B[63..0] 17
M_DQS_B[7..0] 17
M_DQS_BJ[7..0] 17
M_DQM_B[7..0] 17
M_DATA_B[63..0] 17
B
M_DQS_B[7..0] 17
M_DQS_BJ[7..0] 17
M_DQM_B[7..0] 17
M_DATA_B[63..0] 17
Eaglelake-Q
Eaglelake-Q
1D8V_STR
DDRII Compensation Group Signals
*
*R366
1K
R314
+/-1%
MCH_DDR_RPD
80.6
+/-1%
MCH_DDR_VREF
+/-1%
*
1D8V_STR
C347
0.1uF
16V, Y5V, +80%/-20%
*
*R335
1K
R365
*
*
width 10 mils, spacing 10 mils
5 mils width/spacing minimum for max. of 300 mils
in GMCH break-out area
Placed close to GMCH pin
A
MCH_DDR_RPU
80.6
+/-1%
C350
0.1uF
16V, Y5V, +80%/-20%
R363
A
249 OhmMCH_DDR_SPD
+/-1%
*
1D8V_STR
R364
*
MCH_DDR_SPU
80.6
+/-1%
C334
0.1uF
16V, Y5V, +80%/-20%
FOXCONN PCEG
Title
Eaglelake -GMCH -2
Size
C
Date:
5
4
3
2
Document Number
Rev
A
G43M01S1
Sheet
Monday, August 11, 2008
1
13
of
41
5
4
3
2
1
1D1V_MCH
VCCDQ_CRT is very sensitive to
low frequency noise (noise below 1MHz).
1D5V_ICH
7 OF 10
U46G
1D1V_PCIEXPRESS
1250mA
6 OF 10
U46F
L42
VCCDQ_CRT
VCC_HDA
1
1
*
C232
10uF
10V, Y5V, +80%/-20%
25V, Y5V, +80%/-20%
BACK
VCCA_DAC_1
VCCA_DAC_2
VCCA_EXP
A17
VCC_EXP
VCCDQ_CRT
B20
B17
VCCDQ_CRT
VSS
(mA)(mVpp)MinVout
VCCAPLL_EXP 50 20 1.045V
/VCCDPLL_EXP
VCC_CKDDR_1
VCC_CKDDR_2
VCC_CKDDR_3
VCC_CKDDR_4
VCCCML_DDR
AM30
1
2
C267
0.1uF
16V, Y5V, +80%/-20%
C318
4.7uF
*R315
refer to EL update summary
052208
If HDMI is not supported,VCC_HDA
should be shorted to GND
VCCA_DPLLA
*
2
1
1
1
2
1
C364
2.2uF
*
C357
2.2uF
2
*
C356
2.2uF
*
C367
2.2uF
*
C366
2.2uF
Connect ground sides of caps with traces to GND balls
(less than 100 mils from the package)
Eaglelake-Q
1D1V_MCH
EC43
220uF
6.3V, +/-20%
*
C246
0.1uF
16V, Y5V, +80%/-20%
(mA)(mVpp)MinVout
VCCA_DPLLA/B>102 50 1.045V
1D1V_MCH
*
1D1V_MCH
2
C303
10uF
*
C576
1uF
BACK
*
C575
1uF
BACK
*
C274
1uF
BACK
C574
1uF
BACK
*
C280
1uF
BACK
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
Place these caps close to 1D1V_MCH plane in MCH backside
*
1
C578
1uF
BACK
2
*
1
C577
1uF
BACK
2
*
1
C291
1uF
BACK
2
*
1
C567
10uF
BACK
2
*
1
C566
10uF
BACK
2
*
1
C571
10uF
BACK
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
A
*
2
BACK
1
C570
10uF
2
BACK
C209
10uF
10V, Y5V, +80%/-20%
*
BACK
*
*
C238
10uF
*
C230
10uF
10V, Y5V, +80%/-20%
C245
0.1uF
16V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
*
10V, Y5V, +80%/-20%
EC44
220uF
6.3V, +/-20%
VCCA_DPLLB
*
C358
2.2uF
1
*
1
2 L0805 10uH
+/-20%
0
Dummy
INT VRM DISABLE: VCCAVRM_EXP --->1.1V
INT VRM ENABLE: VCCAVRM_EXP --->1.5V
for better PCIe Gen2 performance???
VCC_HDA
0
1D5V_ICH
R275
*R316
1D1V_MCH_CL
L36 1
*
6.3V, X5R, +/-10%
dummy
0
dummy
1
2 L0805 10uH
+/-20%
*
(mA)(mVpp)MinVout
VCCAPLL_EXP 50 20 1.045V
/VCCDPLL_EXP
2
L40 1
C243
10uF
10V, Y5V, +80%/-20%
1D5V_ICH
B
*
6.3V, Y5V, +80%/-20%
VCCA_GPLL
*
0
6.3V, Y5V, +80%/-20%
1
R274
6.3V, Y5V, +80%/-20%
1
R220
VCCAVRAM_EXP
C260
0.1uF
16V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
R221
1D1V_MCH
*
1D8V_STR
6.3V, Y5V, +80%/-20%
2 L0805 1uH
+/-10%
C255
10uF
10V, Y5V, +80%/-20%
1D1V_MCH_CL
C231
2.2uF
Place in FSB_VTT plane as close to the GMCH as possible
(less than 100 mils from the package)
6.3V, Y5V, +80%/-20%
L41 1
VCCCML_DDR
*
C254
2.2uF
1
1
L49
100nH
Eaglelake-Q
*
C229
2.2uF
2
*
2
R230
BACK
VCCA_GPLLD
1
C579
22uF
6.3V,X5R,+/-20%
*
1
R231
+/-5%
BACK
AG2
1
2 L0805 1uH
+/-10%
*
2
L44 1
1
B
*R579
0
+/-5%
BACK
AK32
AL31
AL32
AM31
VCCAVRAM_EXP
1D1V_MCH
*R580
0
A25
B25
B26
C24
C26
D22
D23
D24
E23
F21
F22
G21
G22
H21
H22
J21
J22
K21
K22
L21
L22
M21
M22
N20
N21
N22
P20
P21
P22
P24
R20
R21
R22
R23
R24
2
1
2
R211
B19
D19
C582
0.1uF
FSB_VTT
VTT_FSB_1
VTT_FSB_2
VTT_FSB_3
VTT_FSB_4
VTT_FSB_5
VTT_FSB_6
VTT_FSB_7
VTT_FSB_8
VTT_FSB_9
VTT_FSB_10
VTT_FSB_11
VTT_FSB_12
VTT_FSB_13
VTT_FSB_14
VTT_FSB_15
VTT_FSB_16
VTT_FSB_17
VTT_FSB_18
VTT_FSB_19
VTT_FSB_20
VTT_FSB_21
VTT_FSB_22
VTT_FSB_23
VTT_FSB_24
VTT_FSB_25
VTT_FSB_26
VTT_FSB_27
VTT_FSB_28
VTT_FSB_29
VTT_FSB_30
VTT_FSB_31
VTT_FSB_32
VTT_FSB_33
VTT_FSB_34
VTT_FSB_35
1
For layout, change it from
1D1V_MCH_CL to 1D1V_MCH.
VCCA_DAC
16V, Y5V, +80%/-20%
*
Dummy
1
*
R213
4.7uF
6.3V, X5R, +/-10%
* *
VCCA_MPLL
2.2uH
+/-20%
VCC_HDA
C235
0.1uF
C
FSB_VTT
1
AR2
C193
1D1V_MCH
VCC_CKDDR
Place in 1D1V_MCH_CL plane
(less than 100 mils from the package)
2
VCC3_3
10V, Y5V, +80%/-20%
1
E19
3D3V_SYS
L57
L0805 1uH
+/-10%
BACK
0.16uH
(mA)MinVout
VCC_SMCLK 450 1.7V
C329
10uF
2
VCCA_HPLL
VCCA_MPLL
VCCA_DPLLA
VCCA_DPLLB
10V, Y5V, +80%/-20%
1
B22
A21
D20
C20
2
VCCA_HPLL
VCCA_MPLL
VCCA_DPLLA
VCCA_DPLLB
*
C349
10uF
6.3V, Y5V, +80%/-20%
VCCDPLL_EXP
VCCD_HPLL
VCCAPLL_EXP
*
6.3V, Y5V, +80%/-20%
B12
U33
B16
A
FOXCONN PCEG
Title
Eaglelake -GMCH -3
Size
C
Date:
5
D
*
1D1V_MCH_CL
6.3V, Y5V, +80%/-20%
VCCA_GPLLD
VCCD_HPLL
VCCA_GPLL
COPPER
1
2 Dummy
1
*
C247
2.2uF
6.3V, Y5V, +80%/-20%
1D8V_STR
*
2
#REFDE6
(mA)(mVpp)MinVout
VCCA_MPLL >102 70 1.045V
L38
AP44
AT45
AV44
AY40
BA41
BB39
BD21
BD25
BD29
BD34
BD38
BE23
BE27
BE31
BE36
Place these parts close to
VCC_CKDDR ballout in MCH backside
*
1
*
For layout, change it from
1D1V_MCH_CL to 1D1V_MCH.
VCC_DDR_1
VCC_DDR_2
VCC_DDR_3
VCC_DDR_4
VCC_DDR_5
VCC_DDR_6
VCC_DDR_7
VCC_DDR_8
VCC_DDR_9
VCC_DDR_10
VCC_DDR_11
VCC_DDR_12
VCC_DDR_13
VCC_DDR_14
VCC_DDR_15
1D8V_STR
1D1V_MCH_CL
*
2
VCCA_HPLL
270nH
+/-20%
2
*
L37
*
1
(mA)(mVpp)MinVout
VCCA_HPLL >50 70 1.045V
1D1V_MCH
C
10V, Y5V, +80%/-20%
*
2
Stuff for Non-Graphic sku
C603
C604
C580
C320
0.1uF
0.1uF
10uF
10uF
10V, Y5V, +80%/-20%
25V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
25V, Y5V, +80%/-20%
C573
10uF
1
C261
1uF
10V, Y5V, +80%/-20%
BACK
*
2
(mA)MinVout
VCCA_DAC 70 2.97V
1
*
6.3V, +/-20%
1
EC42
220uF
2
*
FB 600 Ohm
VCCA_DAC
1
1 COPPER
2
R229
1 COPPER
#REFDE16
2
1
L39
#REFDE15
2
2
2
+/-1%
3D3V_SYS
C252
1uF
10V, Y5V, +80%/-20%
AA14
AA15
AB14
AC15
AD14
AD15
AE14
AE15
AF14
AF15
AG15
AJ10
AJ11
AJ12
AJ13
AJ14
AJ6
AJ7
AJ8
AJ9
AK10
AK11
AK12
AK13
AK6
AK7
AK8
AK9
U14
U15
W15
Y14
Y15
AJ1
AJ2
AK2
AK3
AK4
1
1
*R222 *
39.2
Dummy
*
1 VCCA_EXP
R235
+/-1%
VCC_EXP_1
VCC_EXP_2
VCC_EXP_3
VCC_EXP_4
VCC_EXP_5
VCC_EXP_6
VCC_EXP_7
VCC_EXP_8
VCC_EXP_9
VCC_EXP_10
VCC_EXP_11
VCC_EXP_12
VCC_EXP_13
VCC_EXP_14
VCC_EXP_15
VCC_EXP_16
VCC_EXP_17
VCC_EXP_18
VCC_EXP_19
VCC_EXP_20
VCC_EXP_21
VCC_EXP_22
VCC_EXP_23
VCC_EXP_24
VCC_EXP_25
VCC_EXP_26
VCC_EXP_27
VCC_EXP_28
VCC_EXP_29
VCC_EXP_30
VCC_EXP_31
VCC_EXP_32
VCC_EXP_33
VCC_EXP_34
VCC_EXP_35
VCC_EXP_36
VCC_EXP_37
VCC_EXP_38
2
40.2
Dummy
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
VCC_74
VCC_75
VCC_76
VCC_77
VCC_78
VCC_79
VCC_80
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_86
VCC_87
VCC_88
VCC_89
VCC_90
VCC_91
VCC_92
VCC_93
VCC_94
VCC_95
VCC_96
VCC_97
VCC_98
1
*
R232
(mA)MinVout
VCCA_EXP 4 1.425V
AA19
AA21
AA23
AA25
AA27
AA29
AA30
AB20
AB22
AB24
AB26
AB29
AB30
AC16
AC17
AC19
AC21
AC23
AC25
AC27
AC29
AD16
AD17
AD20
AD22
AD24
AD26
AD29
AE16
AE17
AE19
AE21
AE23
AE25
AE27
AE29
AF16
AF17
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
AF27
AF29
AG16
AG17
AG20
AG22
AG24
AG26
AG29
AJ16
AJ17
AJ19
AJ21
AJ23
AJ25
R25
R26
R27
R29
T21
T24
T25
T26
T27
T29
U21
U22
U23
U24
U25
U26
U27
U29
W19
W21
W23
W25
W27
W29
Y20
Y22
Y24
Y26
T22
T23
AC4
AF3
F9
H4
L3
P3
V4
2
*
L43
FB 600 Ohm
AK21
AK22
AK23
AK24
AK25
AK26
AK27
AK29
AK30
AL1
AL10
AL11
AL12
AL14
AL15
AL16
AL17
AL19
AL2
AL20
AL21
AL22
AL23
AL24
AL25
AL26
AL27
AL29
AL4
AL5
AL6
AL7
AL8
AL9
AM2
AM3
AM4
AJ15
AK14
AJ27
AJ29
Y29
Y30
W31
1
1D5V_ICH
Check footprint 0603???
VCC_CL_42
VCC_CL_43
VCC_CL_44
VCC_CL_45
VCC_CL_46
VCC_CL_47
VCC_CL_48
VCC_CL_49
VCC_CL_50
VCC_CL_51
VCC_CL_52
VCC_CL_53
VCC_CL_54
VCC_CL_55
VCC_CL_56
VCC_CL_57
VCC_CL_58
VCC_CL_59
VCC_CL_60
VCC_CL_61
VCC_CL_62
VCC_CL_63
VCC_CL_64
VCC_CL_65
VCC_CL_66
VCC_CL_67
VCC_CL_68
VCC_CL_69
VCC_CL_70
VCC_CL_71
VCC_CL_72
VCC_CL_73
VCC_CL_74
VCC_CL_75
VCC_CL_76
VCC_CL_77
VCC_CL_78
VCC_CL_79
VCC_CL_80
VCC_CL_81
VCC_CL_82
VCC_CL_83
VCC_CL_84
VCC_CL_85
1 COPPER
2
D
VCC_CL_1
VCC_CL_2
VCC_CL_3
VCC_CL_4
VCC_CL_5
VCC_CL_6
VCC_CL_7
VCC_CL_8
VCC_CL_9
VCC_CL_10
VCC_CL_11
VCC_CL_12
VCC_CL_13
VCC_CL_14
VCC_CL_15
VCC_CL_16
VCC_CL_17
VCC_CL_18
VCC_CL_19
VCC_CL_20
VCC_CL_21
VCC_CL_22
VCC_CL_23
VCC_CL_24
VCC_CL_25
VCC_CL_26
VCC_CL_27
VCC_CL_28
VCC_CL_29
VCC_CL_30
VCC_CL_31
VCC_CL_32
VCC_CL_33
VCC_CL_34
VCC_CL_35
VCC_CL_36
VCC_CL_37
VCC_CL_38
VCC_CL_39
VCC_CL_40
VCC_CL_41
2
2
AA32
AA33
AB32
AB33
AD32
AD33
AE32
AE33
AF32
AJ32
AK31
AL30
AM15
AM16
AM17
AM20
AM21
AM22
AM24
AM25
AM26
AM29
Y32
Y33
AP1
AP2
Y31
AA31
AB31
AC31
AD31
AE31
AF31
AG30
AG31
AJ30
AJ31
AK16
AK17
AK19
AK20
1
(mA)MinVout
VCCDQ_CRT 0.5 1.35V
#REFDE14
2
2
1
C239
1uF
10V, Y5V, +80%/-20%
2
1
*
1D1V_MCH
POWER
R223
FB 600 Ohm
POWER
*
1D1V_MCH_CL
2
1D1V_MCH_CL
4
3
2
Document Number
Rev
A
G43M01S1
Sheet
Monday, August 11, 2008
1
14
of
41
5
4
3
8 OF 10
U46H
2
1
9 OF 10
U46I
10 OF 10
U46J
C
B
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
W17
L26
L30
L35
L39
L4
L8
L9
M1
M24
M25
M44
N11
N13
N16
N26
N29
N30
N33
N36
N38
N8
P16
P17
P25
P26
P31
R11
R12
R16
R17
R19
R2
R30
R38
R45
R5
R8
T10
T11
T12
T13
T16
T17
T19
T20
T3
T30
T31
T32
T33
T35
T38
T4
T40
T6
T7
T8
T9
U1
W2
W20
W22
W24
W26
W44
W45
W5
Y10
Y11
Y12
Y13
Y16
Y17
Y19
Y2
Y21
Y23
Y25
Y27
Y3
Y35
Y39
Y9
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360
VSS_361
VSS_362
VSS_363
VSS_364
VSS_365
VSS_366
VSS_367
VSS_368
VSS_369
VSS_370
VSS_371
VSS_372
GND
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
AJ36
AJ39
AJ44
AJ45
AK35
AK38
AK39
AL38
AL44
AL45
AN21
AN22
AN24
AN25
AN26
AN33
AN36
AN38
AN7
AP20
AP21
AP22
AP24
AP25
AP29
AP45
AR10
AR11
AR13
AR16
AR26
AR3
AR31
AR33
AR35
AR39
AR8
AR9
AT1
AT11
AT13
AT17
AT2
AT24
AT29
AT35
AU20
AU22
AU25
AU30
AU35
AU5
AU6
AU9
AV11
AV13
AV15
AV16
AV2
AV21
AV30
AV33
AV38
AV6
AV8
AV9
AW11
AW17
AW20
AW22
AW24
AW26
AW3
AW30
AY1
AY15
AY16
AY21
AY25
AY30
AY45
B10
B21
B27
B29
B34
BA23
F8
BB21
BB25
BB28
BB6
GND
D
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
GND
A12
A15
A19
A27
A31
A36
A40
A8
AA1
AA11
AA12
AA13
AA16
AA17
AA20
AA22
AA24
AA26
AA34
AA38
AA40
AA44
AA8
AB11
AB12
AB16
AB17
AB19
AB21
AB23
AB25
AB27
AB34
AB36
AB39
AB4
AB6
AB7
AB8
AC20
AC22
AC24
AC26
AC45
AC5
AD12
AD19
AD21
AD23
AD25
AD27
AD3
AD34
AD36
AD39
AD6
AD9
AE1
AE11
AE12
AE13
AE20
AE22
AE24
AE26
AE34
AE38
AE40
AE44
AE8
AF10
AF11
AF12
AF13
AF33
AF35
AF39
AF6
AF7
AG19
AG21
AG23
AG25
AG27
AG45
AG5
AH2
AH3
AH4
AJ20
AJ22
AJ24
AJ26
BD12
BD17
BD43
BD8
BE10
BE15
BE19
BE21
BE25
BE29
BE34
BE40
C16
C3
C5
D11
D16
D21
D25
D26
D39
D6
D7
E3
E31
E41
E5
F16
F2
F30
F4
F42
F45
G11
G17
G24
G26
G29
G3
G35
H1
H11
H13
H15
H16
H20
H25
H30
H31
H33
H38
H44
H7
H8
H9
J3
J37
J4
J5
J8
J9
K11
K13
K17
K20
K24
K29
K33
K45
L10
L16
L20
U11
U12
U13
U16
U17
U19
U20
U36
U39
U44
U8
W1
W16
A3
A43
A6
B44
BC1
BC45
BD2
BD44
BE3
BE43
C1
C45
F1
BA5
AD30
AC30
AF30
AE30
D
Eaglelake-Q
C
U46_1
B
2 2
1 A1
D
5C 5
6 6
B
Heatsink
CLIP1N
1
CLIP3N
1
2
2
Clip_2P
Clip_2P
For GMCH heatsink hook
A
A
FOXCONN PCEG
Title
Eaglelake -GMCH -4
Size
C
Date:
5
4
3
2
Document Number
Rev
A
G43M01S1
Sheet
Monday, August 11, 2008
1
15
of
41
5
4
3
2
1
DIMM1
1D8V_STR
13,18 M_BS_A[2..0]
M_BS_A1
M_BS_A0
13,18 M_SCKE_A[1..0]
M_SCKE_A1
M_SCKE_A0
13,18 M_SCS_A1J
13,18 M_SCS_A0J
13
13
13
13
13
13
CK_M_200M_N_DDR2_A
CK_M_200M_P_DDR2_A
CK_M_200M_N_DDR1_A
CK_M_200M_P_DDR1_A
CK_M_200M_N_DDR0_A
CK_M_200M_P_DDR0_A
13,18 M_MAA_A[14..0]
M_MAA_A0
M_MAA_A1
M_MAA_A2
M_MAA_A3
M_MAA_A4
M_MAA_A5
M_MAA_A6
M_MAA_A7
M_MAA_A8
M_MAA_A9
M_MAA_A10
M_MAA_A11
M_MAA_A12
M_MAA_A13
M_MAA_A14
A
13,18 M_BS_A[2..0]
M_BS_A2
13,18 M_CAS_AJ
13,18 M_RAS_AJ
13,18 M_WE_AJ
101
240
239
SA2
SA1
SA0
190
71
BA1
BA0
171
52
CKE1
CKE0
76
193
S1#
S0#
221
220
138
137
186
185
CK2#/RFU
CK2/RFU
CK1#/RFU
CK1/RFU
CK0#
CK0
188
183
63
182
61
60
180
58
179
177
70
57
176
196
174
173
54
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2
74
192
73
CAS#
RAS#
WE#
37
36
DQS<4>
DQS#<4>
84
83
DQS<5>
DQS#<5>
93
92
DQS<6>
DQS#<6>
105
104
DQS<7>
DQS#<7>
114
113
DQS<8>
DQS#<8>
M_DQS_AJ2
M_DQS_A3
1D8V_STR
M_DQS_AJ3
M_DQS_A4
*R446
1K
M_DQS_AJ4
M_DQS_A5
+/-1%
M_DQS_AJ5
M_DQS_A6
SMVREF_A
*
M_DQS_AJ6
M_DQS_A7
R453
1K
+/-1%
M_DQS_AJ7
M_DQS_A[7..0]
46
45
DM0/DQS9
NC/DQS9#
125
126
M_DQM_A0
DM1/DQS10
NC/DQS10#
134
135
M_DQM_A1
DM2/DQS11
NC/DQS11#
146
147
M_DQM_A2
DM3/DQS12
NC/DQS12#
155
156
M_DQM_A3
DM4/DQS13
NC/DQS13#
202
203
M_DQM_A4
DM5/DQS14
NC/DQS14#
211
212
M_DQM_A5
DM6/DQS15
NC/DQS15#
223
224
M_DQM_A6
DM7/DQS16
NC/DQS16#
232
233
M_DQM_A7
DM8/DQS17
NC/DQS17#
164
165
DQ<0>
DQ<1>
DQ<2>
DQ<3>
DQ<4>
DQ<5>
DQ<6>
DQ<7>
DQ<8>
DQ<9>
DQ<10>
DQ<11>
DQ<12>
DQ<13>
DQ<14>
DQ<15>
DQ<16>
DQ<17>
DQ<18>
DQ<19>
DQ<20>
DQ<21>
DQ<22>
DQ<23>
DQ<24>
DQ<25>
DQ<26>
DQ<27>
DQ<28>
DQ<29>
DQ<30>
DQ<31>
DQ<32>
DQ<33>
DQ<34>
DQ<35>
DQ<36>
DQ<37>
DQ<38>
DQ<39>
DQ<40>
DQ<41>
DQ<42>
DQ<43>
DQ<44>
DQ<45>
DQ<46>
DQ<47>
DQ<48>
DQ<49>
DQ<50>
DQ<51>
DQ<52>
DQ<53>
DQ<54>
DQ<55>
DQ<56>
DQ<57>
DQ<58>
DQ<59>
DQ<60>
DQ<61>
DQ<62>
DQ<63>
3
4
9
10
122
123
128
129
12
13
21
22
131
132
140
141
24
25
30
31
143
144
149
150
33
34
39
40
152
153
158
159
80
81
86
87
199
200
205
206
89
90
95
96
208
209
214
215
98
99
107
108
217
218
226
227
110
111
116
117
229
230
235
236
C424
0.1uF
16V, Y5V, +80%/-20%
close to DIMM pin
Width 10 mils minimum, Spacing 10 mils minimum.
C
1D8V_STR
M_DQM_A[7..0]
M_DATA_A0
M_DATA_A1
M_DATA_A2
M_DATA_A3
M_DATA_A4
M_DATA_A5
M_DATA_A6
M_DATA_A7
M_DATA_A8
M_DATA_A9
M_DATA_A10
M_DATA_A11
M_DATA_A12
M_DATA_A13
M_DATA_A14
M_DATA_A15
M_DATA_A16
M_DATA_A17
M_DATA_A18
M_DATA_A19
M_DATA_A20
M_DATA_A21
M_DATA_A22
M_DATA_A23
M_DATA_A24
M_DATA_A25
M_DATA_A26
M_DATA_A27
M_DATA_A28
M_DATA_A29
M_DATA_A30
M_DATA_A31
M_DATA_A32
M_DATA_A33
M_DATA_A34
M_DATA_A35
M_DATA_A36
M_DATA_A37
M_DATA_A38
M_DATA_A39
M_DATA_A40
M_DATA_A41
M_DATA_A42
M_DATA_A43
M_DATA_A44
M_DATA_A45
M_DATA_A46
M_DATA_A47
M_DATA_A48
M_DATA_A49
M_DATA_A50
M_DATA_A51
M_DATA_A52
M_DATA_A53
M_DATA_A54
M_DATA_A55
M_DATA_A56
M_DATA_A57
M_DATA_A58
M_DATA_A59
M_DATA_A60
M_DATA_A61
M_DATA_A62
M_DATA_A63
*
13
M_DATA_A[63..0]
13
13
*
C3
1uF
*
C4
1uF
*
C5
1uF
*
C6
1uF
*
C7
1uF
10V, Y5V, +80%/-20%
SA2 SA1 SA0
0
0
0
RC1
RC0
VDDSPD
VREF
SCL
SDA
DQS<3>
DQS#<3>
M_DQS_AJ1
M_DQS_A2
10V, Y5V, +80%/-20%
17,38 SMB_CLK_OPTION
17,38 SMB_DATA_OPTION
18
55
238
1
120
119
28
27
10V, Y5V, +80%/-20%
SMVREF_A
16
15
DQS<2>
DQS#<2>
10V, Y5V, +80%/-20%
VDDSPD
B
DQS<1>
DQS#<1>
13
M_DQS_A0
M_DQS_AJ0
M_DQS_A1
10V, Y5V, +80%/-20%
Channel A DIMM 1 1.8V high-frequency decoupling caps.
place as close to DIMM power pins as possible
7
6
1
C2
1uF
10V, Y5V, +80%/-20%
2
1
*
M_DQS_AJ[7..0]
DQS<0>
DQS#<0>
2
1D8V_STR
D
1
C
42
43
48
49
161
162
167
168
13,18
2
Place between GMCH and DIMM
CB<0>
CB<1>
CB<2>
CB<3>
CB<4>
CB<5>
CB<6>
CB<7>
M_ODT_A[1..0]
M_ODT_A1
M_ODT_A0
1
*
EC62
1000uF
+/-20%
77
195
2
1D8V_STR
ODT1
ODT0
1
Place between Ch A DIMM II
and Ch B DIMM 1
68
102
19
2
Change 0611
1D8V_STR
NC_1
NC/TEST
NC_2
1
D
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
2
Del 3 pcs ECPs
2
5
8
11
14
17
20
23
26
29
32
35
38
41
44
47
50
65
66
79
82
85
88
91
94
97
100
103
106
109
112
115
118
121
124
127
130
133
136
139
142
145
148
151
154
157
160
163
166
169
198
201
204
207
210
213
216
219
222
225
228
231
234
237
51
56
62
72
75
78
191
194
181
175
170
53
59
64
197
69
172
187
184
178
189
67
B
Channel A DIMM II 1.8V high-frequency decoupling caps.
place as close to DIMM power pins as possible
A
FOXCONN PCEG
Title
DDR3 Channel A DIMM 1, 2
Size
C
DDR II
CONN,DIMM,DDR II,1.8V,V/T,Blue,G/F,G,DIP-240
Date:
5
4
3
2
Document Number
Rev
A
G43M01S1
Sheet
Monday, August 11, 2008
1
16
of
41
5
4
3
2
1
DIMM2
13,18 M_SCS_B1J
13,18 M_SCS_B0J
13
13
13
13
13
13
CK_M_200M_N_DDR2_B
CK_M_200M_P_DDR2_B
CK_M_200M_N_DDR1_B
CK_M_200M_P_DDR1_B
CK_M_200M_N_DDR0_B
CK_M_200M_P_DDR0_B
13,18 M_MAA_B[14..0]
M_MAA_B0
M_MAA_B1
M_MAA_B2
M_MAA_B3
M_MAA_B4
M_MAA_B5
M_MAA_B6
M_MAA_B7
M_MAA_B8
M_MAA_B9
M_MAA_B10
M_MAA_B11
M_MAA_B12
M_MAA_B13
M_MAA_B14
A
13,18 M_BS_B[2..0]
M_BS_B2
13,18 M_CAS_BJ
13,18 M_RAS_BJ
13,18 M_WE_BJ
190
71
BA1
BA0
171
52
CKE1
CKE0
76
193
S1#
S0#
221
220
138
137
186
185
CK2#/RFU
CK2/RFU
CK1#/RFU
CK1/RFU
CK0#
CK0
188
183
63
182
61
60
180
58
179
177
70
57
176
196
174
173
54
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2
74
192
73
CAS#
RAS#
WE#
16
15
DQS<2>
DQS#<2>
28
27
DQS<3>
DQS#<3>
37
36
DQS<4>
DQS#<4>
84
83
DQS<5>
DQS#<5>
93
92
DQS<6>
DQS#<6>
105
104
DQS<7>
DQS#<7>
114
113
DQS<8>
DQS#<8>
46
45
M_DQS_BJ1
M_DQS_B2
1D8V_STR
M_DQS_BJ2
M_DQS_B3
*R456
1K
M_DQS_BJ3
M_DQS_B4
+/-1%
M_DQS_BJ4
M_DQS_B5
SMVREF_B
M_DQS_BJ5
M_DQS_B6
M_DQS_BJ6
M_DQS_B7
M_DQS_BJ7
DM0/DQS9
NC/DQS9#
125
126
M_DQM_B0
DM1/DQS10
NC/DQS10#
134
135
M_DQM_B1
DM2/DQS11
NC/DQS11#
146
147
M_DQM_B2
DM3/DQS12
NC/DQS12#
155
156
M_DQM_B3
DM4/DQS13
NC/DQS13#
202
203
M_DQM_B4
DM5/DQS14
NC/DQS14#
211
212
M_DQM_B5
DM6/DQS15
NC/DQS15#
223
224
M_DQM_B6
DM7/DQS16
NC/DQS16#
232
233
M_DQM_B7
DM8/DQS17
NC/DQS17#
164
165
DQ<0>
DQ<1>
DQ<2>
DQ<3>
DQ<4>
DQ<5>
DQ<6>
DQ<7>
DQ<8>
DQ<9>
DQ<10>
DQ<11>
DQ<12>
DQ<13>
DQ<14>
DQ<15>
DQ<16>
DQ<17>
DQ<18>
DQ<19>
DQ<20>
DQ<21>
DQ<22>
DQ<23>
DQ<24>
DQ<25>
DQ<26>
DQ<27>
DQ<28>
DQ<29>
DQ<30>
DQ<31>
DQ<32>
DQ<33>
DQ<34>
DQ<35>
DQ<36>
DQ<37>
DQ<38>
DQ<39>
DQ<40>
DQ<41>
DQ<42>
DQ<43>
DQ<44>
DQ<45>
DQ<46>
DQ<47>
DQ<48>
DQ<49>
DQ<50>
DQ<51>
DQ<52>
DQ<53>
DQ<54>
DQ<55>
DQ<56>
DQ<57>
DQ<58>
DQ<59>
DQ<60>
DQ<61>
DQ<62>
DQ<63>
3
4
9
10
122
123
128
129
12
13
21
22
131
132
140
141
24
25
30
31
143
144
149
150
33
34
39
40
152
153
158
159
80
81
86
87
199
200
205
206
89
90
95
96
208
209
214
215
98
99
107
108
217
218
226
227
110
111
116
117
229
230
235
236
M_DQS_B[7..0]
C444
0.1uF
16V, Y5V, +80%/-20%
13
Placed close to DIMM pin
Width 10 mils minimum, Spacing 10 mils minimum.
C
M_DQM_B[7..0]
M_DATA_B0
M_DATA_B1
M_DATA_B2
M_DATA_B3
M_DATA_B4
M_DATA_B5
M_DATA_B6
M_DATA_B7
M_DATA_B8
M_DATA_B9
M_DATA_B10
M_DATA_B11
M_DATA_B12
M_DATA_B13
M_DATA_B14
M_DATA_B15
M_DATA_B16
M_DATA_B17
M_DATA_B18
M_DATA_B19
M_DATA_B20
M_DATA_B21
M_DATA_B22
M_DATA_B23
M_DATA_B24
M_DATA_B25
M_DATA_B26
M_DATA_B27
M_DATA_B28
M_DATA_B29
M_DATA_B30
M_DATA_B31
M_DATA_B32
M_DATA_B33
M_DATA_B34
M_DATA_B35
M_DATA_B36
M_DATA_B37
M_DATA_B38
M_DATA_B39
M_DATA_B40
M_DATA_B41
M_DATA_B42
M_DATA_B43
M_DATA_B44
M_DATA_B45
M_DATA_B46
M_DATA_B47
M_DATA_B48
M_DATA_B49
M_DATA_B50
M_DATA_B51
M_DATA_B52
M_DATA_B53
M_DATA_B54
M_DATA_B55
M_DATA_B56
M_DATA_B57
M_DATA_B58
M_DATA_B59
M_DATA_B60
M_DATA_B61
M_DATA_B62
M_DATA_B63
*
*
R459
1K
+/-1%
M_DATA_B[63..0]
13
13
1D8V_STR
B
*
C426
1uF
*
C412
1uF
*
C13
1uF
1
M_SCKE_B1
M_SCKE_B0
DQS<1>
DQS#<1>
13
M_DQS_B0
M_DQS_BJ0
M_DQS_B1
*
C413
1uF
10V, Y5V, +80%/-20%
M_BS_B1
M_BS_B0
13,18 M_SCKE_B[1..0]
SA2
SA1
SA0
7
6
10V, Y5V, +80%/-20%
13,18 M_BS_B[2..0]
101
240
239
M_DQS_BJ[7..0]
DQS<0>
DQS#<0>
10V, Y5V, +80%/-20%
SA2 SA1 SA0
0
1
0
RC1
RC0
VDDSPD
VREF
SCL
SDA
D
10V, Y5V, +80%/-20%
16,38 SMB_CLK_OPTION
16,38 SMB_DATA_OPTION
18
55
238
1
120
119
42
43
48
49
161
162
167
168
13,18
2
SMVREF_B
CB<0>
CB<1>
CB<2>
CB<3>
CB<4>
CB<5>
CB<6>
CB<7>
M_ODT_B[1..0]
M_ODT_B1
M_ODT_B0
1
VDDSPD
B
77
195
2
1D8V_STR
ODT1
ODT0
1
Channel B DIMM1 1.8V high-frequency decoupling caps.
place as close to DIMM power pins as possible
68
102
19
2
C414
1uF
NC_1
NC/TEST
NC_2
1
*
1
2
10V, Y5V, +80%/-20%
C486
1uF
2
10V, Y5V, +80%/-20%
C
*
1
1
C508
1uF
2
1
*
10V, Y5V, +80%/-20%
C12
1uF
10V, Y5V, +80%/-20%
*
2
1D8V_STR
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
2
D
2
5
8
11
14
17
20
23
26
29
32
35
38
41
44
47
50
65
66
79
82
85
88
91
94
97
100
103
106
109
112
115
118
121
124
127
130
133
136
139
142
145
148
151
154
157
160
163
166
169
198
201
204
207
210
213
216
219
222
225
228
231
234
237
51
56
62
72
75
78
191
194
181
175
170
53
59
64
197
69
172
187
184
178
189
67
Channel B DIMM II 1.8V high-frequency decoupling caps.
place as close to DIMM power pins as possible
A
FOXCONN PCEG
Title
DDR3 Channel B DIMM 3, 4
DDR II
CONN,DIMM,DDR II,1.8V,V/T,Blue,G/F,G,DIP-240
Size
C
Date:
5
4
3
2
Document Number
Rev
A
G43M01S1
Sheet
Monday, August 11, 2008
1
17
of
41
5
4
M_ODT_A[1..0]
M_SCKE_A[1..0]
M_BS_A[2..0]
3
13,16
M_SCKE_B[1..0]
13,16
M_BS_B[2..0]
13,16
2
1
13,17
13,17
M_MAA_B[14..0] 13,17
M_MAA_A[14..0] 13,16
M_ODT_B[1..0]
13,17
D
D
VTT_DDR
**
VTT_DDR
*
R506
R503
R447
33
33
M_MAA_B2
M_MAA_B13
M_MAA_A13
33
RN50 33
*1
*1
M_RAS_AJ
M_WE_AJ
2
4
6
8
**
3
5
7
R450
R451
M_CAS_AJ
M_RAS_AJ
M_WE_AJ
13,16
13,16
M_CAS_AJ
13,16
3
5
7
M_MAA_A3
M_MAA_A2
M_MAA_A1
2
4
6
8
3
5
7
*1
3
5
7
M_MAA_A9
M_MAA_A7
M_MAA_A5
M_MAA_A8
2
4
6
8
*1
3
5
7
3
5
7
M_MAA_A14
M_BS_A2
M_MAA_A12
M_MAA_A11
2
4
6
8
3
5
7
3
5
7
M_MAA_A0
M_BS_A1
M_MAA_A10
M_BS_A0
2
4
6
8
3
5
7
*
*
*
*
*
*
*
*
*
*
*
C441
C436
C440
C427
C499
C430
C435
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
M_MAA_B5
M_MAA_B4
M_MAA_B3
M_MAA_B1
2
4
6
8
VTT_DDR
2
4
6
8
M_MAA_B0
M_BS_B1
M_MAA_B10
C
Channel A VTT_0.9V high-frequency decoupling caps.
Place as close to termination resistors as possible
M_BS_B0
M_RAS_BJ
M_WE_BJ
M_CAS_BJ
2
4
6
8
M_RAS_BJ
M_WE_BJ
M_CAS_BJ
13,17
13,17
13,17
M_SCS_B0J
M_ODT_B0
M_ODT_B1
M_SCS_B1J
13,17
13,17
13,17
13,17
M_SCKE_B1
13,17
M_SCKE_B0
13,17
RN49 43 Ohm
*1
3
5
7
RN42 43 Ohm
*1
*
RN48 33
*1
RN39 33
*1
*
C493
C475
C442
C495
C439
C434
C483
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
RN47 33
*1
RN43 33
C
*
RN46 33
RN44 33
*1
1D8V_STR
M_MAA_B8
M_MAA_B9
M_MAA_B7
M_MAA_B6
2
4
6
8
3
5
7
RN38 33
*1
VTT_DDR
RN45 33
*1
M_MAA_A6
M_MAA_A4
33
33
M_BS_B2
M_MAA_B14
M_MAA_B12
M_MAA_B11
2
4
6
8
3
5
7
RN40 33
2
4
6
8
M_SCKE_A1
M_SCKE_A0
M_SCKE_A1
M_SCKE_A0
13,16
13,16
M_ODT_A0
13,16
M_SCS_A0J
13,16
2
4
6
8
M_SCS_B0J
M_ODT_B0
M_ODT_B1
M_SCS_B1J
R505
43+/-5%
M_SCKE_B1
R504
43+/-5%
M_SCKE_B0
RN41 43 Ohm
*1
3
5
7
2
4
6
8
M_ODT_A0
M_SCS_A0J
VTT_DDR
1D8V_STR
R448
R449
43+/-5%
43+/-5%
M_SCS_A1J
M_ODT_A1
M_SCS_A1J
M_ODT_A1
13,16
13,16
B
B
*
VTT_DDR
*
C429
4.7uF
*
*
*
*
*
*
*
VTT_DDR
*
C437
4.7uF
*
*
*
*
*
*
*
VTT_DDR
*
Channel B VTT_0.9V high-frequency decoupling caps.
Place as close to termination resistors as possible
C498
4.7uF
6.3V, X5R, +/-10%
Channel A VTT_0.9V Mid Range decoupling caps.
Placed in termination Island
C482
4.7uF
6.3V, X5R, +/-10%
6.3V, X5R, +/-10%
6.3V, X5R, +/-10%
*
*
C479
C496
C474
C476
C485
C497
C484
C589
C590
C431
C477
C481
C480
C428
C425
C433
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, 16V,
+80%/-20%
Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
Channel B VTT_0.9V Mid Range decoupling caps.
Placed in termination Island
A
A
FOXCONN PCEG
Title
DDRII Termination
Size
C
Date:
5
4
3
2
Document Number
Rev
A
G43M01S1
Sheet
Monday, August 11, 2008
1
18
of
41
5
4
3
2
1
12V_SYS
Q53
C512
0.1uF
16V, Y5V, +80%/-20%
*
2
D
*
E
*R607
20K
VID
LR1
LR2
LR3
FSB_VTT
*R540
10K
=>
=>
=>
=>
S
1
*
C397
10uF
2
C377
0.1uF
2
1
*
2
4
6
8
For 1.05V, Change to 1KOhm.
S0 ONLY
STB POWER
STB POWER
STB POWER
1D8V_STR
FSB_VTT
5.8A???
+/-5%
Q34
VTT_PWRGD 8,10
FSBVTT_DRV
C505
0.1uF
16V, Y5V, +80%/-20%
C
G
0.8V
AOD452
FSB_VTT
R470
C504
68nF
*
Dummy
+/-1%
470 Ohm
*
R486
Near ACPI
931 Ohm
+/-1%
R483
FSB_VTT
3.83KOhm
Dummy
R471
+/-1%
680
Dummy
+/-5%
R487
*
C204
10uF
*
*
C448
0.1uF
EC40
1000uF
+/-20%
*
G
S
AOD452
EC67
1000uF
+/-20%
1
*
*
C478
0.1uF
EC63
1000uF
+/-20%
*
0.8V
C469
4.7uF
VPCIE_SEN
16V, Y5V, +80%/-20%
AP15N03H
ICH 1D5V
2.3A
R548
1D5V_ICH
1.4KOhm
+/-1%
6.3V, X5R, +/-10%
R546
1.6KOhm
+/-1%
*
*
C419
10uF
*
C408
0.1uF
*
C455
0.1uF
C409
0.1uF
*
B
EC58
1000uF
+/-20%
Near ACPI
12V_SYS
C533
0.1uF
*
EC69
470uF
+/-20%
*
EC70
470uF
+/-20%
*
C535
10uF
*
C515
10uF
*
C516
10uF
1D1V_Core@23A
* L48
MCH_Core_20A+ICH_Core_1A+VCC_EXP_2A
1uH@1KHz
R208
2.2
2
D
*
*
12V_SYS
1D8V_VIN
5V_SYS
2
RT9173
C491
0.1uF
16V, Y5V, +80%/-20%
G
2
Total: 24A
15A_DDR+5.8A_FSBVTT+
1.2A_DDRVTT+2A_ICH_1D5V
1uH@1KHz
GND
REFEN
Q48
VPCIE_DRV
1
* L55
Q57
+/-1%
4
2
3
*R527
100KOhm
*
VOUT
VTT_DDR
1
5V_DUAL_DDR
8
7
6
5
2
3
Near DIMM
VCC_GTAE
*
EC64
1000uF
+/-20%
VCNTL
VCNTL
VCNTL
VCNTL
1
*
APM2054N
10
1D8V_STR
VIN
R532
100KOhm
+/-1%
D
U21
1
1
D
B
EC71
1000uF
+/-20%
Q58
VTT_SEL
NC : 1.2V
1.2V: 1.2V
Vss : 1.1V
+/-5%
S
0
+/-5%
DUAL_GTAE R601Dummy
0
+/-5%
*
2
R602
1K
3D3V_SYS
1
Check???
USB_GTAE
VTT_DDR
1.2A
1D8V_STR
Dummy
2
1D8V_DDR2
E
5V_SB_SYS
Q50 Dummy
B
MMBT3904-7-F
*
C
Reserve for Power Compatibility
Place close to Pin
*
1
C507
68nF
Dummy
+/-5%
EC55
1000uF
+/-20%
*
16V, Y5V, +80%/-20%
FSBVTT_SEN
*
B
750
+/-1%
Dummy
1
3
5
7
2
Q73
MMBT3904-7-F
1D1V_MCH
*
+/-1%
Dummy
*R526
2KOhm
C501
0.1uF
PSON_R
ATXPWRGD
+/-5%
C
0
+/-5%
1
*
C500
1uF
16V, Y5V, +80/-20%
SLED
*R606
10K
+/-5%
R605
*
R530
FOX ONE
5V_SB_SYS
+/-5%
1D1V_ICH
RN30 0
LR3_SEN
C465
0.47uF
16V, Y5V, +80%/-20%
1
32
*R608
8.2K
5V_SYS
Rear USB
+/-5%
For 1.05V, Change to 316Ohm.
1
5V_SYS
AOD452
4.7K
ATXPWRGD
R542
10 PSON_R
2 Dummy
1
#REFDE3
COPPER
G
AP15N03H
VRAM_UGATE
VRAM_LGATE
VCC_PWM
VRAM_OPS
VRAM_FB
VTT_COMP
VTT_FB
VTT_PWM
R545
29,32 ATXPWRGD
29,32
PS_ONJ
7,23
SLP_S4J
22,23,30,31,33 SMB_CLK_RESUME
22,23,30,31,33 SMB_DATA_RESUME
Dummy Q49
LR3_DRV
2
S
Q17
AOD452
FSBVTT_SEN
FSBVTT_DRV
VTT_OPS
2
Q63
S
D
D
ATXPWRGD
0 VCC_GTAE
G R604Dummy
+/-5%
12V_SYS
G
For EMI
1D1V_ICH
36
35
34
33
32
31
30
29
28
27
26
25
* *
0.1uF
16V, X7R, +/-10%
SLP_S4J status
AMT
non-AMT
S4
1
0
S5
1
0
3D3V_SYS
24
23
22
21
20
19
18
17
16
15
14
13
SS
VID_SEN
VID_DRV
VTT_OPS
GND
VRAM_UGATE
VRAM_LGATE
VCC_PWM
VRAM_OPS
VRAM_FB
COMP
VTT_FB
S
C511
1
R554
+/-5%
0
+/-5%
4.7K
+/-5%
2
C
D
1
1K
+/-5%
R551
VPCIE_SEN
VDUAL3V_SEN
VDUAL3V_DRV
VCCGATE
USBGATE
DUALGATE
GND
RSMRST#
VBAT
PWOK
VCC3V
TURBO#
1
2
3
4
5
6
7
8
9
10
11
12
S
Front USB
dummy
+/-5%16V, Y5V, +80%/-20%
37
38
39
40
41
42
43
44
45
46
47
48
0
Dummy
D32
LS4148-F
2
5
7
* 13
C532
0.1uF
D
2
4
6
8
2
4
6
8
5
7
* 13
C
*
R550
1
3D3V_SYS
+/-1%
AOD452
EC68
1000uF
+/-20%
1D5V_ICH
1D5V_ICH
2
*R553
3.9KOhm
USB_GTAE
A
D
Q59
G
23,29 SIO_RSMRSTJ
VCCRTC
12,22,23,24,29 PWRGD_3V
10K
+/-5%
**
R552
5V_DUAL_USB
5V_SB_SYS
*
C
LS4148-F
D11
A
C
A
LS4148-F
2
12V_SYS
1K
FSB_VTT
C449
0.1uF
LR3_DRV
LR3_SEN
FAULT#/TURBO2#
PWOKIN
PS_ONIN#
S5#
SCLK5
SDATA
PLED
SLED
VREF
VID_GD
VSB5V
VTT_PWM
VPCIE_SEN
3D3V_SB
VDUAL3V_DRV
VCC_GTAE
USB_GTAE
DUAL_GTAE
For VTT Power OCP
3D3V_SYS
RN58
D12
*
C456
4.7uF
VPCIE_DRV
LR1_DRV
LR1_SEN
VSB5V
C1
GND
C2
CP
LR2_SEN
LR2_DRV
LR3_DRV
LR3_SEN
S
U23
Del SLP_S5# control method
EC66
1000uF
+/-20%
*
RN57
VCC_PWM
*
C503
1uF
16V, Y5V, +80/-20%
VCC_GTAE
G
AOD452
5V_DUAL_USB
*
D13
LS4148-F
C
C
*
2
S
EC60
1000uF
+/-20%
*
D
D
C490
0.1uF
VPCIE_DRV
Note:
Over voltage regulator summary:
1. LRPCIE: can set the reference voltage by software.
A: Vref: 0.66V--0.96V /16 steps(Turbo2, Turbo1=01)
B: Vrdf: 0.74V--1.04V/ 16 steps(Turbo2, Turbo1=ohters)
2. LR3: can set the reference voltage by software.
Vref: 0.74V--1.04V /16 steps
3. PWMVRAM,PWMVTT:
Vref: 0.74V--1.04V /16 steps
AP15N03H
1
G VDUAL3V_DRV
3D3V_SB
D19
SD103AW
5V_SB_SYS
Q54
1
D
A
3D3V_Dual
Power Sequence
1.Vcc1_5/Vcc1_1 must power up before V_CPU_IO
or after V_CPU_IO within 0.7V.
2.V_CPU_IO must power down before Vcc1_5/Vcc1_1
or after Vcc1_5 within 0.7V.
Note:Failure to meet the requirement could
cause glitches on CPU interface.
R474
10
+/-5%
5V_SB_SYS
A
5V_SB_SYS
Q60
1
D
1
*
Q40
2
C470
+/-5%
*
*
*
C572
2.2uF
*
*
C569
2.2uF
*
C10
1uF
*
C11
1uF
*
C568
1uF
*
C279
10uF
*
C282
10uF
10V, Y5V, +80%/-20%
A
*
1D1V_MCH
R499
VTT_FB
R481
*
R497
*R524
2KOhm
+/-1%
near ACPI
EC73
1000uF
+/-20%
Dummy
*
820
+/-1%
Reserved for Core voltage request.
050608.
FOXCONN PCEG
Title
*
VTT_COMP
C473
11K 1
2
10nF
+/-1%
+/-10%
C466
4.7nF
47nF
16V,X7R,+/-10%
*
PWMVTT Vref: 0.74V --1.04V/16 steps
0.8V
ACPI Fox-One
Size
C
Date:
5
C1
2.2uF
1
EC41
1000uF
+/-20%
1
EC47
1000uF
+/-20%
1
EC49
1000uF
+/-20%
2
*
1
C391
10uF
2
*
2
1
33
C316
10nF
2
S
AOD472
*
*
AOD472
Dummy
S
47nF
16V,X7R,+/-10%
R479
1.5KOhm
+/-1%
R480
1.2KOhm
Near
ACPI
+/-1%
*
1D1V_MCH
2
Q38
G
1D1V_MCH
VTT_OPS
15K
+/-5%
3.3uH@100KHz
R269
2.2 +/-5%
Q39
*
R478Dummy
+/-5%C451
33
A
L46
ISL6612ACBZA-T
G
VRAM_FB
R268
AOD452
10K +/-5%
1D1V_PHASE
8
7
6
5
1
PHASE
PVCC
VCC
LGATE
2
UGATE
BOOT
PWM
GND
1
1
2
3
4
2
VTT_PWM
PWMVRAM Vref: 0.74V --1.04V/16 steps
G
2.2+/-5%
R581
U17
10V, Y5V, +80%/-20%
C494
10nF
EC52
330uF
+/-20%
1
*
*
2
EC65
EC74
1000uF
1000uF
+/-20% Dummy
+/-20%
C323
10uF
1
*
*
2
EC61
1000uF
+/-20%
*
*
D
EC57
1000uF
+/-20%
S
*
*
*
C502
10uF
C326
0.1uF
16V, Y5V, +80%/-20%
16V, Y5V,+80%~-20%
D
1
*
*
2.5uH@100KHz
2
AOD472
C306
C14
0.1uF
1uF
16V, Y5V, +80%/-20%
2
1
*
R271
G
S
C314
4.7
1
2 0.1uF
+/-5%
16V, Y5V, +80%/-20%
R270
1D8V_STR
L54
R531
2.2
+/-5%
Q56
VRAM_LGATE
*
*
1D8V_PHASE
D
R582 10K
+/-5%
VRAM_OPS
20K
+/-5%
AOD452
2
R477
G
S
2.2
+/-5%
*
VRAM_UGATE R563
4
3
2
Document Number
Rev
A
G43M01S1
Sheet
Monday, August 11, 2008
1
19
of
41
5
4
3
2
1
D
D
C
C
B
B
A
A
FOXCONN PCEG
Title
Blank
Size
Document Number
Custom
Date:
5
4
3
2
Rev
A
G43M01S1
Monday, August 11, 2008
Sheet
1
20
of
41
4
3
2
RED
*
5V_SYS
*
C28
0.1uF
16V, Y5V, +80%/-20%
BAV99
RGB routing
1. from GMCH to the first 150 ohm resistor: 7.5 mils(min. 6 mils spacing )
2. from the first 150 ohm res. to the second 150 ohm resistor: 4 mils
3. from the second 150 ohm resistor to connector: 4 mils
4. spacing minimum 6 mils, 30 mils spacing is recommended
5. R,G,B should be length matched to 700 mils, max. length is 8400 mils
6. R,G,B signals should be ground referenced
C73
0.1uF
16V, Y5V, +80%/-20%
D
R10
3D3V_SYS
*
82nH@100MHz
*
R16
C103
150
0.1uF
+/ -1%
16V, Y5V, +80%/-20%
*
33nH@100MHz
C42
18pF
+/-5%
*
C59
3.3pF
50V, NPO, +/-0.25pF
L15
FB 300 Ohm
*
L10
3
GREEN
GREEN
1
2
Q8
BAV99
5V_SYS
3D3V_SYS
*
82nH@100MHz
*
*
C183
R23
0.1uF
150
16V, Y5V, +80%/-20% +/ -1%
33nH@100MHz
C45
18pF
+/-5%
*
C44
6.8pF
+/-0.5pF
5V_VSYNC
Q12
BAV99
1
5V_HSYNC
2
5V_DDCA_DATA
5V_SYS
2.2K
3
G
2.2K
Q11
2N7002 S
DDCA_DATA
1
+/-5%
1
2
Q6
33
+/-5%
R600
1
2
Q2
BAV99
2
Q3
*
5V_DDCA_DATA
100pF
3D3V_SYS
*
16
17
5
ID0
4
B
3
G
2
R
1
CONN-VGA
33nH@100MHz
C56
18pF
+/-5%
*
C70
3.3pF
50V, NPO, +/-0.25pF
GND
*
C39
6.8pF
+/-0.5pF
C89
5V_SYS
Place one 0.1uF
decoupling cap near the
ESD diodes
5V_VSYNC
The 150 Ohm resistors near VGA connector and
minimizing length to filter. The filters to VGA
connector maximum distance 800 mils.
C
5V_HSYNC 5V_HSYNC
0
+/-5%
3D3V_SYS
*
82nH@100MHz
*
*
C86
R34
0.1uF
150
16V, Y5V, +80%/-20% +/ -1%
0
+/-5%
3D3V_SYS
3
*
BAV99
R233
2
R599
C
12 3V_HSYNC
1
BAV99
100
+/-5%
*
33
BLUE
BLUE
Dummy
*
R234
12 3V_VSYNC
12
Q13
BAV99
3
*
Q10
2N7002
*
R12
*
R48
3
12 DDCA_DATA
D
5V_DDCA_CLK
100
100pF
+/-5%
C88 Dummy
3
R45
*
DDCA_CLK
D
G
12
S
*
L11
DDCA_CLK
VGA
VGA
15 SCL
10 GND
VSYNC
14
9 NC
13 HSYNC
8 GND
12 SDA
7 GND
11 ID1
6 GND
5V_DDCA_CLK
3D3V_SYS
*R55 *R46
D
L_RED
L_GREEN
L_BLUE
*
C60
3.3pF
50V, NPO, +/-0.25pF
*
C83
C91
0.1uF
1uF
16V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
dummy
R11
*
EMI cap. for RGB layer change
12
*
5V_Display
C43
6.8pF
+/-0.5pF
*
5V_SYS
2
Q7
2
1
*
3
RED
*
L9
12
1
1
5
*
*
C58
33pF
dummy
+/-5%
Placed both Resistors close to GMCH
Within 750 mils
W=4 mils, S=10 mils from GMCH to connector
C49
33pF
+/-5%
dummy
3D3V_SYS
DVI-D
*R88
DVI-D Connector
1K
*R91
5V_SYS
U8
TMDS_00P_DVI
TMDS_00N_DVI
C167
C160
0.1uF 16V, X7R, +/-10% EXP_TXP1_DVI_LS
0.1uF 16V, X7R, +/-10% EXP_TXN1_DVI_LS
45
44
IN_D3+
IN_D3-
OUT_D3+
OUT_D3-
16
17
TMDS_01P_DVI
TMDS_01N_DVI
C155
C152
0.1uF 16V, X7R, +/-10% EXP_TXP0_DVI_LS
0.1uF 16V, X7R, +/-10% EXP_TXN0_DVI_LS
42
41
IN_D2+
IN_D2-
OUT_D2+
OUT_D2-
19
20
TMDS_02P_DVI
TMDS_02N_DVI
C143
C141
0.1uF 16V, X7R, +/-10% EXP_TXP3_DVI_LS
0.1uF 16V, X7R, +/-10% EXP_TXN3_DVI_LS
OUT_D1+
OUT_D1-
22
23
TMDS_CLKP_DVI
TMDS_CLKN_DVI
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
2
11
15
21
26
33
40
46
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
THERMAL_PAD
1
5
12
18
24
27
31
36
37
43
49
7
9
8
TMDS_HPD_DVI
DVI_DDCCLK
DVI_DDCDATA
30
28
29
HPD_SINK
SCL_SINK
SDA_SINK
D
HPD_SW
R85
S
G
*R21
47K
**
R129
R143
4.7K
4.7K
R130
R144
PC_0
PC_1
DDC_EN
32
DDC_EN
REXT
470 Ohm +/-1%
RT_EN#
0
6
10
REXT
RT_EN#
0 Dummy PC_0
PC_1
3
4
34
35
PC_0
PC_1
NC_1
NC_2
4.7K
R131
R142
+/-5%
3D3V_SYS
** ** *
3D3V_SYS
Q27
2N7002
HPD_SOURCE
SCL_SOURCE
SDA_SOURCE
0
Dummy
10uF
10V, Y5V, +80%/-20%
SDVO_S_CTRLDATA
R140
0
dummy
12,22 SDVO_CTRLDATA
SDVO_CTRLDATA
3D3V_SYS
2 OI
C
4
C18216V, Y5V, +80%/-20%
0.1uF
12,22 SDVO_CTRLCLK
*
2
3
Q4
BAV99
3
C84
0.1uF
16V, Y5V, +80%/-20%
dummy
*
*
*
*
*
*
*
*
CONN_DVI
C140
C169
C148
C166
C139
C179
C180
C601
C602
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
1uF
Dummy Dummy
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
10V, Y5V, +80%/-20% 22uF
22uF
5V_SYS
6.3V, X5R, +/-10%
6.3V, X5R, +/-10%
TMDS_00P_DVI
R120 1 Dummy
C38
2 150
+/-5%
SDVO_S_CTRLCLK
R128
0
dummy
SDVO_CTRLCLK
3D3V_SYS
1 IO
TMDS_00N_DVI
TMDS_01P_DVI
TMDS_02P_DVI
R108 1 Dummy
C219
2 150
+/-5%
2pF
Dummy
TMDS_01N_DVI
R102 1 Dummy
C599
2 150
+/-5%
2pF
Dummy
TMDS_02N_DVI
2pF
Dummy
TMDS_CLKN_DVI
TMDS_CLKP_DVI R94
VCC 5
*
2pF
Dummy
*
C149
0.1uF
16V, Y5V, +80%/-20%
C600
1 Dummy
2 150
+/-5%
*R90
2.2K
*R89
2.2K
DVI_DDCCLK
DVI_DDCDATA
A
2 OI
C
MUXSEL
4
3D3V_SYS
GND
3D3V_SYS
*R141
GND
*R127
2.2K
74V1G66CTR
FOXCONN PCEG
2.2K
74V1G66CTR
Title
SDVO_S_CTRLCLK
SDVO_S_CTRLDATA
VGA / DVI-D Connector
Size
C
Date:
5
5V_SYS
2
2
*
3
3
B
5V_SYS
Q9
BAV99
3D3V_SYS
VCC 5
*
DVI_DDCDATA
CKT8
Q1
BAV99
3
1 IO
*
DVI_DDCCLK
CKT7
5V_SYS
Q29
A
CKT6
dummy
Recommended Equalization: [PC1,PC0]=01, 4dB
Q28
TMDS_CLKN_DVI
TMDS_HPD_DVI
CKT5
1
HPD_LS
SDVO_S_CTRLCLK
SDVO_S_CTRLDATA
*
C61
C50
1uF
0.1uF
10V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
CKT4
G1
1K
22
IN_D1+
IN_D1-
*
Fuse 1.5A
* * * *
0 dummy
39
38
C108
*
TMDS_02P_DVI
CKT3
1
R145
13
14
TMDS_02N_DVI
CKT2
1
*R152
OUT_D4+
OUT_D4-
5V_DVI_CON
TMDS_CLKP_DVI
2 FB 300 Ohm
2
*
1D1V_MCH
IN_D4+
IN_D4-
L12
1
1
22 EXP_TXP3_DVI
22 EXP_TXN3_DVI
48
47
5V_Display
2
22 EXP_TXP0_DVI
22 EXP_TXN0_DVI
0.1uF 16V, X7R, +/-10% EXP_TXP2_DVI_LS
0.1uF 16V, X7R, +/-10% EXP_TXN2_DVI_LS
F2
2
22 EXP_TXP1_DVI
22 EXP_TXN1_DVI
*
PS8101QFN48G
C177
C173
** ** ** **
22 EXP_TXP2_DVI
22 EXP_TXN2_DVI
B
OE#
1
25
1
S
1K
dummy
2N7002
CKT1
1
1K G
2
*
R146
MUXSEL
CKT17
CKT9
CKT18
CKT10
CKT19
CKT11
CKT20
CKT12
CKT21
CKT13
CKT22
CKT14
CKT23
CKT15
CKT24
CKT16
G2
D
OE#
Q26
22
TMDS_00N_DVI
TMDS_01N_DVI
TMDS_00P_DVI
TMDS_01P_DVI
4
3
2
Document Number
Rev
A
G43M01S1
Sheet
Monday, August 11, 2008
1
21
of
41
5
4
3D3V_SB
3
3D3V_SYS 12V_SYS
12V_SYS
2
1
3D3V_SYS
19,23,30,31,33
19,23,30,31,33
D
12 PEG_PINB4
SMB_CLK_RESUME
SMB_DATA_RESUME
23,30
WAKEJ
WAKEJ
12V
12V
RSVD1
GND
SMCLK
SMDAT
GND
3.3V
JTAG1
3.3VAUX
WAKE#
PRSNT1#
12V
12V
GND
JTAG2
JTAG3
JTAG4
JTAG5
3.3V
3.3V
PWRGD
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
*
PCI-E1_16X
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
R177
0
Dummy
DDPC_CTRLCLK
12
PEG_PRSNT1
D
Near connector
ICH_G_PLTRSTJ
ICH_G_PLTRSTJ
29,30
ICH_G_PLTRSTJ
C605
*
0.1uF
Dummy
KEY
C207
C208
**
EXP_TXP0_GFX
EXP_TXN0_GFX
0.1uF 16V, X7R, +/-10%
0.1uF 16V, X7R, +/-10%
EXP_TXP0_GFX_C
EXP_TXN0_GFX_C
SDVO_CTRLCLK
12,21 SDVO_CTRLCLK
B12
B13
B14
B15
B16
B17
B18
RSVD2
GND
HSOP0
HSON0
GND
PRSNT2_B17#
GND
GND
REFCLK+
REFCLKGND
HSIP0
HSIN0
GND
A12
A13
A14
A15
A16
A17
A18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
HSOP1
HSON1
GND
GND
HSOP2
HSON2
GND
GND
HSOP3
HSON3
GND
RSVD3
PRSNT2_B31#
GND
RSVD5
GND
HSIP1
HSIN1
GND
GND
HSIP2
HSIN2
GND
GND
HSIP3
HSIN3
GND
RSVD6
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
16V, Y5V, +80%/-20%
CK_PE_100M_P_16PORT
CK_PE_100M_N_16PORT
EXP_RXP0
EXP_RXN0
CK_PE_100M_P_16PORT 7
CK_PE_100M_N_16PORT 7
EXP_RXP0
EXP_RXN0
12
12
3D3V_SYS
EXP_TXP3_GFX
EXP_TXN3_GFX
C223
C225
0.1uF 16V, X7R, +/-10%
0.1uF 16V, X7R, +/-10%
EXP_TXP3_GFX_C
EXP_TXN3_GFX_C
SDVO_CTRLDATA
12
12
EXP_TXP6
EXP_TXN6
12
12
EXP_TXP7
EXP_TXN7
12
EXP_TXP8
EXP_TXN8
12
12
EXP_TXP9
EXP_TXN9
12
12
EXP_TXP10
EXP_TXN10
12
12
EXP_TXP11
EXP_TXN11
12
12
EXP_TXP12
EXP_TXN12
12
12
EXP_TXP13
EXP_TXN13
12
12
EXP_TXP14
EXP_TXN14
B
12
12
EXP_TXP15
EXP_TXN15
EXP_TXP4_C
EXP_TXN4_C
EXP_TXP5
EXP_TXN5
C256
C253
0.1uF 16V, X7R, +/-10%
0.1uF 16V, X7R, +/-10%
EXP_TXP5_C
EXP_TXN5_C
EXP_TXP6
EXP_TXN6
C263
C262
0.1uF 16V, X7R, +/-10%
0.1uF 16V, X7R, +/-10%
EXP_TXP6_C
EXP_TXN6_C
EXP_TXP7
EXP_TXN7
C269
C268
0.1uF 16V, X7R, +/-10%
0.1uF 16V, X7R, +/-10%
EXP_TXP7_C
EXP_TXN7_C
R241
EXP_PRSNT
12
12
0.1uF 16V, X7R, +/-10%
0.1uF 16V, X7R, +/-10%
EXP_TXP8
EXP_TXN8
EXP_TXP9
EXP_TXN9
EXP_TXP10
EXP_TXN10
EXP_TXP11
EXP_TXN11
EXP_TXP12
EXP_TXN12
EXP_PRSNT_C
0
C281
C283
C284
C288
C298
C289
C301
C299
C305
C307
0.1uF 16V, X7R, +/-10%
0.1uF 16V, X7R, +/-10%
0.1uF 16V, X7R, +/-10%
0.1uF 16V, X7R, +/-10%
0.1uF 16V, X7R, +/-10%
0.1uF 16V, X7R, +/-10%
0.1uF 16V, X7R, +/-10%
0.1uF 16V, X7R, +/-10%
0.1uF 16V, X7R, +/-10%
0.1uF 16V, X7R, +/-10%
EXP_TXP8_C
EXP_TXN8_C
EXP_TXP9_C
EXP_TXN9_C
EXP_TXP10_C
EXP_TXN10_C
EXP_TXP11_C
EXP_TXN11_C
EXP_TXP12_C
EXP_TXN12_C
EXP_TXP13
EXP_TXN13
C312
C311
0.1uF 16V, X7R, +/-10%
0.1uF 16V, X7R, +/-10%
EXP_TXP13_C
EXP_TXN13_C
EXP_TXP14
EXP_TXN14
C322
C321
0.1uF 16V, X7R, +/-10%
0.1uF 16V, X7R, +/-10%
EXP_TXP14_C
EXP_TXN14_C
EXP_TXP15
EXP_TXN15
C333
C332
0.1uF 16V, X7R, +/-10%
0.1uF 16V, X7R, +/-10%
R300
12 DDPC_CTRLDATA
EXP_TXP15_C
EXP_TXN15_C
*
EXP_TXP5
EXP_TXN5
C244
C248
*
** ** ** **
12
12
EXP_TXP4
EXP_TXN4
0
Dummy
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
HSOP4
HSON4
GND
GND
HSOP5
HSON5
GND
GND
HSOP6
HSON6
GND
GND
HSOP7
HSON7
GND
PRSNT2_B48#
GND
RSVD7
GND
HSIP4
HSIN4
GND
GND
HSIP5
HSIN5
GND
GND
HSIP6
HSIN6
GND
GND
HSIP7
HSIN7
GND
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
HSOP8
HSON8
GND
GND
HSOP9
HSON9
GND
GND
HSOP10
HSON10
GND
GND
HSOP11
HSON11
GND
GND
HSOP12
HSON12
GND
GND
HSOP13
HSON13
GND
GND
HSOP14
HSON14
GND
GND
HSOP15
HSON15
GND
PRSNT2_B81#
RSVD4
RSVD8
GND
HSIP8
HSIN8
GND
GND
HSIP9
HSIN9
GND
GND
HSIP10
HSIN10
GND
GND
HSIP11
HSIN11
GND
GND
HSIP12
HSIN12
GND
GND
HSIP13
HSIN13
GND
GND
HSIP14
HSIN14
GND
GND
HSIP15
HSIN15
GND
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
EXP_RXP2
EXP_RXN2
EXP_RXP1
EXP_RXN1
12
12
EXP_RXP2
EXP_RXN2
*
*
*
*
*
*
C224
C215
C227
C218
C213
C228
1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
10V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
12
12
6
17
22
27
34
50
55
VDD
VDD
VDD
VDD
VDD
VDD
VDD
EXP_RXP3_SW
EXP_RXN3_SW
12
12
EXP_RXP4
EXP_RXN4
EXP_RXP5
EXP_RXN5
EXP_RXP6
EXP_RXN6
EXP_RXP7
EXP_RXN7
EXP_RXP8
EXP_RXN8
12
12
EXP_RXP4
EXP_RXN4
12
12
EXP_RXP5
EXP_RXN5
12
12
12
12
12
12
EXP_RXP6
EXP_RXN6
12
12
EXP_RXP7
EXP_RXN7
12
12
EXP_RXP8
EXP_RXN8
EXP_RXP10
EXP_RXN10
EXP_RXP11
EXP_RXN11
EXP_RXP12
EXP_RXN12
EXP_RXP13
EXP_RXN13
EXP_RXP14
EXP_RXN14
EXP_RXP15
EXP_RXN15
PEG_PINB4
R193
0
PEG_PRSNT1
R186
0
dummy
12
12
MUXSEL
R182
0
dummy
12
12
12
12
EXP_RXP11
EXP_RXN11
12
12
EXP_RXP12
EXP_RXN12
12
12
EXP_RXP13
EXP_RXN13
12
12
EXP_RXP14
EXP_RXN14
12
12
EXP_RXP15
EXP_RXN15
12
12
9
10
EXP_TXN0
EXP_TXP0
IN_0+
IN_0IN_1+
IN_1IN_2+
IN_2IN_3+
IN_3-
PWRGD_3V
R183
0
dummy
OUT+
OUT-
14
15
X+
X-
MUXSEL
18
SEL
LE#
19
LE#
EXP_RXP3
EXP_RXN3
*R184
0
12,19,23,24,29
EXP_RXP10
EXP_RXN10
7
8
EXP_TXN1
EXP_TXP1
12
13
1K
12
12
EXP_RXP9
EXP_RXN9
4
5
EXP_TXN2
EXP_TXP2
*R189
21
EXP_RXP9
EXP_RXN9
2
3
EXP_TXN3
EXP_TXP3
3D3V_SYS
*
EXP_TXP2_GFX_C
EXP_TXN2_GFX_C
U15
1
0.1uF 16V, X7R, +/-10%
0.1uF 16V, X7R, +/-10%
EXP_RXP1
EXP_RXN1
2
C220
C222
** ** ** ** ** ** ** **
C
EXP_TXP4
EXP_TXN4
EXP_TXP1_GFX_C
EXP_TXN1_GFX_C
EXP_TXP2_GFX
EXP_TXN2_GFX
12,21 SDVO_CTRLDATA
12
12
0.1uF 16V, X7R, +/-10%
0.1uF 16V, X7R, +/-10%
* *
** ** **
C211
C212
*
EXP_TXP1_GFX
EXP_TXN1_GFX
1
11
16
20
21
28
GND
GND
GND
GND
GND
GND
TX_0+
TX_0-
54
53
EXP_TXN3_GFX
EXP_TXP3_GFX
TX_1+
TX_1-
52
51
EXP_TXN2_GFX
EXP_TXP2_GFX
TX_2+
TX_2-
47
46
EXP_TXN1_GFX
EXP_TXP1_GFX
TX_3+
TX_3-
45
44
EXP_TXN0_GFX
EXP_TXP0_GFX
D_0+
D_0-
43
42
EXP_TXN3_DVI 21
EXP_TXP3_DVI 21
D_1+
D_1-
41
40
EXP_TXN2_DVI 21
EXP_TXP2_DVI 21
D_2+
D_2-
39
38
EXP_TXN1_DVI 21
EXP_TXP1_DVI 21
D_3+
D_3-
37
36
EXP_TXN0_DVI 21
EXP_TXP0_DVI 21
RX_0+
RX_0-
33
32
RX_1+
RX_1-
31
30
AUX+
AUX-
26
25
HPD
24
NC
23
GND
GND
GND
GND
GND
GND_PAD
29
35
48
49
56
57
C
EXP_RXP3_SW
EXP_RXN3_SW
HPD_SW
21
PI3PCIE2612-AZFE
B
Slot-PCIE-16X
Change to another part.
050608
12V_SYS
*
EC30
470uF
16V, +/-20%
3D3V_SYS
*
C164
0.1uF
16V, Y5V, +80%/-20%
*
EC37
1000uF
+/-20%
3D3V_SB
*
C186
0.1uF
16V, Y5V, +80%/-20%
*
C200
0.1uF
16V, Y5V, +80%/-20%
A
A
FOXCONN PCEG
Title
PCI-E16X Slot / GenII Switch
Size
C
Date:
5
4
3
2
Document Number
Rev
A
G43M01S1
Sheet
Monday, August 11, 2008
1
22
of
41
5
4
3
2
1
3D3V_SYS
ICH10
ICH10
C
1D5V_PE_ICH
24.9 DMI_COMP_ICH
+/-1%
R452
AF28
AF30
DMIRCOMPO
DMICOMPI
U26
U25
DMICLK100N
DMICLK100P
CK_DMI_N_ICH
CK_DMI_P_ICH
7 CK_DMI_N_ICH
7 CK_DMI_P_ICH
USBRBIASN
USBRBIASP
USBRBIAS_ICH R464
AG3
CK_48M_ICH
Back Panel
36
If integrated LAN is not used, recommend to connect
LAN_RST# to GND via a 8.2 kΩ to 10 kΩ pull-down
resistor
SRTCRSTB
C346
0.1uF
24,32
RTCRSTJ
36
35
CK_48M_ICH
7
27 HSO_P2_LAN
0
Dummy
Dummy
0.1uF HSO_P3
16V, X7R, +/-10%
C402
HSO_N2
0.1uF
16V, X7R, +/-10%
C403
HSO_P2
0.1uF
16V, X7R, +/-10%
+/-5%
0
+/-5%
ICH9 Hardware Straps
3.3KICH_AUD_SDOUT_R
R466
To LAN
Dummy
3.3K ICH_AUD_SYNC_R
R468
SPI_MOSI
SPI_MISO
SPI_CS0B
SPI_CLK
SPI_CS1B/GPIO58/CLGP6
A13
B13
G17
F17
T8
C13
AK28
AE24
F20
SLP_S3B
SLP_S4B
SLP_S5B/GPIO63
SLP_MB
CK_PWRGD
GP72
DPRSTPB
DPSLPB
TP3
4 of 6
ICH_GPIO8
WOL_ONLY
CPU_SKTOCC#
ICH_GPIO12
L_PMEJ
ICH_GPIO14
0
R393
Dummy
SEC request
070908
HDA_SDOUT(Bit 1)
HDA_SYNC(Bit 0)
11 = 1 x4, Port 1 (x4)
10 = Reserved
01 = Reserved
00 = 4 x1s
R594
R494
10K
R516
Dummy
10K
R515
PROCHOTJ
10K
Dummy
Q52
B Dummy
MMBT3904-7-F
ICH_THRM
29
ICH_GPIO56
R396
10K
ICH_GPIO14
R394
10K
TPM_PHY_PRNT
R395
10K
Dummy
0
dummy
*
C354
1uF
dummy
Dummy
Q66
12,19,22,24,29
SPKR
32
7,10,32
12,29,34
22,30
C
29
7,19
CK_PWRGD
0
0
PM_DPRSTP#
DPSLP#
TP_ICH_3
7
10,12
10
TP63
ICH9_TP0_PU
CPU_SKTOCC#
SMBALERTJ
ICH_GPIO8
*1
2
4
6
8
3
5
7
10K Ohm
+/-5%
ICH10 Consumer Family: Pin may only be used as TP0.
Test Point 0: This signal must have an external pull-up to
VccSus3_3.
ICH10 Corporate Family: Pin can be used as GPIO72
VCCRTC
CRB use 390K
R334
0 SMB_DATA_RESUME
dummy
SMLINK0
R328
0 SMB_CLK_RESUME
dummy
R360
330K
R382
330K
INTVRMEN
B
ICH_LAN100SLP_EN
INTVRMEN: enable internal VccSus1_05, VccSus1_5 and
VccCL1_5 regulators when connect to VccRTC
LAN100_SLP: enable internal VccLAN1_05 and
VccCL1_05 regulators when connect to VccRTC
3D3V_SB
B
2
A
R299
10K
Dummy
C337
0.1uF
Need to be tuning
+/-5%
WAKEJ
R419
10K
L_PMEJ
R287
10K
Dummy
R367
1K
SLP_S3J
ICH_SPI_HOLDJ
ICH_SPI_WPJ
ICH_AUD_BCLK
R296
3D3V_SB
R319
1K
dummy
Q41
B Dummy MMBT3904-7-F
SPI
*
3D3V_SYS
Dummy
C457
10pF
50V, NPO, +/-5%
R358
1M
R321
1K
INTRUDERJ
A
ICH_VRMPWRGD
1K
1K
VCCRTC
dummy
16V, Y5V, +80%/-20%
Dummy
R290
8,10 P_VRM_GD
ICH_SPI_CS1J
1.dummy for second SPI???
2.SPI_CS1#: internal pull up
C
MMBT3904-7-F
B DummyQ42
*
C335
1uF
R320
100KOhm
2
R318
1K
*
1
C
C340
0.1uF
Note:
1.Ensure that VRMPWRGD falls below Vih levels
before the next SLP_S3# deassertion
2.The signal power type of VRMPWRGD is SUSPEND.
E
*
8
7
3
4
R298
10K
dummy
E
to ICH9 within 500 mils
SPI_SOCKET
R289
15Ohm +/-1%
1 CS#
VCC
R292
15Ohm +/-1%
6 SCK
HOLD#
R294
15Ohm +/-1%
5 SI
WP#
R324
15Ohm
2 SO
GND
+/-1%
close to SPI within 500 mils
Socket
*
C336
0.1uF
1K
3D3V_SB
C
*
3D3V_SYS
1
1
D22
3
BAV99
*R330
2.2K
3D3V_SYS
R399
R326
4.7K
D21
LS4148-F
3D3V_SYS
Check resistor value??
***
PWRGD_3V
12
+/-5%
Close to ROM power pin.
012008
16V, Y5V, +80%/-20%
VTT_OUT_RIGHT
ICH_GPIO8
R297
1K
Dummy
SPI ROM
8,10 P_VRM_GD
0
ICH10 -1
Size
C
Date:
4
FOXCONN PCEG
Title
R295
W25X80VDAIZ
5
29
39
34
3D3V_SB
All RTC-well inputs(RSMRST#,RTCRST#,INTRUDER#,PWROK)
must either pull up to VccRTC or pulled down
to ground while in G3 for preventing from
floating in G3 and will prevent IccRTC leakage
that can cause excessive
coin-cell drain.
A
PWRBTNJ
ICH_RIJ
LPCPDJ
TP67
FP_RSTJ
PLTRSTJ
WAKEJ
SLP_S3J
SLP_S4J
TP64
CK_PWRGD
ICH9_TP0_PU
R496
R462
*R362
47K
E MMBT3906
C
for reset issue when testing
place near ICH9
close
ICH_SPI_CS0J
ICH_SPI_CLK
ICH_SPI_MOSI
ICH_SPI_MISO
ICH_SYNCJ
SLP_S3J
SLP_S4J
ICH_RSMRSTJ
0
2
1
C368
10pF
50V, NPO, +/-5%
R398
2
3
4
*
3D3V_SYS
R463
1K
dummy
1K
SMLINK1
WOL_ONLY
2
1
*
29
PWRBTNJ
ICH_RIJ
LPCPDJ
TP_SUSCLK
FP_RSTJ
PLTRSTJ
WAKEJ
INTRUDERJ
PWRGD_3V
ICH_RSMRSTJ
INTVRMEN
SPKR
**
R539
R361
1K
C359
10pF
50V, NPO, +/-5%
10
ICH_THRM
3D3V_SB
10K
X2_1
19,29 SIO_RSMRSTJ
CPU_PWRGD
3D3V_SB
R415
TPM Physical
R414
Presence (PP) Strap
Pullup: PP Asserted
Pulldown: PP Deasserted
MMBT3904-7-F
E
3D3V_SB
10K
Dummy
R418
100KOhm
+/-1%
9
GP33: Fab-B change
Low: Disable ME feature
High: Enable ME feature(defaul)
1K
Dummy
ICH_GPIO56
TPM_PHY_PRNT
CPU_PWRGD
ICH_LAN100SLP_EN
ICH_THRM
ICH_VRMPWRGD
3D3V_SB
X2
XTAL-32.768kHz
2
1
10
29
CK_PCI_STOP 7
ICH_SPI_WPJ
ICH_RTCX1
Crystal Retainer
L_PMEJ
CK_CPU_STOP 7
3D3V_SYS
Q55
B Dummy
R417
CPU_SKTOCC#
RN55
ICH_GPIO12
Dummy
10M
27
TP66
CPU_GTLREF_CTRL2
3D3V_SYS
ICH_RTCX2
R420
LAN_PMEJ
Has relation with HDA_SDOUT strap
10
B
29
U13
C
27 HSO_N2_LAN
* *R482
R473
C406
C26
B26
E25
G23
F23
ICH_SPI_CS1J
3D3V_SYS for W/O HDMI
1D5V_ICH 3D3V_SYS
To PCI-E x1 Slot 1
SMLINK0
SMLINK1
10K
10K
C
30 HSO_P3_SLOT
0.1uF HSO_N3
16V, X7R, +/-10%
C16
H16
E16
F18
A15
B15
ICH Enable Strap(SPI_MOSI)
Pullup: Enable TPM
Float: Disable TPM
**
* * * *
C405
SMBALERTJ
ICH_SPI_MOSI
ICH_SPI_MISO
ICH_SPI_CS0J
ICH_SPI_CLK
U13
30 HSO_N3_SLOT
A21
B21
A25
H20
R332
R333
22.6 +/-1%
USBRBIAS connection
4 mils width, length no longer than 500 mils
Trace tied together close to pins.
F25
E14
C21
G15
H14
E13
F15
F14
G14
ICH_RTCX1
ICH_RTCX2
RTCRSTJ
SRTCRSTB
19,22,30,31,33 SMB_CLK_RESUME
19,22,30,31,33 SMB_DATA_RESUME
9 CPU_GTLREF_CTRL1
3D3V_SB
27
10K LAN_PWROK
R400
VCCRTC
OF 6
ALL AC Coupling caps. should be close to ICH10
33
33
Back Panel with LAN
USB_OCJ_BACK_LAN
AG1
AG2
R467
R469
AH3
AJ1
AK3
AH4
AH1
AJ3
ICH_AUD_SDOUT_R AJ2
ICH_AUD_SYNC_R
AK1
M5
PECI_RQT
D
A20
A18
C17
A8
A19
A9
C15
M2
K1
AF5
A14
B18
C11
A11
G18
K2
AF6
AH5
L1
F16
C12
AD23
E21
AK26
C22
AH25
T3
G19
R1
R5
F19
C14
E20
G21
C25
F22
E23
N8
MISC
28 ICH_AUD_SDOUT
28 ICH_AUD_SYNC
7 CK_14M_ICH
*
USB_OCJ_BACK
39
33
+/-5%
28 ICH_AUD_SDIN2
USB_OCJ_FRONT_1_2
USB_OCJ_FRONT_3
R475
R465
N7
GP8
GP9_WOL_EN
GP10/CLGPIO1
GP12
HDA_BIT_CLK
GP13
HDA_RSTB
GP14_CLGPIO2
HDA_SDI0
STP_PCIB/GP15
HDA_SDI1
GP16
HDA_SDI2
GP18
HDA_SDI3
GP20
HDA_SD0UT
GP24/MEM_LED
HDA_SYNC
STP_CPUB/GP25
CLK14
GP26_S4_STATEB
GP27_QRT_STATE0
GP28_QRT_STATE1
GLAN_CLK
GP32
LAN_RSTSYNC
GP33
LAN_RSTB
GP34
LAN_RXD0
SATACLKREQB_GP35
LAN_RXD1
GP56
LAN_RXD2
CLGPIO5_GP57
LAN_TXD0
CPUPWRGD
LAN_TXD1
LAN100_SLP
LAN_TXD2
THRMB
VRMPWRGD
RTCX1
MCH_SYNCB
RTCX2
PWRBTNB
RTCRSTB
RIB
SRTCRSTB
SUS_STATB/LPCPD
SUSCLK
SYS_RESETB
SMBALERTB_GP11
PLTRSTB
SMBCLK
WAKEB
SMBDATA
INTRUDERB
LINKALERTB/GP60/CLGPIO4
PWROK
SMLINK0
RSMRSTB
SMLINK1
INTVRMEN
SPKR
LPC
28 ICH_AUD_BCLK
28 ICH_AUD_RSTJ
Front Panel 3
GP0
AUDIO
Front Panel 2
L_DRQ0J
L_FRAMEJ
*
29
29,34
LDRQ1B_GP23
FWH0/LAD_0
FWH1/LAD_1
FWH2/LAD_2
FWH3/LAD_3
LDRQ0B
FWH4/LFRAMEB
LAN
USB
OC0B_GP59
OC1B_GP40
OC2B_GP41
OC3B_GP42
OC4B_GP43
OC5B_GP29
OC6B_GP30
OC7B_GP31
OC8B_GP44
OC9B_GP45
OC10B_GP46
OC11B_GP47
CLK48
2
Front Panel 1
R359
180K
P5
N3
P7
R7
N2
N1
N5
M1
P3
R6
T7
P1
10K
J3
K3
H1
M7
J1
L6
L5
L_AD0
L_AD1
L_AD2
L_AD3
RTC
HSI_N3
HSI_P3
27
27
27
27
35
35
35
35
35
35
35
35
36
36
36
36
36
36
36
36
36
36
36
36
SMB
To PCI-E x1 Slot 1 30
30
HSI_N2
HSI_P2
HSO_N2
HSO_P2
HSI_N3
HSI_P3
HSO_N3
HSO_P3
PER6N_GLAN_RXN
PER6N_GLAN_RXP
PER6N_GLAN_TXN
PER6N_GLAN_TXP
PER1N
PER1P
PET1N
PET1P
PER2N
PER2P
PET2N
PET2P
PER3N
PER3P
PET3N
PET3P
PER4N
PER4P
PET4N
PET4P
PER5N
PER5P
PET5N
PET5P
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
For Intel QST function
R392
Dummy
29,34 L_AD[3..0]
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USB10N
USB10P
USB11N
USB11P
AD6
AD5
AE3
AE2
AD1
AD2
AB6
AB5
AC3
AC2
AB1
AB2
Y6
Y5
AA3
AA2
Y1
Y2
V6
V5
W2
W3
V1
V2
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
SP1
HSI_N2
HSI_P2
D29
D30
E26
E28
P30
P29
R26
R28
M30
M29
N26
N28
K30
K29
L26
L28
H30
H29
J26
J28
F30
F29
G26
G28
DMIORXN
DMIORXP
DMIOTXN
DMIOTXP
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
E
27
27
To LAN
W28
W26
V30
V29
AA26
AA28
Y30
Y29
AC26
AC28
AB30
AB29
AF26
AE26
AD29
AD30
DMI
D
DMI_TXN0
DMI_TXP0
DMI_RXN0
DMI_RXP0
DMI_TXN1
DMI_TXP1
DMI_RXN1
DMI_RXP1
DMI_TXN2
DMI_TXP2
DMI_RXN2
DMI_RXP2
DMI_TXN3
DMI_TXP3
DMI_RXN3
DMI_RXP3
DMI_TXN0
DMI_TXP0
DMI_RXN0
DMI_RXP0
DMI_TXN1
DMI_TXP1
DMI_RXN1
DMI_RXP1
DMI_TXN2
DMI_TXP2
DMI_RXN2
DMI_RXP2
DMI_TXN3
DMI_TXP3
DMI_RXN3
DMI_RXP3
PCI-E
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
3
2
Document Number
Rev
A
G43M01S1
Sheet
Monday, August 11, 2008
1
23
of
41
5
4
3
2
1
3D3V_SYS
CL_CLK
12
CL_DATA
24.9 +/-1%
A29
B29
G22
C18
H21
E19
C27
A16
T6
B16
G20
CL_VREF_ICH
12
PWRGD_3V
CL_RST
CL_RST
**
12,19,22,23,29
R508Dummy
0
+/-5%
R510Dummy
0
+/-5%
**
33 ICH_FANOUT1_CPU
33 ICH_FANOUT2_SYS1
FANIN1_ICH
R517Dummy
0
R533Dummy
0
+/-5% FANIN2_ICH
+/-5% FANIN3_ICH
ICH_GPIO7_PU
33 ICH_FANIN1_CPU
33 ICH_FANIN2_SYS1
GLAN_COMPO
GLAN_COMPI
CL_CLK0
TP5
CL_DATA0
TP4
CL_VREF0
TP6
CLPWROK
TP7
CL_RST0b
AJ21
AJ22
AK22
PWM0
PWM1
PWM2
AH21
AK21
AH22
AK23
GP17_TACH0
GP1_TACH1
GP6_TACH2
GP7_TACH3
AK25
AE20
AE21
AE22
AF22
AD21
ICH_GPIO21_PU
ICH_GPIO19_PU
ICH_GPIO36_PU
ICH_GPIO37_PU
SATA4GP_PU
SATA5GP_PU
Stuff when using ICH9 FSC
FANIN2_ICH
*
C464
47nF
C19
16V,X7R,+/-10%
Dummy
SST
A20GATE
A20Mb
P8
AJ28
IGNNEb
INT3_3VB
INTb
INTR
FERRb
NMI
RCINb
SERIRQ
SMIb
STPCLKb
THRMTRIPB
PECI
AC22
M3
AE23
AH27
AJ27
AF24
L3
N6
AH26
AJ29
AD24
AC23
-When unused all PWM[2:0], SST and
PECI may be left unconnected.
Refer to DG1.2
For 3pin Fan only.
ICH_GPIO22_PU
ICH_GPIO38_PU
ICH_GPIO39_PD
ICH_GPIO48_PU
R514
C
AJ24
AK24
AH23
AD20
AJ25
2.2K
dummy
GP22_SCLOCK
GP38_SLOAD
GP39_SDATAOUT0
GP48_SDATAOUT1
GPIO49
3 OF 6
SATA_LED
CK_SATA_100M_N_ICH 7
CK_SATA_100M_P_ICH 7
R484
10nF
10nF
25V, X7R, +/-10%
25V, X7R, +/-10%
SATA_RXN0 C544
SATA_RXP0 C548
10nF
10nF
25V, X7R, +/-10%
25V, X7R, +/-10%
SATA_TXP1 C520
SATA_TXN1 C530
10nF
10nF
25V, X7R, +/-10%
25V, X7R, +/-10%
SATA_RXN1 C534
SATA_RXP1 C538
10nF
10nF
25V, X7R, +/-10%
25V, X7R, +/-10%
SATA_TXP2 C519
SATA_TXN2 C529
10nF
10nF
25V, X7R, +/-10%
25V, X7R, +/-10%
SATA_RXN2 C537
SATA_RXP2 C541
10nF
10nF
25V, X7R, +/-10%
25V, X7R, +/-10%
SATA_TXP3 C518
SATA_TXN3 C528
10nF
10nF
25V, X7R, +/-10%
25V, X7R, +/-10%
SATA_RXN3 C536
SATA_RXP3 C540
10nF
10nF
25V, X7R, +/-10%
25V, X7R, +/-10%
SATA_TXP4 C591
SATA_TXN4 C594
10nF
10nF
Dummy
Dummy
25V, X7R, +/-10%
25V, X7R, +/-10%
SATA_RXN4 C593
SATA_RXP4 C592
10nF
10nF
Dummy
Dummy
25V, X7R, +/-10%
25V, X7R, +/-10%
SATA_TXP5 C595
SATA_TXN5 C598
10nF
10nF
Dummy
Dummy
25V, X7R, +/-10%
25V, X7R, +/-10%
SATA_RXN5 C597
SATA_RXP5 C596
10nF
10nF
Dummy
Dummy
25V, X7R, +/-10%
25V, X7R, +/-10%
24.9 +/-1%
A20GATE
A20MJ
9
10
10
10
29
29,34
10
10
10
10,29
R383
3.24KOhm
+/-1%
0.405V
ICH_GPIO19_PU
R509
10K
ICH_GPIO21_PU
R493
10K
ICH_GPIO36_PU
R538
10K
ICH_GPIO37_PU
R537
10K
8
9
1
2
3
4
5
6
7
SATA_1
CONN-SATA
8
9
1
2
3
4
5
6
7
SATA_2
CONN-SATA
D
8
9
1
2
3
4
5
6
7
SATA_3
CONN-SATA
8
9
SATA_4
CONN-SATA
1 Dummy
2
3
8
4
5
9
6
7
SATA_5
CONN-SATA
1 Dummy
2
3
8
4
5
9
6
7
SATA_6
CONN-SATA
C
For SEC spec change for EV2 stage
3D3V_SYS
3D3V_CL
1
2
3
4
5
6
7
29
10
10
INITJ
INTR
FERRJ
NMI
KBRSTJ
SERIRQ
SMIJ
STPCLKJ
THERMTRIPJ
PECI
0
Dummy
32
Fab-B change
0320
IGNNEJ
R458
HDD_LED
SATA_TXP0 C514
SATA_TXN0 C517
** **
GP21_SATA0GP
GP19_SATA1GP
GP36_SATA2GP
GP37_SATA3GP
SATA4GP
SATA5GP
SATALEDB
SATARBIASN
SATABIASP
HOST
12
SATA
R426
D
D14
LS4148-F
C
A
** **
SATA_LED
SATARBIAS_ICH
1D5V_PE_ICH
R476
10K
** **
AE7
AK6
AJ6
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATACLKN
SATACLKP
4 mils width, length no longer than 500 mils
Trace tied together close to pins.
** **
SATA_RXN0
SATA_RXP0
SATA_TXN0
SATA_TXP0
SATA_RXN1
SATA_RXP1
SATA_TXN1
SATA_TXP1
SATA_RXN2
SATA_RXP2
SATA_TXN2
SATA_TXP2
SATA_RXN3
SATA_RXP3
SATA_TXN3
SATA_TXP3
SATA_RXN4
SATA_RXP4
SATA_TXN4
SATA_TXP4
SATA_RXN5
SATA_RXP5
SATA_TXN5
SATA_TXP5
CK_SATA_100M_N_ICH
CK_SATA_100M_P_ICH
** **
AK17
AJ17
AK19
AJ19
AJ15
AK15
AH16
AF16
AJ13
AK13
AH14
AF14
AJ11
AK11
AF12
AH12
AJ9
AK9
AF10
AH9
AJ7
AK7
AF8
AH7
AF18
AF19
** **
ICH10
CL_VREF_ICH
1
*
C369
0.1uF
16V, Y5V, +80%/-20%
FSB_VTT
**
2
R384
453
+/-1%
4 mils width, 10 mils spacing
place cap. near pin
R513
62
THERMTRIPJ
R495
62
FERRJ
B
B
3D3V_SYS
3D3V_SYS
R488
R534
10K
10K
R490
10K
SATA4GP_PU
R535
10K
SATA5GP_PU
FANIN1_ICH
U13_1
8D 8
7 7
FANIN2_ICH
Empty when using ICH9 FSC
R489
10K
FANIN3_ICH
R491
10K
ICH_GPIO7_PU
R512
10K
ICH_GPIO22_PU
R492
10K
ICH_GPIO38_PU
R536
10K
R511
10K
Dummy
Refer to DG1.2
If not used, pull up to VCC3_3.
ICH_GPIO39_PD
3 3
4 B4
Heatsink
3D3V_SB
VCCRTC
Q33
BAT54C
VCCRTC_SIO
R507
10K
R265
ICH_GPIO48_PU
C
CLIP2S
1
width 20 mils
1
D7
CLIP4S
1
2
2
Clip_2P
Clip_2P
3
A
2
1K
R173
20K
+/-1%
SD103AW
BAT_1
A
R178
1K
LITHIUM BATT
*
C210
1uF
10V, X5R, +/-10%
A
RTCRSTJ
CR2032
*
+
Battery
RTCRSTJ
23,32
C217
1uF
10V, X5R, +/-10%
BAT
For battery cell.
Battery Holder
-
FOXCONN PCEG
Title
ICH10 -2
Size
C
Date:
5
4
3
2
Document Number
Rev
A
G43M01S1
Sheet
Monday, August 11, 2008
1
24
of
41
5
4
3
2
1
REF5V_SUS
Del 3D3V_CL control circuit
3D3V_CL
VccLAN1_05_2
VccLAN1_05_1
C30
C29
C28
B30
VccGLAN1_5_1
VccGLAN1_5_2
VccGLAN1_5_3
VccGLAN1_5_4
need to check???
3D3V_SB
CBEJ0
CBEJ1
CBEJ2
CBEJ3
VCCSUSHDA
31
31
31
31
Q51 AME8800LEETZ
3 Dummy
V_IN
V_OUT 2
C472
2.2uF
6.3V, Y5V, +80%/-20%
Dummy
STUFF for HDMI
*
R501
0
Dummy
VccSATAPLL LC Filter
*
VCCSATAPLL
VccGLANPLL LRC Filter
1D5V_ICH
10V, Y5V, +80%/-20%
1
*
C467
10uF
C461
1uF
2
L0805 10uH
10V, Y5V, +80%/-20%
*
L50
1
R424
2
VCCGLANPLL
0
1uH@10MHz
*
Rated at least 100mA
C392
10uF
*
C390
2.2uF
6.3V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
Place LC near pin AK20
Place LRC near pin A25
1D1V_ICH
C393
0.1uF
16V, X7R, +/-10%
C382
22nF
50V, X7R, +/-10%
1
*
2
*
Note:
In order to meet to Eaglake DMI signal level,
recommend the VCCDMI power signal must be
tied to 1.1V.
012008
1D1V_ICH
1D1V_MCH
*
R457
0
Dummy
+/-5%
*R461
0
+/-5%
1D1V_DMI
AA23
AA24
AA25
AB24
AB25
AC25
AD25
AD26
AD28
AE28
AE29
AE30
J24
J25
K23
K24
K25
L24
L25
M23
M24
M25
N24
N25
P23
P24
P25
R24
R25
T23
T24
T25
T26
T28
U24
U28
U29
U30
V23
V24
V25
W24
W25
Y23
Y24
Y25
Vcc1_5_B_1
Vcc1_5_B_2
Vcc1_5_B_3
Vcc1_5_B_4
Vcc1_5_B_5
Vcc1_5_B_7
Vcc1_5_B_8
Vcc1_5_B_9
Vcc1_5_B_10
Vcc1_5_B_11
Vcc1_5_B_12
Vcc1_5_B_13
Vcc1_5_B_14
Vcc1_5_B_15
Vcc1_5_B_16
Vcc1_5_B_17
Vcc1_5_B_18
Vcc1_5_B_19
Vcc1_5_B_20
Vcc1_5_B_21
Vcc1_5_B_22
Vcc1_5_B_23
Vcc1_5_B_24
Vcc1_5_B_25
Vcc1_5_B_26
Vcc1_5_B_27
Vcc1_5_B_28
Vcc1_5_B_29
Vcc1_5_B_30
Vcc1_5_B_31
Vcc1_5_B_32
Vcc1_5_B_33
Vcc1_5_B_34
Vcc1_5_B_35
Vcc1_5_B_36
Vcc1_5_B_37
Vcc1_5_B_38
Vcc1_5_B_39
Vcc1_5_B_40
Vcc1_5_B_41
Vcc1_5_B_42
Vcc1_5_B_43
Vcc1_5_B_44
Vcc1_5_B_45
Vcc1_5_B_46
Vcc1_5_B_47
AG29
AG30
VccDMI_1
VccDMI_2
H10
H11
AC11
AB23
AC18
AC20
AC13
AD11
AD12
AD13
AE11
AF11
AH10
AH11
AJ10
AK10
AC17
AD17
AE17
AF17
AH17
AH18
AJ18
AK18
Vcc1_5_A_1
Vcc1_5_A_2
Vcc1_5_A_3
Vcc1_5_A_4
Vcc1_5_A_5
Vcc1_5_A_6
Vcc1_5_A_7
Vcc1_5_A_8
Vcc1_5_A_9
Vcc1_5_A_10
Vcc1_5_A_11
Vcc1_5_A_12
Vcc1_5_A_13
Vcc1_5_A_14
Vcc1_5_A_15
Vcc1_5_A_16
Vcc1_5_A_17
Vcc1_5_A_18
Vcc1_5_A_19
Vcc1_5_A_20
Vcc1_5_A_21
Vcc1_5_A_22
Vcc1_5_A_23
Vcc1_5_A_24
1D5V_ICH
1D5V_ICH
VccDMIPLL LRC Filter
*
C416
10uF
C418
10nF
25V, X7R, +/-10%
*
10V, Y5V, +80%/-20%
10V, Y5V, 10V,
+80%/-20%
Y5V, +80%/-20%
1
*
C462
1uF
2
1uH@10MHz
Rated at least 100mA
C398
1uF
*
VCCDMIPLL
0
1
R445
2
1
1
2
ICH8 Core decoupling caps.
2
L51
B
Place LRC near pin T30
3D3V_SYS
1D5V_ICH
PCI-E (VCC1_5_B) Filter
1D5V_PE_ICH
L52
1D5V_PE_ICH
2
L1206 0.47uH
*
+/-20%
EC59
220uF
6.3V, +/-20%
*
*
C422
C423
22uF
22uF
6.3V, X5R, +/-10% 6.3V, X5R, +/-10%
PCI-E decoupling caps.
5V_SYS
6.3V, Y5V, +80%/-20%
*
C432
2.2uF
1
1
2
1
*
*
10V, Y5V, +80%/-20%
Dummy
2
1
C394
1uF
*
2
1
1
2
16V, Y5V, +80%/-20%
R455
FSB_VTT
*
VccHDA
R454
C584
0.1uF
25V, Y5V, +80%/-20%
D
3D3V_SYS
0
+/-5%
BACK 1D5V_ICH
0
Dummy
+/-5%
BACK
BACK
C
3D3V_SYS
VccGLAN3_3
A27
VccLAN3_3_1
VccLAN3_3_2
A12
B12
3D3V_SYS
3D3V_SYS
3D3V_SYS
Vcc3_3_5
Vcc3_3_4
Vcc3_3_3
Vcc3_3_2
Vcc3_3_1
Vcc3_3_6
Vcc3_3_7
Vcc3_3_8
Vcc3_3_9
Vcc3_3_10
Vcc3_3_11
Vcc3_3_12
Vcc3_3_13
Vcc3_3_14
Vcc3_3_15
Vcc3_3_16
AH24
AF21
AC21
AC19
AD10
AH30
AK4
A2
B1
B9
G11
G3
H7
J2
K8
L8
*
*
C386
0.1uF
16V, X7R, +/-10%
LAN decoupling caps.
Close to Pin A12,12
3D3V_SB
VccSus3_3
VccSus3_3_1
VccSus3_3_2
VccSus3_3_3
VccSus3_3_4
VccSus3_3_5
VccSus3_3_6
VccSus3_3_7
VccSus3_3_8
VccSus3_3_9
VccSus3_3_10
VccSus3_3_11
VccSus3_3_12
VccSus3_3_13
VccSus3_3_14
VccSus3_3_15
VccSus3_3_16
AF2
U1
U2
U3
U5
U6
U7
U8
V8
W7
W8
Y8
A17
B20
C20
E17
H15
VccRTC
A22
VccSus1_05_1
VccSus1_05_2
AC7
H17
VccSus1_5_1
VccSus1_5_2
H18
AD8
*
*
B
VCCRTC
1D05V_ICH_SB
1D5V_ICH_SB
*
Place near ball
H18
5 OF 6
*
C459
0.1uF
BACK
*
C583
0.1uF
25V, Y5V, +80%/-20%
BACK
25V, Y5V, +80%/-20%
A
*R460
100
Unstuff for VccSus3_3 rail is
derived from the 5 VSB
D10
10
DummyD
+/-5%
LS4148-F
A
REF5V_SUS
REF5V_SUS
C443
1uF
10V, Y5V, +80%/-20%
*
place cap. near pin AF1
FOXCONN PCEG
Title
V5REF / 3D3V_SYS Power Sequencing
V5REF_SUS / 3D3V_SB Power Sequencing
ICH10 -3
Size
C
Date:
5
C373
0.1uF
Close to B23,C23
place cap. near pin A15
Placed near AG30
DMI decoupling caps.
*
3D3V_SB
A
REF5V
REF5V
0.1uF C446
16V, Y5V, +80%/-20%
C379
4.7uF
C
C438
22uF
6.3V, X5R, +/-10%
*
10
1
*
* R410
D8
LS4148-F
2
1
2
A
0.1uF C378
16V, Y5V, +80%/-20%
*
AH28
AJ30
*
1D1V_ICH
C363
4.7uF
6.3V, X5R, +/-10%
3D3V_SYS
5V_SB_SYS
1D1V_DMI
C
1
1
C458
0.1uF
16V, Y5V, +80%/-20%
2
*
V_CPU_IO_1
V_CPU_IO_2
*
0.1uF C417
16V, Y5V, +80%/-20%
B10
A10
A24
B24
C24
E24
F24
G24
H23
H24
J23
M12
M13
M15
M17
M18
M19
N12
N19
R12
R19
U12
U19
V12
V19
W12
W13
W15
W17
W18
W19
2
VccGLANPLL
Vcc1_05_1
Vcc1_05_2
Vcc1_05_3
Vcc1_05_4
Vcc1_05_5
Vcc1_05_6
Vcc1_05_7
Vcc1_05_8
Vcc1_05_9
Vcc1_05_10
Vcc1_05_11
Vcc1_05_12
Vcc1_05_13
Vcc1_05_14
Vcc1_05_15
Vcc1_05_16
Vcc1_05_17
Vcc1_05_18
Vcc1_05_19
Vcc1_05_20
Vcc1_05_21
Vcc1_05_22
Vcc1_05_23
Vcc1_05_24
Vcc1_05_25
Vcc1_05_26
Vcc1_05_27
Vcc1_05_28
Vcc1_05_29
0.1uF C380
16V, Y5V, +80%/-20%
VccDMIPLL
A28
1D5V_PE_ICH
1D5V_ICH_SB
0
VccSATAPLL
T30
16V, X7R, +/-10%
1D5V_ICH
R502
AK20
VCCGLANPLL
C385
*
0.1uF
Dummy
OF 6
L53
VccUSBPLL
VCCDMIPLL
1D5V_PE_ICH
*internal pull-up
C
VccHDA
AK5
Dummy
1D5V_ICH
* *
1
*SPI_CS1#
1
0
1
VccCL1_05
C389
0.1uF
16V, Y5V, +80%/-20%
VccSusHDA
*
AA7
AA8
AB7
AB8
T1
AC14
AC15
AC16
1
PIRQAB
PIRQBB
PIRQCB
PIRQDB
GP2_PIRQEB
GP3_PIRQFB
GP4_PIRQGB
GP5_PIRQHB
C381
0.1uF
16V, X7R, +/-10%
*
AC10
1D5V_ICH
VCCSATAPLL
Vcc1_5_A_25
Vcc1_5_A_26
Vcc1_5_A_27
Vcc1_5_A_28
Vcc1_5_A_29
Vcc1_5_A_30
Vcc1_5_A_31
Vcc1_5_A_32
VccCL1_05
2
J5
E1
F1
A3
K6
L7
F2
G2
VccHDA
*
VccCL1_5
0.1uF C445
16V, Y5V, +80%/-20%
INTAJ
INTBJ
INTCJ
INTDJ
INTEJ
INTFJ
INTGJ
INTHJ
BACK
VccCL1_5
V5REF_Sus
A26
1
31
31
31
31
31
31
31
31
VccCL1_5
VccCL1_05 A23
+/-5%
BACK
VccSusHDA
AC9
2
REQB_0
REQB1_GP50
REQB2_GP52
REQB3_GP54
+/-1%
*R500
0
#REFDE7
COPPER
0.1uF C388
16V, Y5V, +80%/-20%
K7
G13
F13
G8
C471
0.1uF
16V, Y5V, +80%/-20%
1
PREQ0J
PREQ1J
PREQ2J
PREQ3J
*GNT0
0
1
1
CBEJ0
CBEJ1
CBEJ2
CBEJ3
GNTB0
GNTB1_GP51
GNTB2_GP53
GNTB3_GP55
31
31
31
31
Boot Device
SPI
PCI
LPC
CXBEB_0
CXBEB_1
CXBEB_2
CXBEB_3
F11
G9
C4
E8
PCI
VccSusHDA
*R485*
1K
Dummy
2
R429
1K
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
0.1uF C395
16V, Y5V, +80%/-20%
GNT0J
H5
A7
C7
F7
GNT0J
GNT1J
C10
C8
E9
C9
A5
E12
E10
B7
B6
B4
E7
A4
H12
F8
C5
D2
E5
G7
E11
G10
G6
D3
H6
G5
C1
C2
C3
D1
J7
F3
G1
H3
3D3V_CL
Stuff for non-Intel LAN
or M0 only
C370
0.1uF
16V, Y5V, +80%/-20%
1
PCI Slot
31
31
AD_0
AD_1
AD_2
AD_3
AD_4
AD_5
AD_6
AD_7
AD_8
AD_9
AD_10
AD_11
AD_12
AD_13
AD_14
AD_15
AD_16
AD_17
AD_18
AD_19
AD_20
AD_21
AD_22
AD_23
AD_24
AD_25
AD_26
AD_27
AD_28
AD_29
AD_30
AD_31
PAR
DEVSELB
PCICLK
PCIRSTB
IRDYB
PMEB
SERRB
STOPB
PLOCKB
TRDYB
PERRB
FRAMEB
AF1
3D3V_SYS
VccCL3_3_2
VccCL3_3_1
V5REF
2
PCI Slot
E3
C6
B3
R2
J8
R3
K5
F10
H8
E6
F5
G12
0
31
GND
D
PAR
DEVSELJ
CK_33M_ICH
R441
IRDYJ
PMEJ
SERRJ
STOPJ
LOCKJ
TRDYJ
PERRJ
FRAMEJ
PAR
DEVSELJ
CK_33M_ICH
PCIRSTJ
IRDYJ
PMEJ
SERRJ
STOPJ
LOCKJ
TRDYJ
PERRJ
FRAMEJ
AD[31..0]
3D3V_SB
1
31
31
7
31
31
31
31
31
31
31
31
31
A6
AD[31..0]
B23
C23
0.1uF C421
16V, Y5V, +80%/-20%
2
1
ICH10
ICH10
2
REF5V
4
3
2
Document Number
Rev
A
G43M01S1
Sheet
Monday, August 11, 2008
1
25
of
41
5
4
3
2
1
ICH10
B
3D3V_SB
3D3V_SYS
FSB_VTT
FSB_VTT
1D5V_ICH
C454
4.7uF
*
1
C410
0.1uF
16V, X7R, +/-10%
2
*
C460
0.1uF
16V, X7R, +/-10%
2
*
1
2
D
3D3V_SB
CPU decoupling caps.
C374
C420
0.1uF
0.47uF
16V, X7R, +/-10%10V, X5R, +/-10%
*
2
1
*
2
Audio decoupling caps.
1
C396
0.1uF
16V, X7R, +/-10%
C463
0.1uF
16V, X7R, +/-10%
Placed near AH28 and AJ30
3D3V_SYS
*
*
6.3V, X5R, +/-10%
*
1
C447
0.1uF
16V, X7R, +/-10%
2
*
1
C387
0.1uF
16V, X7R, +/-10%
0.1uF
16V, Y5V, +80%/-20%
*
C450
C400
1uF
10V, Y5V, +80%/-20%
1
*
2
C399
1uF
10V, Y5V, +80%/-20%
2
*
1D5V_ICH
1D5V_ICH
1
1D5V_ICH
1
SATA decoupling caps.
VCCRTC
VCCRTC
C376
C375
0.1uF
0.1uF
16V, X7R, +/-10%
16V, X7R, +/-10%
1
*
*
C365
1uF
10V, X5R, +/-10%
USB decoupling caps.
2
1
*
2
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
H13
H19
H2
H22
H25
H26
H28
H9
J29
J30
J6
K26
K28
L2
L23
L29
L30
M14
M16
M26
M28
M6
M8
N13
N14
N15
N16
N17
N18
N23
N29
N30
P12
P13
P14
P15
P16
P17
P18
P19
P2
P26
P28
P6
R13
R14
R15
R16
R17
R18
R23
R29
R30
R8
T12
T13
T14
T15
T16
T17
T18
T19
T2
T29
T5
U13
U14
U15
U16
U17
U18
U23
V13
V14
V15
V16
V17
V18
V26
V28
V3
V7
W1
W14
W16
W23
W29
W30
W5
W6
Y26
Y28
Y3
Y7
AA30
AA29
AA1
A30
A1
2
AK27
AH29
AJ4
AF3
B27
VSS_099
VSS_098
VSS_097
VSS_096
VSS_095
VSS_094
VSS_093
VSS_092
VSS_091
VSS_090
VSS_089
VSS_088
VSS_087
VSS_086
VSS_085
VSS_084
VSS_083
VSS_082
VSS_081
VSS_080
VSS_079
VSS_078
VSS_077
VSS_076
VSS_075
VSS_074
VSS_073
VSS_072
VSS_071
VSS_070
VSS_069
VSS_068
VSS_067
VSS_066
VSS_065
VSS_064
VSS_063
VSS_062
VSS_061
VSS_060
VSS_059
VSS_058
VSS_057
VSS_056
VSS_055
VSS_054
VSS_053
VSS_052
VSS_051
VSS_050
VSS_049
VSS_048
VSS_047
VSS_046
VSS_045
VSS_044
VSS_043
VSS_042
VSS_041
VSS_040
VSS_039
VSS_038
VSS_037
VSS_036
VSS_035
VSS_034
VSS_033
VSS_032
VSS_031
VSS_030
VSS_029
VSS_028
VSS_027
VSS_026
VSS_025
VSS_024
VSS_023
VSS_022
VSS_021
VSS_020
VSS_019
VSS_018
VSS_017
VSS_016
VSS_015
VSS_014
VSS_013
VSS_012
VSS_011
VSS_010
VSS_009
VSS_008
VSS_007
VSS_006
VSS_005
VSS_004
VSS_003
VSS_002
VSS_001
3D3V_SYS
C
Placed near A22
*
1
C
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
C384
0.1uF
16V, X7R, +/-10%
RTC decoupling caps.
2
D
G30
G29
G25
G16
F9
F6
F28
F26
F21
F12
E30
E29
E22
E2
E18
E15
D28
B8
B5
B28
B25
B22
B2
B19
B17
B14
B11
AK8
AK30
AK29
AK2
AK16
AK14
AK12
AJ8
AJ5
AJ26
AJ23
AJ20
AJ16
AJ14
AJ12
AH8
AH6
AH20
AH2
AH19
AH15
AH13
AG28
AF9
AF7
AF29
AF25
AF23
AF20
AF15
AF13
AE9
AE8
AE6
AE5
AE25
AE19
AE18
AE16
AE15
AE14
AE13
AE12
AE10
AE1
AD9
AD7
AD3
AD22
AD19
AD18
AD16
AD15
AD14
AC8
AC6
AC5
AC30
AC29
AC24
AC12
AC1
AB3
AB28
AB26
AA6
AA5
PCI decoupling caps.
B
Del PLTRST# and PCIRST# buffer
Use SIO PCIRST# buffer
6 OF 6
A
A
FOXCONN PCEG
Title
ICH10 -4
Size
C
Date:
5
4
3
2
Document Number
Rev
A
G43M01S1
Sheet
Monday, August 11, 2008
1
26
of
41
5
4
3
2
1
VDD33
E
3D3V_SB
1
C65
0.1uF
2
1
1
1
2
75
RT9166A-12PXL
TX-
AVDDL
RX
RX+
1
75
RX-
2
10uF
10V, Y5V, +80%/-20%
0.1 uF
Dummy
1000pF
1
3D3V_SB
3
7
8
6
2KV
1
D3
C
A LS4148-F
1
2
16V, Y5V, +80%/-20%
*
16V, Y5V, +80%/-20%
0 +/-5%
*
1
20
19
16V, Y5V, +80%/-20%
LANUSBPWR
27
28
29
30
*
3D3V_SB
USBP0N_L
USBP1N_L
L6
1 Dummy
5
3
7
USBP0P_L
USBP1P_L
2
6
3
7
4
8
4
23
24
25
26
EC25
470uF
16V, +/-20%
16V, Y5V, +80%/-20%
*
C114
0.1uF
*
8
Filter 100MHz
RN9
1
3
5
7
Left Side
1
C118
0.1uF
2
LED0
16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20%
C586
0.1uF
Green Active Left side
Yellow Link Right side
*
USBP1N_L
USBP1P_L
USBP0N_L
USBP0P_L
USBP1N
USBP1P
USBP0N
USBP0P
23
23
23
23
A
5V_DUAL_USB
1
6
2
5
3
4
USBP1P
FOXCONN PCEG
Title
For EMI.
IP4220CZ6
USBP0P
RTL8101E/8111B
Size
C
Date:
4
USBP1N
USBP1P
USBP0N
USBP0P
2
4
6
8
0
+/-5%
U5
USBP1N
2
1
*
USBP0N
5
23
C153
0.1uF
16V, Y5V, +80%/-20%
LED caps. should be placed
next to connector
+/-5%
*
*
2
6
CONN-USBX2_RJ45
*R66
330
USB_OCJ_BACK_LAN
R103
15K
2
A
10K
R104
1
R62
0
+/-5%
C105
0.1uF
F3
Fuse 1.5A
1
5
GRN_LED
dummy
Right Side
9
10
11
12
13
14
15
16
17
18
2
*
22
21
C117
0.1uF
RJ45-MJ2
AVDDL
2
@8101E
MDI0+
MDI0MDI1+
MDI1MDI2+
MDI2MDI3+
MDI3R61
*
1
*
C587
0.1uF
#VNIC_USB1#VNIC_USB2
USB-1
LED2
NIC_USB
LAN_PLTRSTJ
C607
0.1uF
Dummy
16V, Y5V, +80%/-20%
2
+/-5%
USB-2
C
A LS4148-F
5V_DUAL_USB
0.1uF 16V, Y5V, +80%/-20%
YLW_LED
D4
*R64
330
GRN_LED
LED1
1
C120
*
*
@8111C/8111B
Near 8111C
USB-1
B
3D3V_SB
R65
330
+/-5%
@8111C/8111B
0 +/-5%
CONN-USBx2_RJ45
USE CONNECTOR (Foxconn P/N:
JFM24U13-21U5W) WITH 10/100 DESIGN
*
R63
CONN-USBx2_RJ45
16V, Y5V, +80%/-20%
@8101E/8111B
LED3
C121
1nF
50V, X7R, +/-10%
@8101E
*
C122
0.1uF
2
C72
0.1uF
16V, X7R, +/-10%
@8101E
*
FB 120 Ohm
@8101E
2
1
*
5
2
Link Led
YELLOW
250
L27
*
Link
右灯
灭
灭
綠色灯亮
橙色灯亮
@8111C/8111B
GRN_LED
75
1
4
GRN_LED
TX+
75
AVDDL
*
C85
0.1uF
16V, X7R, +/-10%
@8101E
2
2
TX
YLW_LED
OUT
VNIC_USB2
@8101E
Q20
Link Led
Green
250
Active
左灯
模式
无网线连接 灭
綠色灯閃爍
10M
綠色灯閃爍
100M
綠色灯閃爍
1000M
16V, Y5V, 16V,
+80%/-20%
Y5V, +80%/-20%
FB 100 Ohm
+/-25%
@8111C
For 8111C Cost down only, if stuff this circuit,
unstaff L26(4.7uH)
*
*
C119
0.1uF
RJ45-MJ2
3D3V_SB
+/-5%
R35
49.9
+/-1%
@8101E
*
0 +/-5%
@8101E/8111B
C63
0.1uF
MDI0-
*
R25
49.9
+/-1%
@8101E
2
1
*
2
B
MDI0+
MDI1-
MDI1+
*
R41
49.9
+/-1%
@8101E
EVDD18
C116
0.1uF
C
0
*
0 +/-5%
#VR414#VFB16
16V, Y5V, +80%/-20%
10uF
10uF
@8111C
10V, Y5V, +80%/-20% 10V, Y5V, +80%/-20%
@8111C
@8111C
XTAL2
*
R40
49.9
+/-1%
@8101E
R70
1
2
2
2
2
1
2
*
*C46
C136
R68
AVDDL
2
*
CTRL15
*C55
Dummy
EGND
1
2
C87
0.1uF
1
*
1
*
1
1
1
*
C67
0.1uF
2
1
*
+/-5%
@8111C
0
VIN
7
7
2
2
2
E
C
4
*
C82
0.1uF
1:1
CK_PE_100M_P_LAN
VDD33
0
16V, Y5V, +80%/-20%
C76
0.1uF
VNIC_USB1
CK_PE_100M_N_LAN
+/-5%
C68
0.1uF
DVDD
1
R2
3D3V_SB
3
23
D
XTAL1
X1
XTAL-25MHz
+/-30PPM
GND
23
C104
0.1uF
VFB16
2
HSI_N2
HSI_P2
*
R47
*
VR414
1
HSO_N2_LAN
AVDDH
AVDDH
*C74
10uF
10V, Y5V, +80%/-20%
@8101E
1
1
2
2
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
C115
0.1uF
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
10uF
16V, Y5V, +80%/-20%
AVDDL
10V, Y5V, +80%/-20%
@8101E/8111B
*C40
33pF
+/-5%
2 0.1uF
16V, X7R, +/-10%
2 0.1uF
16V, X7R, +/-10%
+/-5%
@8101E
C112
10uF 10uF 16V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10uF
10uF
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
0
16V, Y5V, +80%/-20%
C125
* *
C78
0.1uF
2
1
1
1
*
Q16
BCP69T1G
@8111B
1
1
*
R43
C66
0.1uF
VDD33
2
*
C
4
1
*
C92
0.1uF
C54
DVDD
C53
C123 1
EGND
*
C107
*
VDD33
2
0
+/-5%
@8101E/8111B
**
LAN_PLTRSTJ
C48
0
+/-5%
@8111C
R52
2
*
8
7
6
5
VCC
NC
ORG
GND
AT93C46DN-SH-T
R54
1K
+/-1%
R49
1
2
15K
+/-1%
DVDD
VDD33
CS
SK
DI
DO
2
*
3D3V_SYS
DVDD
R50
CTRL15
U1
+/-5% EECS
1
EESK
R18 Dummy
0
2
EEDI/AUX 3
R19
EEDO 4
3.6K
+/-5%
33pF
+/-5%
C124 1
LAN_PMEJ
23 HSO_P2_LAN
23
EESK
EEDI/AUX
VDD33
EEDO
EECS
DVDD
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
*
EVDD18
In order to disable wake up funciton
respectivlely, it should be not shared with
other PME singal of the PCI-E devices .
29 LAN_PLTRSTJ
AVDDL
VDD33
*
NC7
NC8
LANWAKEB
PERSTB
VDD15B
EVDD18A
HSIP
HSIN
EGNDA
REFCLK_P
REFCLK_N
EVDD18B
HSOP
HSON
EGNDB
NC9
DVDD
EVDD18
#VU21#VU22#VU33
EESK
EEDI/AUX
VDD33C
EEDO
EECS
VDD15C
NC17
NC16
NC15
NC14
NC13
VDD33B
ISOLATEB
NC12
NC11
NC10
RTL8101E-GR
VCTRL18
AVDD33
MDIP0
MDIN0
AVDD18A
MDIP1
MDIN1
AVDD18B
NC1
NC2
NC3
NC4
NC5
NC6
VDD15A
VDD33A
+/-5%
0
AVDDL
+/-5%
@8101E
B
3D3V_SB VDD33
*
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
R14
0
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CTRL18
AVDDH
MDI0+
MDI0AVDDL
MDI1+
MDI1AVDDL
MDI2+
MDI2AVDDL
MDI3+
MDI3AVDDL
DVDD
VDD33
RTL8111C-VB-GR
AVDDL
EGND
DVDD
65
65
U3
R53
3D3V_SB
4.7uH
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
#VR401#VR402
23
RTL8101E-GR
DVDD
XTAL2
XTAL1
AVDDH
DVDD
LED0
LED1
LED2
LED3
VDD33
DVDD
RSET
CTRL15
R15
+/-1%
L8
@8111C
RSET
VCTRL15
NC22
CKTAL2
CKTAL1
NC21
VDD15E
LED0
LED1
LED2
LED3
VDD33D
NC20
NC19
NC18
VDD15D
*
D
C
CTRL18
C64
0.1uF
@8111B
RTL8111B-VC-GR
2KOhm
@8111C
1
*
VU33
2
*
Dummy
2KOhm
@8101E +/-1%
VU22 @8101E
2
VR402
C52
1uF
1
* *
@8111C/8111B
VR401
2.49K+/-1%
Q5
BCP69T1G
@8111B
B
VU21 @8111B
USB-2
*
R13
0
+/-5%
@8111C
3
2
Document Number
Rev
A
G43M01S1
Sheet
Monday, August 11, 2008
1
27
of
41
5
4
3
2
1
5V_SB_SYS
A
5V_AUDIO
GND
D5
C
LS4148-F
1 Dummy
2
3
*
C102
10uF
16V, Y5V,+80%~-20%
EC13
100uF
*
R57
A Reserved
R67
39.2K +/-1%
@6JACK
SURR_JD
37
F_JD
37
L1_JD
37
MIC1_JD
37
D
5.1KOhm +/-1%
FB 300 Ohm
R59
2
R58
10
+/-5%
R69
10K +/-1% r0402h4
20K +/-1% r0402h4
Filtering Power Noise(Improve
background noise caused by MIC-boost)
GND_AUDIO
GND_AUDIO
Jack Detect
SENSE_B
1D5V_ICH
R73
0
3D3V_SYS
R74
0.1uF
R30
0
*
R20
Dummy
C131
Dummy
5V_AUDIO
R28
1
*
C129
0.1uF
*
*
C79
0.1uF
*
C71
0.1uF
R29
5.1KOhm +/-1%
@6JACK
SURRBACK_JD 37
10K
+/-1%
@6JACK
CEN_JD
37
MIC2_JD
37
LINE2_JD
37
20K
+/-1% r0402h4
39.2K
+/-1%
C
2
C
C135
4.7uF
Dummy
* * *
*
2
1
C57
4.7uF
IN
SENSE_A
L26
L78L05N
OUT
* *
U11
1
D
*
Jack Detect
12V_SYS
C
D2
SD103AW
R81
R75
1K+/-1%
*
C134
100pF
Dummy
GND_AUDIO
+/-5%
C132
r0402h4
1uF 10V, X5R, +/-10%
Dummy
SENSE_A
AUX_L
AUX_L
AUX_R
AUX_R
MIC2_L_16
MIC2_L
MIC2_R_17
MIC2_R
CD_L
CD_GND
CD_R
MIC1_L
MIC1_R
LINE1_L
LINE1_R
37
37
37
37
37
37
37
37
37
37
37
37
SPDIF_OUT
11
6
10
8
5
RESET#
BCLK
SYNC
SDATA-IN
SDATA_OUT
12
13
14
15
16
17
18
19
20
21
22
23
24
47
48
PCBEEP
Sense A
LINE2-L (Port-E-L)
LINE2-R (Port-E-R)
MIC2-L (Port-F-L)
MIC2-R (Port-F-R)
CD-L
CD-GND
CD-R
MIC1-L (Port-B-L)
MIC1-R (Port-B-R)
LINE1-L (Port-C-L)
LINE1-R (Port-C-R)
SPDIFI/EAPD
SPDIFO
ALC888-GR
FRONT-L (Port-D)
FRONT-R (Port-D)
PIN37-VREFO
NC
Sense B
SURR-L (Port-A-L)
JDREF
SURR-R (Port-A-R)
CENTER (Port-G-L)
LFE (Port-G-R)
SIDE-L (Port-H-L)
SIDE-R (port-H-R)
MIC1-VREFO-L
VREF
LINE1-VREFO
MIC2-VREFO
LINE2-VREFO
MIC1-VREFO-R
Add CD-IN Eric
35
36
37
33
34
39
40
41
43
44
45
46
LINE_OUT_L
LINE_OUT_R
R31
10K +/-1% r0402h4 @883
SENSE_B
5V_AUDIO
SURRBACK_L
SURRBACK_R
MIC1_VREFO
28
2 10uF
27 C69 1
29
30
31
32
37
37
MIC1_VREFO
SURR_L
37
SURR_R
CEN
LFE
SURRBACK_L
SURRBACK_R
37
37
37
37
37
R38
*
*
10K +/-5% r0402h4 Dummy
Dummy
B
22
GPIO1/DMIC-DATA
GPIO0/DMIC-CLK
20K +/-1% r0402h4
Near to Codec
GND_AUDIO
37
GND_AUDIO
B
MIC2_VREFO 37
LINE2_VREFO 37
MIC1_VREFO_R 37
ALC888-GR
4
7
26
42
BEEP_PC
R72
*
32
ICH_AUD_RSTJ
ICH_AUD_BCLK
ICH_AUD_SYNC
ICH_AUD_SDIN2
ICH_AUD_SDOUT
*
23
23
23
23
23
All of JD resistors should be placed as
close as possible to Codec.
*
3
2
37 FIO_PRESENCEJ
GND_AUDIO
DVDD
DVDD-IO
AVDD1
AVDD2
U4
*
C130
3.3pF
50V, NPO, +/-0.25pF
DVSS
DVSS
AVSS1
AVSS2
*
1
9
25
38
ICH_AUD_BCLK
#REFDE5
* *
C41
Dummy
R585
R586
A
X_COPPER
GND_AUDIO
0
+/-5%
0.1uF
16V, Y5V, +80%/-20%
**
C51
Dummy
0.1uF
16V, Y5V, +80%/-20%
#REFDE4
For EMI
X_COPPER
0
A
*
+/-5%
C133
0.1uF
Dummy
16V, Y5V, +80%/-20%
FOXCONN PCEG
GND_AUDIO
Title
GND_AUDIO
HDA Codec ALC888S
Size
Document Number
Custom
Date:
5
4
3
2
Rev
A
G43M01S1
Monday, August 11, 2008
Sheet
1
28
of
41
1
For the temperature sensor circuits,
1)Please don't remove the 1uF capacitor(C4)
between Vref and AGND.
2)Place the thermal diode close to IT8720F.
3)Keep the trace away from +12V, fast data bus,
nd CRTs.
4)Recommended trace widths and spacings are 12 mils.
5)Isolate AGND and DGND.
3D3V_SYS
Close to pin
D
R543
1K
*
1
R549
R557
Dummy
Dummy
680
680
System temperature sensing
5V_SYS
A20GATE
KBRSTJ
L_DRQ0J
16V, Y5V, +80%/-20%
2
1
*
C489
0.1uF
*
1
C488
0.1uF
*
16V, Y5V, +80%/-20%
2
1
EMI Cap.
2
R544
1K
10K
C542
0.1uF
16V, Y5V, +80%/-20%
2
*
R525
Dummy
C487
0.1uF
Del Vref circuit
16V, Y5V, +80%/-20%
placed near pin4,35,99
*
C563
TMPIN1
2
*
*
*
39
39
39
39
DCD2J
RI2J
CTS2J
DSR2J
SOUT2
SIN2
RTS2J
DTR2J
DCD2J
RI2J
CTS2J
DSR2J
23
Note:
Recommend Vin4,Vin5,Vin6 monitor the
voltage signals of less than 4.096V.
Gary 011108
48
25
24
ICH_THRM
32
32
SIO_BEEP
PWR_LED
5V_SYS
R520
4.7K
R519
4.7K
23
3D3V_SYS
PECI_RQT
R522
0
*R528
10K
5V_SYS
*Dummy
1
2
3
4
5
6
8
150 7
+/-5%
R566Dummy
150
+/-5%
L_AD3
L_AD2
L_AD1
L_AD0
1
X
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
Dummy
JP3
Pin 124
JP4
A
Pin 126
JP3 &
JP5
Pin 124
& 46
JP5
Pin46
JP6
Pin29
Disabled.
0
Flash I/F Address Segment 1 is enabled
1
Disable VID output pins
0
Enable VID output pins
Use for chip 1 when two IT8718F exit in the
same system. Chip is selected in conjunction
with "Global Configuration Register - Index 22, bit 7
CHIP_SEL
K8PWR_EN
FAN_CTL_SEL
WDT_EN
SVID_EN
0
51
63
52
55
54
53
57
58
56
60
62
64
61
59
65
INDEXJ
MOAJ
10,24
DSAJ
PECI
R560
0
DIRJ
STEPJ
WDJ
WEJ
TRAK0J
WPJ
RDATAJ
HEADJ
DSKCHGJ
DENSEL#
INDEX#
MTRA#
PECI/AMDSI_C/DRVB#
DRVA#
SST/PECI_AVA/AMDSI_D/MTRB#
DIR#
STEP#
WDATA#
WGATE#
TRK0#
WPT#
RDATA#
HDSEL#
DSKCHG#
12,23,34 PLTRSTJ
23
L_DRQ0J
24,34
SERIRQ
23,34 L_FRAMEJ
7
7
23
CK_33M_SIO
CK_48M_SIO
L_PMEJ
24
24
34
34
34
34
KBRSTJ
A20GATE
KBDATA
KBCLK
MSDATA
MSCLK
L_DRQ0J
L_AD0
L_AD1
L_AD2
L_AD3
KBRSTJ
A20GATE
KBDATA
KBCLK
MSDATA
MSCLK
37
38
39
40
41
42
43
44
47
49
73
LRESET#
LDRQ#/JP1
SERIRQ
LFRAME#
LAD0
LAD1
LAD2
LAD3
PCICLK
CLKIN
PME#/GP54
45
46
80
81
82
83
KRST#/GP62
GA20/JP5
KDAT/GP61
KCLK/GP60
MDAT/GP57
MCLK/GP56
10
1
#REFDE9
2Dummy
X_COPPER
THERMDC
10
CPU temperature sensing
67
VCCH
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
PD[7..0]
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
3D3V_SYS
R569
R571
78
77
76
75
72
71
R523
1
#REFDE10
30
85
66
70
68
79
84
34
33
32
39
C
STBJ
AFDJ
ERRJ
INIT
SLINJ
ACKJ
BUSY
PE
SLCT
39
39
39
39
39
39
39
39
39
10K
10K
ICH_G_PLTRSTJ R158
LAN_PLTRSTJ
R60
R567
4.7K
5V_SB_SYS
10K
2Dummy
X_COPPER
PS_ONJ
19,32
PWRBTNJ
23
CIRTX
5V_SYS
SIO_RSMRSTJ
IRTX
IRRX
32
*
19,23
32
32
R578
33
C555
1uF
10V, Y5V, +80%/-20%
SLP_S3J
23
3D3V_SYS
R597
VIN0
VIN1
VIN2
VIN3/ATXPG
VIN4/VLDT_12
VIN5/VDDA_25
VIN6/VDIMM_STR
VREF
TMPIN1
TMPIN2
TMPIN3
TS_D-
98
97
96
95
94
93
92
91
90
89
88
87
FAN_CTL3/GP36
FAN_TAC3/GP37
FAN_CTL2/GP51
FAN_TAC2/GP52
FAN_CTL1
FAN_TAC1
VID0/GP30
VID1/GP31
VID2/GP32
VID3/GP33
VID4/GP34
VID5/GP35
12
11
10
9
8
7
19
18
17
16
14
13
VBAT
VIDVCC
69
36
VIN0
VIN1
VIN2
VIN4
K8 power sequence function is disabled
K8 power sequence function is enabled
11
The default value of EC Index 15h/16h/17h is 40h(Fan half speed)
10
The default value of EC Index 15h/16h/17h is 7Fh(Fan off )
01
The default value of EC Index 15h/16h/17h is 00h(Fan full speed )
00
The default value of EC Index 15h/16h/17h is 20h
1
Disable WDT to rest PWROK
2 Dummy
1
0
Enable WDT to rest PWROK
COPPER
1
Disable SVID Function
0
Enable SVID Function
0
Dummy
+/-5%
B
PWRGD_3V
12,19,22,23,24
VCCRTC
ATXPWRGD
19,32
*R588
10M
SIOVREF
TMPIN1
TMPIN2
+/-5%
*
TS_D-
C556
1uF
10V, Y5V, +80%/-20%
COPENJ
COPENJ
32
closed to pin 91
For BIOS request
FANOUT2_SYS1 33
FANIN2_SYS1 33
FANOUT1_CPU 33
FANIN1_CPU 33
3D3V_SYS
0
VCCRTC_SIO
C554
1uF
*
1.Closed to pin 69, Vbat should be routed
with a minimum trace width of 12 mils.
2.Isolate the pin69/Vbat of IT8720F and
pin VCCRTC of ICH.
A
10V, Y5V, +80%/-20%
IT8720F/CX-L
#REFDE11
FOXCONN PCEG
Title
Super I/O IT8720H
GND_IO
Size
C
3
32
R521
1K
1
4
PBTNJ_SIO
power button input
Note:
COPEN# should be connected to GND
when the function is not be used.
Date:
5
1K
1K
5V_SB_SYS
COPENJ
TP69
CIRRX
32
LAN_PLTRSTJ 27
ICH_G_PLTRSTJ 22,30
GNDA
Pin 122
VIDO_EN
Description
1
R558
86
JP2
Flashseg1_EN
PM_SLP
GNDD
GNDD
GNDD
GNDD
Pin 38
10,12
15
50
74
117
JP1
value
DENSELJ
Header_2X17_K3
IT8720 Power On Strapping Options
Symbol
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
PWROK2/GP41
SUSC#/GP53
PSON#/GP42
PANSWH#/GP43
PWRON#GP44
SUSB#
RESETCON#/CIRTX1/CE_N
RSMRST#/CIRRX1/GP55
IRTX/GP47
IRRX/GP46
COPEN#
3VSBSW#/GP40
PCIRST4#/GP10/VDIMM_STR_EN
PCIRST2#/GP11
PCIRST1#/GP12
PWROK1/GP13
Hardware Monitoring
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
RN51
L_AD[3..0]
99
FLOPPY
1
B
RDATAJ
FAN_CTL4/VID_TURBO
PSI_L/FAN_CTL5/CIRRX2/GP16
PCIRSTIN#/CIRTX2/SVD
PECI_RQT/SVC/GP14
VCORE_GOOD/VID6/GP63
VCORE_EN/VID7/GP64
VDDA_EN/GP65
VLDT_EN/GP66
CPU_PG/GP67
MISC.
121
2
3
31
6
5
120
119
118
BOARD0
BOARD1
BOARD2
SERIRQ
DSKCHGJ
WPJ
INDEXJ
TRAK0J
GP50/SO
GP22/SCK
GP23/SI
5V_SYS
Del VIN5, VIN6 monitor circuit only
for Clone MB request.
012008
23,34 L_AD[3..0]
THERMDA
*
16V, Y5V, +80%/-20%
2Dummy
X_COPPER
*
C561
0.1uF
GND_IO
1
#REFDE8
U25
PD7/GP77/BUSSO2
PD6/GP76/BUSSO1
PD5/GP75/BUSSO0
PD4/GP74/BUSSI2
PD3/GP73/BUSSI1
PD2/GP72/BUSSI0
PD1/GP71
PD0/GP70
STB#/GP87/SMBC_M
AFD#/GP86/SMBC_R
ERR#/GP83
INIT#/GP85/SMBD_M
SLIN#/GP84/SMBD_R
ACK#/GP82
BUSY/GP81
PE/GP80
SLCT
Power-on
Control
GND_IO
C552
EC72
0.1uF
16V, Y5V, +80%/-20% 100uF
**
VIN2
* *
R575
10K
+/-1%
SOUT2
SIN2
RTS2J
DTR2J
DCD1#
RI1#
CTS1#
DTR1#/JP4
RTS1#/JP2
DSR1#
SOUT1/JP3
SIN1
VIDO1/GP21/DCD2#
VIDO6/GP17/RI2#
VIDO0/GP20/CTS2#
VDIO7/DTR2#/JP6
VIDO2/FAN_TAC5/GP24/RTS2#
VIDO3/FAN_TAC4/GP25/DSR2#
VIDO4/GP26/SOUT2
VIDO5/GP27/SIN2
Floppy I/F
30K
+/-1%
2
R574
1
*
GND_IO
12V_SYS
39
39
39
39
127
128
1
126
122
123
124
125
26
28
27
29
23
22
21
20
LPC I/F
2
16V, Y5V, +80%/-20%
DCD1J
RI1J
CTS1J
DTR1J
RTS1J
DSR1J
SOUT1
SIN1
DCD2J
RI2J
CTS2J
DTR2J
RTS2J
DSR2J
SOUT2
SIN2
DCD1J
RI1J
CTS1J
DTR1J
RTS1J
DSR1J
SOUT1
SIN1
KB/MS
1
C560
0.1uF
Dummy
39
39
39
39
39
39
39
39
Parallel Port
*
TS_D-
Close to pin
*
*
*
The strap's resistor can be deleted since VIDO
and COM2 need to be pulled high.
AVCC
VCC
1
2
16V, Y5V, +80%/-20%
Serial Port 1/2
10K
35
10K
4
10K
VIN4
10K
+/-5%
C546
1uF
C557
3.3nF
+/-10%
R591Dummy
R592Dummy
R593
Dummy
VIN1
GND_IO
R573
*
C553
10uF
Note:
Place C441,C442 close
to Pin99
* 0.1uF
Dummy
C
3D3V_SYS
*
VCC
C562
10K
*
FB 80Ohm
*
GND_IO
10K
+/-5%
10K
L56
BOARD0
BOARD1
BOARD2
16V, Y5V, +80%/-20%
R576
*
SPI
1
10K
0.1uF
Dummy
1D8V_STR
*
R587Dummy
R589Dummy
R590
Dummy
VIN0
*
placed near SIO
GND_IO
SOUT1
5V_SB_SYS
10K
+/-5%
*
+/-1%
5V_SYS
5V_SYS
R577
SIOVREF
10K
R568
C558
10K
0.1uF
+/-1%
16V, Y5V, +80%/-20%
RTS1J
5V_SYS
VCCP
R570
1
If without use these pins, Please pull-up to VCC.
Don't let it floating
1.Pin 30:RESETCON#
2.Pin 95:VIN3/ATXPG
3.Pin 71:SUSB#
4..Power On Strapping Options pin
5.Please don't remove the pull-up resistor (R108)
of pin38/LDRQ#.
6.Please don't remove any components in the
VINx circuits and the FANx control circuits.
7.Please don't change the sequence of
VIN0~VIN6.
8.If without use these pins,please pull-up to VCC,
Don't let it floating ,pin 3,pin 30,pin 38,pin 46,
pin 95,pin 122,pin 124,pin 126.
TMPIN2
*
2
2
3
*
D
4
T
5
2
Document Number
Rev
A
G43M01S1
Sheet
Monday, August 11, 2008
1
29
of
41
5
4
3
2
1
D
D
3D3V_SB
3D3V_SYS
12V_SYS
12V_SYS
3D3V_SYS
12V_SYS
Near connector
PCI-E1_1X
19,22,23,31,33
19,22,23,31,33
SMB_CLK_RESUME
SMB_DATA_RESUME
22,23
WAKEJ
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
12V
12V
RSVD_1
GND
SMCLK
SMDAT
GND
3.3V
JTAG1
3.3VAUX
WAKE#
PRSNT1#
12V
12V
GND
JTAG2
JTAG3
JTAG4
JTAG5
3.3V
3.3V
PWRGD
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
GND
REFCLK+
REFCLKGND
HSIP0
HSIN0
GND
A12
A13
A14
A15
A16
A17
A18
C
*
C188
0.1uF
16V, Y5V, +80%/-20%
3D3V_SB
*
C194
0.1uF
16V, Y5V, +80%/-20%
*
C606
0.1uF
Dummy
16V, Y5V, +80%/-20%
ICH_G_PLTRSTJ
ICH_G_PLTRSTJ
22,29
1
12V_SYS
CK_PE_100M_P_1PORT_1 7
CK_PE_100M_N_1PORT_1 7
EC27
470uF
16V, +/-20%
3D3V_SYS
*
EC38
1000uF
+/-20%
2
23 HSO_P3_SLOT
23 HSO_N3_SLOT
RSVD_2
GND
HSOP0
HSON0
GND
PRSNT2#
GND
3D3V_SYS
ICH_G_PLTRSTJ
KEY
B12
B13
B14
B15
B16
B17
B18
*
C170
0.1uF
16V, Y5V, +80%/-20%
HSI_P3
HSI_N3
23
23
C
Slot-PCIE-1X
PCI-E x1 Slot 1
B
B
A
A
FOXCONN PCEG
Title
PCI Express x1 Slot
Size
C
Date:
5
4
3
2
Document Number
Rev
A
G43M01S1
Sheet
Monday, August 11, 2008
1
30
of
41
5
4
3
2
1
5V_SYS
5V_SYS
3D3V_SYS
3D3V_SYS
-12V_SYS
-12V_SYS
3D3V_SYS
3D3V_SYS
5V_SYS
5V_SYS
12V_SYS
12V_SYS
Note: 20-24 mils
Note: 20-24 mils
PCI2
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
D
25
25
INTFJ
INTHJ
7
CK_33M_PCI1
PREQ0J
AD31
AD29
AD27
AD25
25
CBEJ3
AD23
CBEJ3
AD21
AD19
AD17
25
25
C
CBEJ2
IRDYJ
25
DEVSELJ
25
25
LOCKJ
PERRJ
25
SERRJ
25
CBEJ1
IRDYJ
DEVSELJ
LOCKJ
PERRJ
SERRJ
CBEJ1
AD14
AD12
AD10
AD8
AD7
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
AD5
AD3
AD1
ACK64J
-12V
TCK
GND1
TDO
+5V1
+5V3
INTB#
INTD#
PRSNT1#
RSV2
PRSNT2#
GND2
GND4
RSV4
GND6
CLK
GND7
REQ#
+5V7
AD(31)
AD(29)
GND9
AD(27)
AD(25)
+3.3V2
C/BE#(3)
AD(23)
GND11
AD(21)
AD(19)
+3.3V4
AD(17)
C/BE#(2)
GND13
IRDY#
+3.3V6
DEVSEL#
GND16
LOCK#
PERR#
+3.3V8
SERR#
+3.3V9
C/BE#(1)
AD(14)
GND18
AD(12)
AD(10)
GND20
Slot,PCI CONN
TRST# A1
+12V A2
TMS A3
TDI A4
+5V2 A5
INTA# A6
INTC# A7
+5V4 A8
RSV1 A9
+5V5 A10
RSV3 A11
GND3 A12
GND5 A13
SB3V A14
RESET# A15
+5V6 A16
GNT# A17
GND8 A18
PCI_PME# A19
AD(30) A20
+3.3V1 A21
AD(28) A22
AD(26) A23
GND10 A24
AD(24) A25
IDSEL A26
+3.3V3 A27
AD(22) A28
AD(20) A29
GND12 A30
AD(18) A31
AD(16) A32
+3.3V5 A33
FRAME# A34
GND14 A35
TRDY# A36
GND15 A37
STOP# A38
+3.3V7 A39
SDONE A40
SBO# A41
GND17 A42
PAR A43
AD(15) A44
+3.3V10 A45
AD(13) A46
AD(11) A47
GND19 A48
AD(9) A49
AD(8)
AD(7)
+3.3V12
AD(5)
AD(3)
GND22
AD(1)
+5V8
ACK64#
+5V10
+5V12
C/BE#(0)
+3.3V11
AD(6)
AD(4)
GND21
AD(2)
AD(0)
+5V9
REQ64#
+5V11
+5V13
INTEJ
INTGJ
25
25
25
25
PCI1
INTHJ
INTFJ
3D3V_SB
PCIRSTJ
AD30
7
25
GNT0J
25
PMEJ
25
CK_33M_PCI2
PREQ1J
AD31
AD29
AD28
AD26
AD27
AD25
AD24
IDSEL1
25
CBEJ3
AD22
AD20
AD21
AD19
AD18
AD16
FRAMEJ
TRDYJ
STOPJ
AD17
FRAMEJ
25
25
25
TRDYJ
25
25
DEVSELJ
STOPJ
25
25
25
LOCKJ
PERRJ
25
SERRJ
PAR
25
25
CBEJ1
PSCLK
PSDATA
PAR
AD15
CBEJ3
AD23
AD13
AD11
CBEJ2
IRDYJ
IRDYJ
DEVSELJ
LOCKJ
PERRJ
SERRJ
CBEJ1
AD14
AD12
AD10
AD9
CBEJ0
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
CBEJ0
AD8
AD7
25
AD6
AD4
AD5
AD3
AD2
AD0
AD1
ACK64J
REQ64_1J
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
-12V
TCK
GND1
TDO
+5V1
+5V3
INTB#
INTD#
PRSNT1#
RSV2
PRSNT2#
GND2
GND4
RSV4
GND6
CLK
GND7
REQ#
+5V7
AD(31)
AD(29)
GND9
AD(27)
AD(25)
+3.3V2
C/BE#(3)
AD(23)
GND11
AD(21)
AD(19)
+3.3V4
AD(17)
C/BE#(2)
GND13
IRDY#
+3.3V6
DEVSEL#
GND16
LOCK#
PERR#
+3.3V8
SERR#
+3.3V9
C/BE#(1)
AD(14)
GND18
AD(12)
AD(10)
GND20
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
AD(8)
AD(7)
+3.3V12
AD(5)
AD(3)
GND22
AD(1)
+5V8
ACK64#
+5V10
+5V12
Slot,PCI CONN
TRST# A1
+12V A2
TMS A3
TDI A4
+5V2 A5
INTA# A6
INTC# A7
+5V4 A8
RSV1 A9
+5V5 A10
RSV3 A11
GND3 A12
GND5 A13
SB3V A14
RESET# A15
+5V6 A16
GNT# A17
GND8 A18
PCI_PME# A19
AD(30) A20
+3.3V1 A21
AD(28) A22
AD(26) A23
GND10 A24
AD(24) A25
IDSEL A26
+3.3V3 A27
AD(22) A28
AD(20) A29
GND12 A30
AD(18) A31
AD(16) A32
+3.3V5 A33
FRAME# A34
GND14 A35
TRDY# A36
GND15 A37
STOP# A38
+3.3V7 A39
SDONE A40
SBO# A41
GND17 A42
PAR A43
AD(15) A44
+3.3V10 A45
AD(13) A46
AD(11) A47
GND19 A48
AD(9) A49
C/BE#(0)
+3.3V11
AD(6)
AD(4)
GND21
AD(2)
AD(0)
+5V9
REQ64#
+5V11
+5V13
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
INTGJ
INTEJ
25
25
3D3V_SB
PCIRSTJ
AD30
25
GNT1J
25
PMEJ
25
AD28
AD26
AD24
IDSEL2
AD22
AD20
AD18
AD16
FRAMEJ
TRDYJ
STOPJ
FRAMEJ
25
TRDYJ
25
STOPJ
25
PAR
25
CBEJ0
25
PSCLK
PSDATA
PAR
AD15
C
AD13
AD11
AD9
CBEJ0
AD6
AD4
AD2
AD0
REQ64_2J
25
AD16
IDSEL2
*
AD[31..0]
*
AD[31..0]
AD[31..0]
D
AD[31..0]
25
AD21
R187
330
5V_SYS
12V_SYS
3D3V_SYS
IDSEL1
-12V_SYS
R206
330
*
C176
0.1uF
16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20%
*
EC29
470uF
16V, +/-20%
Dummy
*
EC50
1000uF
+/-20%
*
C226
0.1uF
*
*
C327
0.1uF
16V, Y5V, +80%/-20%
B
C144
0.1uF
PSCLK
*
B
16V, Y5V, +80%/-20%
R329
0
PSDATA R327
0
EC31
100uF
16V, +/-20%
SMB_CLK_RESUME
19,22,23,30,33
SMB_DATA_RESUME 19,22,23,30,33
5V_SYS
12V_SYS
3D3V_SYS
-12V_SYS
5V_SYS
*1
3
5
7
RN16
*1
3
5
7
2
4
6
8
INTDJ
INTBJ
INTAJ
INTCJ
25
25
25
25
2
4
6
8
INTGJ
INTHJ
INTEJ
PREQ1J
25
25
25
25
2
4
6
8
PREQ3J
PREQ0J
PREQ2J
INTFJ
25
25
25
25
8.2K
+/-5%
3
5
7
A
3
5
7
2
4
6
8
EC53
470uF
16V, +/-20%
*
C331
0.1uF
*
C145
0.1uF
*
16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20%
C234
0.1uF
16V, Y5V, +80%/-20%
C147
0.1uF
16V, Y5V, +80%/-20%
REQ64_2J
@SAMSUNG
3D3V_SYS
RN21
8.2K
+/-5%
RN14
*1
REQ64_1J
ACK64J
2.7KOhm
+/-5%
*1
RN17
*1
*
RN53
*
Swap pin
3D3V_SYS
2
4
6
8
3
5
7
Note: EC placement
SERRJ
PERRJ
LOCKJ
STOPJ
8.2K
+/-5%
RN20
8.2K
+/-5%
*1
A
2
4
6
8
3
5
7
DEVSELJ
TRDYJ
IRDYJ
FRAMEJ
8.2K
+/-5%
FOXCONN PCEG
Title
PCI Slot
Size
C
Date:
5
4
3
2
Document Number
Rev
A
G43M01S1
Sheet
Monday, August 11, 2008
1
31
of
41
5
4
3
5V_SB_SYS
-12V_SYS 3D3V_SYS
12V_SYS
5V_SB_SYS
1
5V_SYS
5V_SYS
R559
4.7K
19,29
3D3V_SYS
2
5V_SYS
PWR1
13
14
15
16
17
18
19
20
21
22
23
24
PS_ONJ
D
*
C523
0.1uF
16V, Y5V, +80%/-20%
dummy
+3.3V3 +3.3V1
-12V
+3.3V2
GND4
GND1
PSON
+5V1
GND5
GND2
GND6
+5V2
GND7
GND3
RSVD PWR0K
+5V3 +5V_AUX
+5V4
+12V_1
+5V5
+12V_2
GND8
+3.3V4
*R561
10K
1
2
3
4
5
6
7
8
9
10
11
12
5V_SB_SYS
3D3V_SYS
5V_SYS
12V_SYS
3D3V_SYS
5V_SYS
5V_SYS
D
ATXPWRGD
R572
470
+/-5%
Header_2x12
*
*
19,29
C20
0.1uF
*
C15
0.1uF
*
C16
0.1uF
C19
C588
0.1uF
*
Dummy
0.1uF
*
Dummy
C521
1uF
10V, Y5V, +80%/-20%
A
3D3V_SYS
For EMI.
C
D25
17-215SYGC-S530-E1-TR8
3D3V_SYS
*
5V_SB_SYS
C539
0.1uF
16V, Y5V, +80%/-20%
*
C526
0.1uF
16V, Y5V, +80%/-20%
2
1
*
C550
0.1uF
16V, Y5V, +80%/-20%
Clear CMOS
5V_SYS
12V_SYS
C545
0.1uF
16V, Y5V, +80%/-20%
C522
0.1uF
16V, Y5V, +80%/-20%
*
C525
0.1uF
16V, Y5V, +80%/-20%
*
C524
0.1uF
16V, Y5V, +80%/-20%
23,24 RTCRSTJ
1
2
3
Header_1X3
2
*
1
-12V_SYS
CLR_CMOS
1
2
3
CLR_CMOS
CMOS
Clear
(1-2)
Normal
(2-3)
CLR_CMOS(2-3)
Jumper_2P_Blu
R547
1K
*
C
C
Chassis Intruder Header
IR/CIR CONNECTOR
5V_SYS
INTR
29
5V_SB_SYS
1
2
COPENJ
Header_1X2
C549
0.1uF
16V, Y5V, +80%/-20%
*
Dummy
Dummy
IR/CIR
1
29
IRRX
29
IRTX
5
7
9
2
4
6
8
X
X
CIRRX
29
CIRTX
29
SPEAKER HEADER
Header_2X5_K3K10
SPEAKER
1 Dummy
1
Dummy
*
C547
C551
470pF
470pF
50V, X7R,50V,
+/-10%
X7R, +/-10%
*
*
C543
0.1uF
16V, Y5V, +80%/-20%
3
4
3
4
5V_SYS
Dummy Dummy
Header_1X4_K2
RN52
*1
B
BUZ
+
2
4
6
8
3
5
7
BUZZER
-
100 Ohm
B
Buzzer
5V_SYS
R565
4.7K
5V_SB_SYS
5V_DUAL_USB
1
SIO_BEEP
2
R529
R541
8.2K
D
X
C453
470pF
50V, X7R, +/-10%
dummy
*
C506
470pF
50V, X7R, +/-10%
R272
0 +/-5%
Dummy
C452
470pF
50V, X7R, +/-10%
Dummy
*
*
SLED
19
PBTNJ_SIO
29
C492
1uF
10V, Y5V, +80%/-20%
R564
2.2K
Q62
MMBT3904-7-F
B
*
C527
1uF
16V, Y5V, +80/-20%
BEEP_PC
R598
Dummy
Q31 Dummy
2N7002
G
1K
+/-5%
PWR_LED
29
S
FP_RSTJ
2
4
6
8
Header_2X5_K10
*
28
FP1
1
3
5
7
9
HDD_LED
3
BAT54C
5V_SB_SYS
1
7,10,23
+/-5%
Dummy
2
24
R498
470
+/-5%
470
Dummy
*
R472
0
+/-5%
29
For SEC LED request
E
3D3V_SB
C
Q64
SPKR
23
5V_SYS
PWR_LED(SIO-GP23) programming
(Only For SEC)
S0
dummy
GPI(Default)
S3
0(Low)
S4/S5
GPI(Default)
A
A
FOXCONN PCEG
Title
ATX, FP, MISC Connector
Size
C
Date:
5
4
3
2
Document Number
Rev
A
G43M01S1
Sheet
Monday, August 11, 2008
1
32
of
41
5
4
3
2
1
5V_SYS
*R156
4.7K
SM Bus Bridge
+/-5%
D
R160
29 FANOUT2_SYS1
R325
2.7K
Dummy
SMB_DATA_RESUME
R331
2.7K
Dummy
SMB_CLK_RESUME
*
24 ICH_FANOUT2_SYS1
*
3D3V_SB
0
+/-5%
R153
D
100
+/-5%
12V_SYS
12V_SYS
R421
SMB_DATA_MAIN
C559
0.1uF
R425
2.7K
*R137
4.7K
24 ICH_FANIN2_SYS1
SMB_CLK_MAIN
+/-5%
#REFDE12
2 Dummy
1 COPPER
#REFDE13
2 Dummy
1 COPPER
for Clock Generator/DIMMs
7,34,38 SMB_CLK_MAIN
R148
1
*
C191
47pF Dummy
50V, NPO, +/-5%
SMB_DATA_RESUME 19,22,23,30,31
27KOhm
+/-5%
R150
22K
+/-5%
*
1
0
+/-5%
SYS_FAN
2
4
1
3
+12V
CMD
GND
TACH
Header_1X4 FAN4P
C178
0.1uFDummy
16V, Y5V, +80%/-20%
2
R149
29 FANIN2_SYS1
*
*
Dummy
7,34,38 SMB_DATA_MAIN
D6
LS4148-F
A
*
2.7K
C
3D3V_SYS
2
for PCI-E x16/ICH9/LAN/PCI/PCI-E x1/Over Clock
System FAN 1
SMB_CLK_RESUME 19,22,23,30,31
For ICH10 Fan control, the voltage divider
need to be tuning again.
michael
C
C
5V_SYS
*R443
4.7K
24 ICH_FANOUT1_CPU
+/-5%
*
*
12V_SYS
29 FANOUT1_CPU
R442
0
+/-5%
R436
100
+/-5%
12V_SYS
*
EC28
100uF
16V, +/-20%
C
Dummy
R434
1
*
C411
47pFDummy
50V, NPO, +/-5%
A
27KOhm
+/-5%
R435
22K
+/-5%
*
1
0
+/-5%
CPU_FAN
2
4
1
3
C415
0.1uF Dummy
16V, Y5V, +80%/-20%
+12V
CMD
GND
TACH
Header_1X4 FAN4P
2
R444
*
*
+/-5%
29 FANIN1_CPU
D9
LS4148-F
*R433
4.7K
24 ICH_FANIN1_CPU
2
B
B
CPU FAN
For ICH10 Fan control, the voltage divider
need to be tuning again.
michael
4-pin
pin1.
pin2.
pin3.
pin4.
FAN Header Definition
GND
+12V
Sense
Control
Peak fan current draw: 1.5A
Average fan current draw: 1.1A
Fan start-up current draw: 2.2A
Fan start-up current draw maximum duration: 1.0 second
Fan header voltage: 12V +/- 10%
A
A
FOXCONN PCEG
Title
CPU / System Fan
Size
C
Date:
5
4
3
2
Document Number
Rev
A
G43M01S1
Sheet
Monday, August 11, 2008
1
33
of
41
5
4
3
2
1
TPM Connector
D
3D3V_SYS
D
5V_SYS
TPM
R169
3D3V_SYS
23,29
LCLK
3
LFRAMEn
LAD3
LAD2
8
L_AD2
9
VDD
LAD1
10
L_AD1
L_AD0
11
GND
12
LPCPDJ
NC_4
0
15
NC_2
SERIRQ
16
Dummy
17
GND CLKRUNin
18
19
LPCPDn
20
*
NC_1
14
R201
R215
LAD0
13
*
23
3D3V_SYS
LRESETn NC_3
0
Dummy
3D3V_SB
0
7
*
7,33,38 SMB_CLK_MAIN
R266
Dummy
L_AD3
*R596
R225
KEY
6
10K
Dummy
+/-5%
23,29
GND
5
Dummy
12,23,29 PLTRSTJ
Del XDP Connector
33
33
Dummy
NC_5
23,29
*
R595
23,29
10K Dummy
+/-5%
*
*
CK_33M_TPM
2
*
7
23,29 L_FRAMEJ
1
R176
SERIRQ
0
Dummy
SMB_DATA_MAIN 7,33,38
24,29
Header_2X10_4 (TPM)
C
C
Dummy
5V_DUAL_USB
F1
Fuse 1.5A
1
*
KB / MS Connector
For Samsung request.
050608
L25
FB 300 Ohm
B
2
B
29
KBCLK
29
KBDATA
5
7
* 13
2
4
6
8
*
*
C80
C81
0.1uF
0.1uF
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
dummy
RN2
2.7KOhm
+/-5%
KB_CLK
KB/MS
29
MSCLK
29
MSDATA
KB_DATA
13
16
MS_CLK
MS_DATA
MS_CLK
MS_DATA
12
10
8
7
9
11
6
4
2
14
1
3
5
KB_DATA
KB_CLK
17
UP
A
DOWN
15
A
PS2X2
*
CN1
220pF
50V, NPO, +/-10%
FOXCONN PCEG
Title
KB/MS, TPM
Size
C
Date:
5
4
3
2
Document Number
Rev
A
G43M01S1
Sheet
Monday, August 11, 2008
1
34
of
41
5
4
3
2
1
5V_DUAL_USB
R92
D
@USBX4
F9
Fuse 1.5A
@USBX2
F4
Fuse 2.6A
#F9#F10
10
BACKUSBPWR
USB1
L3
1 Dummy
5
2
6
3
7
4
8
11
R93
15K
*
*
C146
0.1uF
16V, Y5V, +80%/-20%
F10
Fuse 2.6A
*
D
10K
*
23 USB_OCJ_BACK
7
USBP5N_C
6
5
TOP
8
USBP5P_C
Filter 100MHz
1
3
5
7
USBP5P_C
USBP5N_C
USBP4P_C
USBP4N_C
2
4
6
8
0
+/-5%
USBP4P_C
3
USBP4N_C
2
C110
CONN-USBx2
470pF
50V, X7R, +/-10%
C113
@USBX2
1uF
10V, Y5V, +80%/-20%
Place as close as possible
to USB connector.
dummy
1
*
USBP4N
1
6
2
5
3
4
*
2
U6
USBP5N
USBP5P
5V_DUAL_USB
USBP4P
IP4220CZ6
BACKUSBPWR
USB2
41
42
43
44
VCC1
USB0USB0+
GND1
31
32
33
34
VCC2
USB1USB+
GND2
USBP4N_C
USBP4P_C
21
22
23
24
VCC3
USB2USB2+
GND3
USBP5N_C
USBP5P_C
11
12
13
14
VCC4
USB3USB3+
GND4
USBP2N_C
USBP2P_C
L1
1 Dummy
5
USBP3N_C
2
6
USBP3P_C
3
7
4
8
B
USBP3P
USBP3N
USBP2P
USBP2N
*
USBP3P
USBP3N
USBP2P
USBP2N
1
3
5
7
USBP3P_C
USBP3N_C
USBP2P_C
USBP2N_C
2
4
6
8
@USBX4
0
+/-5%
USBP3N
6
2
5
3
4
5V_DUAL_USB
*
470pF
50V, X7R, +/-10%
@USBX4
Third
Down
GND5
GND6
GND7
GND8
GND9
GND10
45
46
47
48
49
50
CONN-USBx4
2
1
IP4220CZ6
A
C109
USBP2P
Second
1
U7
USBP2N
UP
B
Filter 100MHz
RN11
23
23
23
23
C
1
EC24
1000uF
+/-20%
*
9
*
USBP5P
USBP5N
USBP4P
USBP4N
12
C
USBP5P
USBP5N
USBP4P
USBP4N
BOTTOM
4
RN10
23
23
23
23
@USBX4
USBP3P
@USBX4
A
FOXCONN PCEG
Title
LAN / USB Connectors
Size
Document Number
Custom
Date:
5
4
3
2
Rev
A
G43M01S1
Monday, August 11, 2008
Sheet
1
35
of
41
5
4
3
2
1
5V_DUAL_USB
D
D
*
F5
Fuse 1.5A
R240
10K
USB_OCJ_FRONT_3
R242
15K
Del F_USB header 4
*
C309
1uF
10V, Y5V, +80%/-20%
*
EC51
470uF
16V, +/-20%
*
*
23
C278
0.1uF
16V, Y5V, +80%/-20%
C273
0.1uF
16V, Y5V, +80%/-20%
USBPWR_FP3
dummy
F_USB3
1
3
5
7
USBP11N_C
USBP11P_C
X
2
4
6
8
10
USBP10N_C
USBP10P_C
Header_2X5_K9
USB Front Header 3
C
C
L5
1 Dummy
5
2
6
3
7
4
5V_DUAL_USB
23
23
23
23
USBP11P
USBP11N
USBP10P
USBP10N
8
Filter 100MHz
RN22
1
2
3
4
5
6
7
8
*
USBP11P
USBP11N
USBP10P
USBP10N
USBP11P_C
USBP11N_C
USBP10P_C
USBP10N_C
0
+/-5%
*
U16
F6
Fuse 2.6A
USBP11N
USBP10N
*
EC56
1000uF
+/-20%
*
C338
0.1uF
16V, Y5V, +80%/-20%
1
6
2
5
3
4
USBP11P
5V_DUAL_USB
USBP10P
IP4220CZ6
R285
10K
USB_OCJ_FRONT_1_2
R286
15K
B
*
23
C330
0.1uF
16V, Y5V, +80%/-20%
B
USBPWR_FP1
USBPWR_FP1
F_USB1
1
3
5
7
USBP7N_C
USBP7P_C
X
2
4
6
8
10
F_USB2
USBP6N_C
USBP6P_C
1
3
5
7
USBP9N_C
USBP9P_C
X
2
4
6
8
10
*
USBP8N_C
USBP8P_C
C401
0.1uF
16V, Y5V, +80%/-20%
Header_2X5_K9
Header_2X5_K9
USB Front Header 1
5V_SYS
USB Front Header 2
L2
1 Dummy
5
6
1 Dummy
5
3
7
2
6
4
8
3
7
*
Filter 100MHz
4
USBP7P
USBP7N
USBP6P
USBP6N
*
USBP7P
USBP7N
USBP6P
USBP6N
1
3
5
7
USBP7P_C
USBP7N_C
USBP6P_C
USBP6N_C
2
4
6
8
0
+/-5%
A
8
Filter 100MHz
RN35
23
23
23
23
RN24
23
23
23
23
USBP9P
USBP9N
USBP8P
USBP8N
*
USBP9P
USBP9N
USBP8P
USBP8N
1
3
5
7
USBP6N
1
6
2
5
3
USBP9P_C
USBP9N_C
USBP8P_C
USBP8N_C
2
4
6
8
A
4
USBP7P
U19
5V_DUAL_USB
USBP9N
USBP6P
USBP8N
IP4220CZ6
1
6
2
5
3
4
USBP9P
5V_DUAL_USB
FOXCONN PCEG
USBP8P
Title
IP4220CZ6
Front USB Connector
Size
C
Date:
5
EMI
0
+/-5%
U20
USBP7N
2
1
2
0.1uF C319
16V, Y5V, +80%/-20%
L4
4
3
2
Document Number
Rev
A
G43M01S1
Sheet
Monday, August 11, 2008
1
36
of
41
330 +/-5%
L21
RN1
22 KOhm
+/-5%
FB 600 Ohm
L_IR_A
FB 600 Ohm
L_IL_A
LINE-IN
R39
2
22K
+/-5%
r0402h4 SURRBACK_L_M
1
@6JACK
R36
2
22K
+/-5%
r0402h4
1
@6JACK
SURR_L
28
SURR_R
28
CEN
28
LFE
LINE_OUT_R
28
LINE_OUT_L
75
+/-5%
EC12
AUD_FIO_LR27
100uF
75
+/-5%
* *
28
* *
28 SURRBACK_L
AUD_FIO_RR6
100uF
*
L20
*
L23
1
C
L_OR_A
20080617
1
R24
22K
+/-5%
r0402h4
2 Reserved 2
L_OL_A
L_OR_A
AUDIO
FB 600 Ohm
L_OL_A
Front_OUT
A
EC5
EC16
EC15
EC10
@6JACK
R8
100uF @6JACK
@6JACK
R17
100uF @6JACK
@6JACK
R5
100uF @6JACK
@6JACK
R22
100uF @6JACK
@6JACK
R37
100uF @6JACK
@6JACK
R26
100uF @6JACK
AUDIO1ACONN-6 Ports Audio
AUDIO1DCONN-6 Ports AudioGND_AUDIO
@6JACK
@6JACK
AUDIO1BCONN-6 Ports Audio
AUDIO1ECONN-6 Ports Audio
GND_AUDIO
@6JACK
GND_AUDIO
Dummy
L14
L19
L13
L17
L7
L16
*
*
*
*
*
*
MIC1_JD
FB 600 Ohm @6JACK
SURRBACK_R_C
C
F_JD
L_OL_A
L_IR_A
L_IS_A
C
C
1 AUDIOA audio
5
4
3
2
#AUDIO1#AUDIO2
audio
21 AUDIOB
25
24
23
22
#AUDIO1#AUDIO2
audio
31 AUDIOC
35
34
33
32
#AUDIO1#AUDIO2
GND_AUDIO
28
INSULATOR
L1_JD
L_IL_A
Silk Screen
AUDIO
GND_AUDIO
GND_AUDIO
3
5V_SYS
1
2
*
3
1
100uF +/-20%
R79
EC17
100uF +/-20%
R78
EC20
100uF +/-20%
R77
EC19
100uF +/-20%
R76
75
+/-5%
75
+/-5%
33
+/-5%
33
+/-5%
LFE_C
CEN_GND
28
F_AUDIO
1
3
5
7
X
9
RN13
22K
+/-5%
A
CEN_C
GND_AUDIO
3D3V_SYS
GND_AUDIO
SURR_R_C
SURR_GND
28
CONN-JACK
@3JACK
SURR_JD
SURR_L_C
GND_AUDIO
+/-5%
Dummy
2
4
6
GND_AUDIO
10
28
FIO_PRESENCEJ 28
MIC2_JD
28
28
LINE2_JD
28
28
CD_L
CD_GND
CD_R
C106
C90
C77
Header_2X5_K8
for ALC880
CEN_JD
1uF 10V, X5R, +/-10% c0603h9 R56
1uF 10V, X5R, +/-10% c0603h9 R51
Dummy
1uF 10V, X5R, +/-10% c0603h9 R42
Dummy
Dummy
36
GND_AUDIO
audio
41 AUDIOD
45
44
43
42
#AUDIO1#AUDIO2
audio
51 AUDIOE
55
54
53
52
#AUDIO1#AUDIO2
audio
61 AUDIOF
65
64
63
62
#AUDIO1#AUDIO2
1K +/-1%
B
CD_IN
1
2
3
4
1K +/-1%
Dummy
1K +/-1%
Dummy
Header_1X4
Dummy
Dummy
*
2
4
6
8
GND_AUDIO
Header_1X4_K2
*R71
10K
EC18
SURRBACK_L_C
GND_AUDIO
1
3
5
7
AUX_L
28 SURRBACK_JD
GND_AUDIO
3
4
26
GND_AUDIO
A
2
4
6
8
28
AUX_R
C196
22pF
50V, NPO, +/-5%
3
4
For EMI
RN12
2.2K Ohm
+/-5%
****
28
MIC2_R
5
7
* 13
28
MIC2_L
****
28
SPDIF_OUT
SPDIF_OUT
SURRBACK_R_C
SURRBACK_GND
SPDIF_OUT
1 1
***
2
***
Q15
BAT54A
LFE_C
SURRBACK_L_C
L_OR_A
L_OS_A
GND_AUDIO
Q14
CEN_C
FB 600 Ohm @6JACK
GND_AUDIO
BAT54A
1
SURR_R_C
M_L_A
TVS2025-01H-R07F
AUDIO2
28 LINE2_VREFO
2
SURR_L_C
FB 600 Ohm @6JACK
FB 600 Ohm @6JACK
GND_AUDIO
28
1
FB 600 Ohm @6JACK
M_R_A
M_S_A
28
AUDIO1CCONN-6 Ports Audio
AUDIO1FCONN-6 Ports Audio
@6JACK
TVS2025-01H-R07F
TVS2025-01H-R07F
28 MIC2_VREFO
@6JACK
FB 600 Ohm @6JACK
D24
@6JACK
B
2
1
2
1
2
1
2
1
1
2
1
75 SURR_L_M
+/-5%
75 SURR_R_M
+/-5%
75 CEN_M
+/-5%
75 LFE_M
+/-5%
75 SURRBACK_L_M
+/-5%
75 SURRBACK_R_M
+/-5%
28
A
D23
Dummy
C
EC11
CEN_C
A
D31
TVS2025-01H-R07F
EC4
@6JACK
GND_AUDIO
D30
@6JACK
C
R9
22K
+/-5%
r0402h4
Reserved
LFE_C
A
28 SURRBACK_R
FB 600 Ohm
D
GND_AUDIO
28
EC6
2
@6JACK
@6JACK
@6JACK
@6JACK
GND_AUDIO
GND_AUDIO
* * * * * *
SURRBACK_R_M
******
R4
*
*
2
2
100uF
L24
******
EC7
330 +/-5%
*
R7
1
3
5
7
LINE1_L
100uF
2
4
6
8
28
EC14
**
LINE1_R
**
28
1
* * * * * *
1
GND_AUDIO
AUDIO
D
C99 C95 C97 C96 C98 C93
150pF 150pF 150pF 150pF 150pF 150pF
2
22 KOhm
+/-5%
@6JACK
2
MIC-IN
1
AUDIO
M_L_A
2
**
M_R_A
FB 600 Ohm
50V, NPO, +/-5%
FB 600 Ohm
50V, NPO, +/-5%
*
*
50V, NPO, +/-5%
L18
50V, NPO, +/-5%
L22
330 +/-5%
50V, NPO, +/-5%
330 +/-5%
50V, NPO, +/-5%
R1
M_R_A
M_L_A
L_OL_A
SURR_R_C
L_IL_A
SURRBACK_R_C
50V, NPO, +/-5%
R3
100uF
LFE_M
SURR_R_M
CEN_M
SURR_L_M
50V, NPO, +/-5%
100uF
EC9
*
1
3
5
7
50V, NPO, +/-5%
EC8
L_IR_A
L_OR_A
CEN_C
SURRBACK_L_C
LFE_C
SURR_L_C
C75 C94 C47 C62 C100 C101
150pF 150pF 150pF 150pF 150pF 150pF
RN6
2
4
6
8
50V, NPO, +/-5%
MIC1_L
2.2K +/-5%
1
50V, NPO, +/-5%
MIC1_R
28
2.2K +/-5%
2
50V, NPO, +/-5%
28
R33
MIC1_VREFO_R R32
3
1
MIC1_VREFO
MIC1_VREFO
28 MIC1_VREFO_R
**
28
4
**
5
FOXCONN PCEG
Title
HDA Audio Port
GND_AUDIO
Size
Document Number
Custom
Date:
5
4
3
2
Rev
A
G43M01S1
Monday, August 11, 2008
Sheet
1
37
of
41
5
4
3
2
1
Del AMT Led circuit
Del 1.1V MCH CL circuit
(1D8V_STR to 1D1V_MCH_CL)
D
D
1D1V_MCH
1D1V_MCH_CL
RN25
*1
3
5
7
3.8A
2
4
6
8
*
EC54
1000uF
+/-20%
*
*
C581
0.1uF
C328
0.1uF
0
16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20%
stuff for non-AMT
always stuff
Change footprint to 0603
VDDSPD
Del CL PWROK GENERATION
3D3V_SYS
*
Stuff for NON-AMT
0
R518
+/-5%
*
Stuff for NON-AMT
R438
16,17 SMB_CLK_OPTION
0
SMB_CLK_MAIN 7,33,34
C
C
*
Stuff for NON-AMT
R437
16,17 SMB_DATA_OPTION
3D3V_SYS
0
SMB_DATA_MAIN 7,33,34
5V_SYS
*
*
*
C30
C383
C404
0.1uF
0.1uF
0.1uF
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
dummy
dummy
dummy
*
*
C22
0.1uF
16V, Y5V, +80%/-20%
dummy
12V_SYS
*
*
C355
C407
C339
0.1uF
0.1uF
0.1uF
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
dummy
dummy
dummy
*
*
1D1V_MCH
*
C32
C33
0.1uF
0.1uF
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
dummy
dummy
*
*
C35
C36
0.1uF
0.1uF
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
dummy
dummy
*
C37
C21
0.1uF
0.1uF
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
dummy
dummy
B
B
EMI reserved
mh40x80_s
mh40x80_s
mh40x80_s
7
8
9
4
3
2
MH5
Mounting Hole
FD4
FMARK
FD40
IMPEDANCE_2
For Board Top side
1
2
For Board Bottom side
Header_1X2
dummy
A
MH4
Mounting Hole
3D3V_SYS
7
8
9
MH Footprint update to mh48x80_s
for SEC only.
052208
FD6
FMARK
FD40
1
2
FOXCONN PCEG
1
mh40x80_s
FD5
FMARK
FD40
Header_1X2
dummy
1
4
3
2
IMPEDANCE_3
1
6
5
6
5
4
3
2
1
7
8
9
FD1
FMARK
FD40
mh40x80_s
For SEC EMI request
A
FD7
FMARK
FD40
1
Header_1X2
dummy
6
5
4
3
2
FD3
FMARK
FD40
1
1
2
1
7
8
9
1
4
3
2
1
7
8
9
MH2
Mounting Hole
6
5
6
5
6
5
4
3
2
1
7
8
9
MH3
Mounting Hole
1
IMPEDANCE_1
MH1
Mounting Hole
1
3D3V_SYS
MH6
Mounting Hole
IMPEDANCE_4
mh40x80_s
Title
1
2
Header_1X2
dummy
Reserved-1
For CPU
Size
C
Date:
5
4
3
2
Document Number
Rev
A
G43M01S1
Sheet
Monday, August 11, 2008
1
38
of
41
5
4
3
2
1
D
D
5V_SYS
U22
1
3
5
7
9
NRTS2J
NRI2J
NRI2J
CN6
29
220pF 50V, NPO, +/-10%
RN5
29
29
29
29
AFDJ
STBJ
SLINJ
INIT
*1
2
4
6
8
3
5
7
PD[7..0]
PD[7..0]
33
RN4
33
PD0
PD1
PD2
PD3
+/-5%
AFD1STBSLIN1INIT1-
RN3
PD7
PD6
PD5
PD4
8
6
4
2
7
5
3
1
3
5
7
2
4
6
8
*1
Header_2X5_K10
DA1
DA2
DA3
RY1
RY2
RY3
RY4
RY5
DY1
DY2
DY3
RA1
RA2
RA3
RA4
RA5
GND
-12V
10
NRTS1J
NDTR1J
NSOUT1
NRI1J
NCTS1J
NDSR1J
NSIN1
NDCD1J
C
*
A
1
1
5
6
8
2
3
4
7
9
2
11
12V_COM
+12V
VCC
33
2
4
6
8
PRT PORT
12V_SYS
CONN - PrinterPort
NDCD1J
2
ERRP_D1
A
C
-12V_SYS
NDTR1J
CN9
NRTS1J
LS4148-F
C510
0.1uF
INIT1P_D2
220pF 50V, NPO, +/-10%
SLIN1-
*
1
3
5
7
9
NRTS1J
NRI1J
P_D3
NDSR1J
P_D4
NCTS1J
P_D5
NRI1J
2
4
6
8
1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13
P_D0
COM1
NDCD1J
NSOUT1
STBAFD1-
NSIN1
D20
*
GD75232
COM1 HEADER
5
7
+/-5%
P_D7
P_D6
P_D5
P_D4
ACKJ
BUSY
PE
SLCT
NSOUT1
-12V_COM
B
C
LS4148-F
C468
0.1uF
1
16
15
13
19
18
17
14
12
C111
0.1uF
16V, Y5V, +80%/-20%
+/-5%
*
RTS1J
DTR1J
SOUT1
RI1J
CTS1J
DSR1J
SIN1
DCD1J
29
29
29
29
D18
U24
20
29
29
29
29
29
29
29
29
*
P_D4
P_D5
P_D6
P_D7
29 ERRJ
5V_SYS
LS4148-F
2.7K
+/-5%
NCTS2J
C531
0.1uF
NSIN2
NDTR2J
NDSR2J
NCTS2J
2
4
6
8
* 13
P_D0
P_D1
P_D2
P_D3
COM2
NDCD2J
NSOUT2
RN56
2.7K
+/-5%
A
1
1
2
COM2 HEADER
220pF 50V, NPO, +/-10%
RN8
2.7K
+/-5%
NDSR2J
1
*
GD75232
C
2
NRTS2J
R44
2.7K
+/-5%
2
4
6
8
-12V_COM
NDTR2J
CN7
RN7
2.7K
+/-5%
5
7
10
RN23
NSIN2
* 13
-12V
5V_SYS
D1
C
NSOUT2
2
4
6
8
GND
NDCD2J
C509
0.1uF
5
7
11
*
* 13
NRTS2J
NDTR2J
NSOUT2
NRI2J
NCTS2J
NDSR2J
NSIN2
NDCD2J
2
4
6
8
5
6
8
2
3
4
7
9
5
7
1
DY1
DY2
DY3
RA1
RA2
RA3
RA4
RA5
* 13
+12V
DA1
DA2
DA3
RY1
RY2
RY3
RY4
RY5
*
VCC
16
15
13
19
18
17
14
12
2
12V_COM
20
*
RTS2J
DTR2J
SOUT2
RI2J
CTS2J
DSR2J
SIN2
DCD2J
*
29
29
29
29
29
29
29
29
NSIN1
NDTR1J
NDSR1J
NCTS1J
P_D6
220pF 50V, NPO, +/-10%
P_D7
CN8
ACKJ
X
BUSY
Header_2X5_10
PE
SLCT
B
28
27
26
PRT
3D3V_SB
12V_SYS
R562
8.2K
+/-5%
*
16V, Y5V, +80%/-20%
1
NSOUT1
Q65
3
BAV99
2
2
Q35
3
BAV99
D15
LS4148-F
*
CN3
220pF
50V, NPO, +/-10%
NSIN2
Q67
3
BAV99
NSOUT2
BAV99
1
NSIN1
1
3
S
R555
10K
+/-5%
*
CN4
220pF
50V, NPO, +/-10%
A
*
C
2N7002
C513
0.1uF
2
Q32
G
1
C LS4148-F
10K
+/-5%
2
D16 A
R556
LS4148-F
*
C
*
NRI2J
D17 A
*
CN2
220pF
50V, NPO, +/-10%
20080617
2
Q61
NRI1J
23
1
*
D
ICH_RIJ
CN5
220pF
50V, NPO, +/-10%
A
A
-12V_SYS
FOXCONN PCEG
Title
Reserved-2
Size
C
Date:
5
4
3
2
Document Number
Rev
A
G43M01S1
Sheet
Monday, August 11, 2008
1
39
of
41
5
4
3
ICH10 GPIO Summary
D
C
B
A
Name
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
GPIO39
GPIO40
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47
GPIO48
GPIO49
GPIO50
GPIO51
GPIO52
GPIO53
GPIO54
GPIO55
GPIO56
GPIO57
GPIO58
GPIO59
GPIO60
Power Well
3.3V
3.3V
5V
5V
5V
5V
3.3V
3.3V
3.3V_SB
3.3V_SB
3.3V_SB
3.3V_SB
3.3V_SB
3.3V_SB
3.3V_SB
3.3V_SB
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V_SB
3.3V_SB
3.3V_SB
3.3V_SB
3.3V_SB
3.3V_SB
3.3V_SB
3.3V_SB
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V_SB
3.3V_SB
3.3V_SB
3.3V_SB
3.3V_SB
3.3V_SB
3.3V_SB
3.3V_SB
3.3V
3.3V
5.5V
3.3V
5.5V
3.3V
5.5V
3.3V
3.3V_SB
3.3V_SB
3.3V_SB
3.3V_SB
3.3V_SB
Type
I/O
I/O
I/OD
I/OD
I/OD
I/OD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
N/A
N/A
N/A
N/A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2
1
PCI Routing Summary
Description
FP_AUD_DETECT
TACH_1
PIRQE#
PIRQF#
PIRQG#
PIRQH#
TACH_2
TACH_3
Unused(pull up)
WOL_ONLY
Unused(pull-up)
SMBALERT#
LAN_DISABLE#
L_PME#
Unused(pull-up)
CK_PCI_STOP
Unused(NC)
TACH_0
Unused(NC)
SATA_1GP
Unused(NC)
SATA_0GP
Unused(pull-up)
LDRQ1#
AMT_LED
CK_CPU_STOP
S4_STATE#
QRT_STATE0
QRT_STATE1
USB_OC3_FRONT#
USB_OC4_FRONT#
USB_OC4_FRONT#
Unused(NC)
MFG
Unused(NC)
Unused(NC)
SATA_2GP
SATA_3GP
Unused(pull-up)
Unused(pull-down)
USB_OC1_FRONT#
USB_OC2_FRONT#
USB_OC2_FRONT#
USB_OC3_FRONT#
USB_OC_BACK#
USB_OC_BACK#
USB_OC_BACK_LAN#
USB_OC_BACK_LAN#
Unused(pull-up)
DMI_STRAP(pull-down)
REQ_1#
Unused(NC)
REQ_2#
Unused(NC)
REQ_3#
Unused(NC)
Unused(pull-up)
Unused(pull-up)
Unused(pull-up)
USB_OC1_FRONT#
Unused(pull-up)
INTAJ
INTBJ
INTCJ
INTDJ
INTEJ
INTFJ
INTGJ
INTHJ
REG#/GNT#
IDSEL
PCI1
F
G
H
E
D
0
16
C
B
A
FOXCONN PCEG
Title
GPIO / IRQ / IDSEL Map
Size
C
Date:
5
4
3
2
Document Number
Rev
A
G43M01S1
Sheet
Monday, August 11, 2008
1
40
of
41
5
4
3
2
1
Change history
FAB-B change
Date: May 9. 2008
1. PG 07: Change R154, R157 from 33 Ohm to 1K Ohm
2. PG 08: Add PSI control circuit for Wolfdale and Yorkfield CPU
3. PG 10: Add R310 51 Ohm, dummy L34, L35, EC39, R308, R348
4. PG 12: Dummy R185
5. PG 19: Reserve EC73, EC74; Connect VBAT pin of U23 to VCCRTC.
6. PG 29: Dummy R549, R566, RN51
7. PG 32: Add Q67, R597, R598 with 2N3904, 1KOhm, 1KOhm repectively
D
D
8. PG 34: Change KB/MS Power from 5V_SB_SYS to 5V_Dual_USB
9. PG 39: Add RN23, RN26 from 2.7KOhm
EV2 to PV1 change
Date: June 17. 2008
1. PG 09: Dummy R390,R388,C372,R342,R375,R376,C361,R341.Reserve R439,R440,R431,R422,R427,R428,R430,R423,R411,R377,R340,Q44,Q45,Q46,Q47, Change R439 from 10K Ohm to 1K Ohm
2. PG 19: Add D32,R602,R601(dummy) ,Change R477 from 21K Ohm to 20K Ohm,Change R268 from 24.9K Ohm to 15K Ohm
3. PG 25: Change R460 from 10 Ohm to 100 Ohm
4. PG 37: Add D30,D31
5. PG 39: Add Q32,Q35,Q65,Q67
PV1 to PV2 change
Date: July 10. 2008
1. PG 14: Add C603,C604
2. PG 19: Reserve D32,R551,Add R208,C14,R604,R605,R606,R607,R608,Q73,Change C465 from 0.22uF Ohm to 0.47uF
3. PG 23: Add R415
4. PG 29: Add R597(dummy),Reserve R558
PV2 to PR change
Date: July 23. 2008
1. PG 32: Change C527 from 0.1uF to 1uF
C
C
B
B
A
A
FOXCONN PCEG
Title
History
Size
Document Number
Custom
Date:
5
4
3
2
Rev
A
G43M01S1
Monday, August 11, 2008
Sheet
1
41
of
41