CHAPTER 12
Solutions for Exercises
E12.1
(a) vGS = 1 V and vDS = 5 V: Because we have vGS < Vto, the FET is in
cutoff.
(b) vGS = 3 V and vDS = 0.5 V: Because vGS > Vto and vGD = vGS - vDS = 2.5 >
Vto, the FET is in the triode region.
(c) vGS = 3 V and vDS = 6 V: Because vGS > Vto and vGD = vGS - vDS = -3 V <
Vto, the FET is in the saturation region.
(d) vGS = 5 V and vDS = 6 V: Because vGS > Vto and vGD = vGS - vDS = 1 V
which is less than Vto, the FET is in the saturation region.
E12.2
First we notice that for v GS = 0 or 1 V, the transistor is in cutoff, and the
drain current is zero. Next we compute the drain current in the
saturation region for each value of vGS:
K = 21 KP (W / L) = 21 (50 × 10 −6 )(80 / 2) = 1 mA/V 2
iD = K (v GS −Vto ) 2
The boundary between the triode and saturation regions occurs at
v DS = v GS −Vto
v GS (V) iD (mA) v DS at boundary
2
3
4
1
4
9
1
2
3
In saturation, iD is constant, and in the triode region the characteristics
are parabolas passing through the origin. The apex of the parabolas are
on the boundary between the triode and saturation regions. The plots
are shown in Figure 12.7 in the book.
E12.3
First we notice that for v GS = 0 or − 1 V, the transistor is in cutoff, and
the drain current is zero. Next we compute the drain current in the
saturation region for each value of vGS:
1
K = 21 KP (W / L) = 21 (25 × 10 −6 )(200 / 2) = 1.25 mA/V 2
iD = K (v GS −Vto ) 2
The boundary between the triode and saturation regions occurs at
v DS = v GS −Vto .
v GS (V)
iD (mA)
v DS at boundary
-2
-3
-4
1.25
5
11.25
-1
-2
-3
In saturation, iD is constant, and in the triode region the characteristics
are parabolas passing through the origin. The apex of the parabolas are
on the boundary between the triode and saturation regions. The plots
are shown in Figure 12.9 in the book.
E12.4
We have
v GS (t ) = v in (t ) +VGG = sin(2000πt ) + 3
Thus we have VGS max = 4 V, VGSQ = 3 V, and VGS min = 2 V. The
characteristics and the load line are:
2
For vin = +1 we have vGS = 4 and the instantaneous operating point is A.
Similarly for vin = -1 we have vGS = 2 V and the instantaneous operating
point is at B. We find VDSQ ≅ 11 V, VDS min ≅ 6 V, VDS max ≅ 14 V.
E12.5
First, we compute
VG = VDD
R2
= 7V
R1 + R2
1
and K = 2 KP (W / L) = 21 (50 × 10 −6 )(200 / 10) = 0.5 mA/V 2
As in Example 12.2, we need to solve:
V

 1
2
2
VGSQ
+ 
− 2Vto VGSQ + (Vto ) − G = 0
RS K

 RS K
Substituting values, we have
2
VGSQ
−VGSQ − 6 = 0
The roots are VGSQ = -2 V and 3 V. The correct root is VGSQ = 3 V which
yields IDQ = K(VGSQ - Vto)2 = 2 mA. Finally, we have VDSQ = VDD - RSIDQ =
16 V.
E12.6
First we replace the gate bias circuit with its equivalent circuit:
Then we can write the following equations:
K = 21 KP (W / L) = 21 (25 × 10 −6 )(400 / 10) = 0.5 mA/V 2
VGG = 11.5 =VGSQ − Rs I DQ + 20
(1)
3
I DQ = K (VGSQ −Vto ) 2
(2)
Using Equation (2) to substitute into Equation (1), substituting values, and
2
− 16 = 0 . The roots of this equation are
rearranging, we have VGSQ
VGSQ = ±4 V. However VGSQ = −4 V is the correct root for a PMOS
transistor. Thus we have
I DQ = 4.5 mA
and
E12.7
VDSQ = Rs I DQ + RD I DQ − 20 = −11 V.
From Figure 12.21 at an operating point defined by VGSQ = 2.5 V and VDSQ
= 6 V, we estimate
gm =
1 rd =
∆iD
(4.4 − 1.1) mA = 3.3 mS
=
∆v GS
1V
∆iD
(2.9 − 2.3) mA = 0.05 × 10 − 3
≅
(14 - 2) V
∆v GS
Taking the reciprocal, we find rd = 20 kΩ.
4
E12.8
E12.9
gm =
RL′ =
∂iD
∂v GS
=
Q − po int
∂
∂v GS
1
1 rd + 1 RD + 1 RL
(
K (v GS −Vto )2
= 2K V GSQ −Vto
)
Q − po int
= RD = 4.7 kΩ
Avoc = − gm RL′ = −(1.77 mS) × (4.7 kΩ ) = −8.32
E12.10
For simplicity we treat rd as an open circuit and let RL′ = RD RL.
v in = v gs + Rs gmv gs
v o = −RL′ gmv gs
− RL′ gm
v
Av = o =
v in 1 + RL′ gm
E12.11
RL′ = RD RL = 3.197 kΩ
Av =
E12.12
− RL′ gm
vo
− (3.197 kΩ )(1.77 mS)
=
=
= −0.979
1 + (2.7 kΩ )(1.77 mS)
v in 1 + RL′ gm
The equivalent circuit is shown in Figure 12.28 in the book from which we
can write
5
v in = 0
v gs = −v x
ix =
Solving, we have
Ro =
E12.13
vx vx
v
v
+
− gmv gs = x + x + gmv x
RS rd
RS rd
vx
1
=
1
1
ix
gm +
+
RS rd
Refer to the small-signal equivalent circuit shown in Figure 12.30 in the
book. Let RL′ = RD RL .
v in = −v gs
v o = −RL′ gmv gs
Av = v o v in = RL′ gm
iin = v in Rs − gmv gs = v in Rs + gmv in
Rin =
v in
1
=
iin
gm + 1 Rs
If we set v (t) = 0, then we have vgs = 0. Removing the load and looking
back into the amplifier, we see the resistance RD. Thus we have Ro = RD .
E12.14
See Figure 12.34 in the book.
E12.15
See Figure 12.35 in the book.
Answers for Selected Problems
P12.3*
(a) Saturation iD = 2.25 mA
(b) Triode iD = 2 mA
(c) Cutoff iD = 0
6
P12.4*
iD
vGS = 4 V
3V
2V
vDS
P12.11* Vto = 1.5 V
K = 0.8 mA/V2
P12.15* v GS = −2.5 V
P12.17*
The load line rotates around the point (VDD, 0) as the resistance changes.
P12.19* The gain is zero.
P12.21* RDmax = 3.778 kΩ
7
P12.27* IDQ = 3.432 mA
VDSQ = 16.27 V
P12.28* RS = 3 kΩ
R2 = 2 MΩ
P12.29* Rs = 400 Ω
R1 = 2.583MΩ.
P12.34* VDSQ = VGSQ = 5.325 V
IDQ = 4.675 mA
P12.40* gm = 2KVDSQ
P12.41* rd =
2K (VGSQ
1
−Vto −VDSQ )
P12.50* (a)
VGSQ = 3 V
I DQ = 10 mA
gm = 0.01 S
(b)
Av = −5
Rin = 255 kΩ
Ro = 1 kΩ
P12.53* Ro =
1
= 253 Ω
1 RD + gm
P12.56* RS = 3.382 kΩ
Av = 0.6922
Rin = 666.7kΩ
Ro = 386.9 Ω
8