Accelerating time domain
simulations of PLLs
Giovanni De Luca
Dept. of Mathematics and Computer Science,
Technische Universiteit Eindhoven, Eindhoven (NL)
May 10, 2016
G. De Luca - SPI2016 (Turin)
Where innovation starts
Outline
Introduction
Motivation
Innovation
Methodology
Experiment
Conclusions & Perspectives
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Outline
Introduction
Motivation
Innovation
Methodology
Experiment
Conclusions & Perspectives
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Introduction: The Project
ASIVA14:
Analog SImulation and Variability Analysis for 14nm designs
http://www.itn-asiva14.eu
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Introduction: Nearly-Periodic Circuits
Nearly-periodic circuits: PLLs, SMPSs, ∆ − Σ modulators
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Introduction: Nearly-Periodic Circuits
Slow/fast-varying, analog/digital-like waveforms
Need of accurate pre/post-layout SPICE simulations
Noise-free and noisy time simulations required
Slow Time-to-Market
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Introduction: PLLs
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Outline
Introduction
Motivation
Innovation
Methodology
Experiment
Conclusions & Perspectives
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Motivation: The Problem
Solve for t ∈ [t0 , tend ] set of DAEs (from KCLs)
 dq(x(t))

 dt + i(x(t)) = b(t) + bnoise (t)

x(t ) = x ∈ Rn
0
0
Designers need to extract:
-
Power consumptions (components/battery’s life)
Locking time (PLL’s proper working condition)
Phase noise (spectral purity)
Jitter (time domain signal’s purity)
Even if n relatively small, D&V process might take
weeks/months for accurate transistor-level simulations
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(1)
Motivation: State-of-the-Art
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Behavioral simulation:
- “Analysis of VCO phase noise in charge-pump PLLs”, Maffezzoni
and Levantino, 2012
- “TP-PPV: piecewise nonlinear, time-shifted oscillator macromodel
extraction for fast, accurate PLL simulation”, Lai and
Roychowdhury, 2006
Transistor-level simulation:
- “General envelope-transient formulation of PLLs using three time
scales”, Sancho et al., 2004
- “Adaptive multi-rate wavelet method for circuit simulation”,
Bittner and Brachtendorf, 2014
Unique, automated method for complete D&V process is desired
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Outline
Introduction
Motivation
Innovation
Methodology
Experiment
Conclusions & Perspectives
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Innovation
Unique method to extract all factors of interest
As accurate as and faster than transistor-level simulation
Targeted to industrial integer-N PLLs (with high N)
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Outline
Introduction
Motivation
Innovation
Methodology
Experiment
Conclusions & Perspectives
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Methodology: Ingredients
Goal: Reduce number of time steps during simulation (due
to highest signal’s frequency)
Method relies on oscillators’ perturbation theory (phase
deviation dominates, [Demir et al., 2000]):
- deterministic perturbation on vc (t)
- stochastic perturbations (noise) on each oscillator’s
node/component
Replace VCO and divider (VCODIV) with phase
macromodel ⇒ remove the highest signal’s frequency
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Methodology: Phase Macromodel
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Methodology: Phase Macromodel
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Methodology: Phase Macromodel
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Methodology: Phase Macromodel’s Interfaces
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Equivalent current/voltage sources at VCODIV’s pins
Given a VCODIV steady-state (SST) solution i(t) = i(t + Tout ), Tout > 0, then
√

PNh

i(t + j(t)) = k=−N
Ik e −1k·θtot (t)


h



θ (t) = 2π fout · t + ∆θ(t)

 tot

∆θ(t) = 2π f · j(t)
out
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Methodology: Phase Macromodel’s Interfaces
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Harmonic Balance computes an SST solution of VCODIV at
specific vc (t) = Vc,sst (Fourier coefficients and oscillating
frequency)
But which Vc,sst ?
And which equation for ∆θ(t) ?
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Methodology: Phase Deviation Equation
Building the macromodel before simulation
PLL’s core: fvco VS vc curve
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Methodology: Phase Deviation Equation
Building the macromodel before simulation
PLL’s core: fvco VS vc curve
Extract SSTi at vc (t) = Vc,sst,i
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Methodology: Phase Deviation Equation
Building the macromodel before simulation
PLL’s core: fvco VS vc curve
Extract SSTi at vc (t) = Vc,sst,i
Oscillator’s sensitivity: Kmacro,i =
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∆ fvco,i
∆Vc,sst,i
(local)
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Methodology: Phase Deviation Equation
Building the macromodel before simulation
Macromodel’s core: ∆ fvco,i = Kmacro,i · ∆Vc,sst,i
Extract SSTi at vc (t) = Vc,sst,i
Oscillator’s sensitivity: Kmacro,i =
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∆ fvco,i
∆Vc,sst,i
(local)
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Methodology: Phase Deviation Equation
Building the macromodel before simulation
Macromodel’s core: ∆ωvco,i = 2πKmacro,i · ∆Vc,sst,i
Extract SSTi at vc (t) = Vc,sst,i
Oscillator’s sensitivity: Kmacro,i =
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∆ fvco,i
∆Vc,sst,i
(local)
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Methodology: Phase Deviation Equation
Building the macromodel before simulation
Macromodel’s core:
d
∆θc,vco (t)
dt
= 2πKmacro,i · ∆Vc,sst,i
Extract SSTi at vc (t) = Vc,sst,i
Oscillator’s sensitivity: Kmacro,i =
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∆ fvco,i
∆Vc,sst,i
(local)
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Methodology: Phase Deviation Equation
Building the macromodel before simulation
Macromodel’s core:
d
∆θc,vco (t)
dt
= 2πKmacro (Vc,sst,i ) · ∆Vc (t)
Extract SSTi at vc (t) = Vc,sst,i
Oscillator’s sensitivity: Kmacro (Vc,sst,i ) = Kmacro,i and ∆Vc (t) = vc (t) − Vc,sst,i , for
vc (t) ∈ [Vc,l , Vc,l+1 ] (global)
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Methodology: Phase Deviation Equation
Building the macromodel before simulation
Macromodel’s core:
d
∆θc,div (t)
dt
=
2πKmacro (Vc,sst,i )
N
· ∆Vc (t)
Extract SSTi at vc (t) = Vc,sst,i
Oscillator’s sensitivity: Kmacro (Vc,sst,i ) = Kmacro,i and ∆Vc (t) = vc (t) − Vc,sst,i , for
vc (t) ∈ [Vc,l , Vc,l+1 ] (global)
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Methodology: Macromodel’s Equations
PLL’s/Macromodel’s interfaces:
√

P h

i(t + j(t)) = N
Ik e −1k·θtot (t)


k=−N
h

Rt


θ
(t)
=
2π
f
(τ)dτ
+ ∆θc,div (t)
tot
out

0


∆θ(t) = 2π f · j(t)
out
Phase deviation equation:
d
2πKmacro (Vc,sst,i )

· ∆Vc (t)

dt ∆θc,div (t) =
N




∆θc,div (0) = 0



Kmacro (Vc,sst,i ) = Kmacro,i



∆V (t) = v (t) − V
c
c
c,sst,i
Supply currents equation:



IDC (t) = IDC,i + smacro · (vc (t) − Vc,sst,i )

−IDC,i

smacro = VIDC,i+1 −V
c,sst,i+1
c,sst,i
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when vc (t) ∈ [Vc,l , Vc,l+1 ]
when vc (t) ∈ [Vc,l , Vc,l+1 ]
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Methodology: Noise Analysis (VCO)
Building the macromodel before simulation
Sθ,vco (∆ f ) =
1
∆f2
·(
c f l,vco
∆f
+ cwh,vco ) (freq domain, power)
Compute c f l,vco and cwh,vco from extracted Sθ,vco (∆ f ) at some ∆ f
Rt
∆θnoise,vco (t) = 2π 0 (n f l,vco (c f l,vco , τ) + nwh,vco (cwh,vco , τ))dτ (time domain)
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Methodology: Noise Analysis (Divider)
Building the macromodel before simulation
Sθ,div (∆ f ) =
c f l,div
∆f
+ cwh,div (freq domain, power)
Compute c f l,div and cwh,div from extracted Sθ,div (∆ f ) at some ∆ f
∆θnoise,div (t) = n f l,div (c f l,div , t) + nwh,div (cwh,div , t) (time domain)
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Methodology: Macromodel’s Equations
PLL’s/Macromodel’s interfaces (with noise):
√

PNh

i(t + j(t)) = k=−N
Ik e −1k·θtot (t)


h

Rt

∆θ
(t)

θtot (t) = 0 2π fout (τ)dτ + ∆θc,div (t) + noise,vco
+ ∆θnoise,div (t)

N


∆θ(t) = 2π f · j(t)
out
Phase deviation equation:

2πKmacro (Vc,sst,i )
d


· ∆Vc (t)

N
 dt ∆θc,div (t) =



∆θc,div (0) = 0


Kmacro (Vc,sst,i ) = Kmacro,i




∆Vc (t) = vc (t) − Vc,sst,i
when vc (t) ∈ [Vc,l , Vc,l+1 ]
Noise equations:
Rt


∆θnoise,vco (t) = 2π 0 (n f l,vco (c f l,vco , τ) + nwh,vco (cwh,vco , τ))dτ




∆θnoise,div (t) = n f l,div (c f l,div , t) + nwh,div (cwh,div , t)




∆θ (t) = N · ∆θ (t) + ∆θ
pll
c,div
noise,vco (t)
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(2)
(3)
(4)
Outline
Introduction
Motivation
Innovation
Methodology
Experiment
Conclusions & Perspectives
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Experiment: Integer-N PLL
N = 25
1271 equations, 1009 active device, BSIM3 model
tend = 20µ sec for noise-free simulation
tend = 1m sec for noise simulation
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Experiment: Integer-N PLL
re f = 100MHz, then sweep to re f = 115MHz
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Experiment: Integer-N PLL
re f = 100MHz, then sweep to re f = 115MHz
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Experiment: Integer-N PLL
re f = 100MHz, then sweep to re f = 115MHz
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Experiment: Integer-N PLL
re f = 100MHz, then sweep to re f = 115MHz
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Experiment: Integer-N PLL
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Experiment: Integer-N PLL
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Experiment: Integer-N PLL
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Table 1: Accuracy of the factors of interest
tlock
PO
PD
DB(Sθ,pll )
Data
1.9739µ
−5.8761m
−2.3510m
1
Macro
1.9740µ
−5.8713m
−2.3156m
2
Error
5 · 10−5 %
8 · 10−4 %
1.5%
≤ 2DB
1
2
[−82.65, −90.00, −109.00] @[1, 10, 100]MHz from fvco .
[−82.40, −88.00, −107.00] @[1, 10, 100]MHz from fvco .
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Experiment: Integer-N PLL
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Table 2: Simulation time results
TRAN
# retained steps
tbuild (min)
tsim (min)
speedup
Data
3.7 · 106
-
131
-
Macro
3.8 · 105
1.5
10
11.4x
NOISE
# retained steps
tbuild (min)
tsim (hour)
speedup
8
Data
2.6 · 10
-
338
-
Macro
2.1 · 107
1.5
18.5
18.3x
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Outline
Introduction
Motivation
Innovation
Methodology
Experiment
Conclusions & Perspectives
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Conclusions & Perspectives
Conclusions:
- Macromodel built through standard simulator analyses (SST,
Verilog-A)
- Accurate method to extract factors of interest
- Faster than transistor level (for noise analysis, speedup close to
N×)
Next steps:
- Error analysis on the construction of macromodel
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Thank You
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Bibliography (Some)
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“Analysis of VCO phase noise in charge-pump PLLs”, Maffezzoni and
Levantino, 2012
“TP-PPV: piecewise nonlinear, time-shifted oscillator macromodel extraction
for fast, accurate PLL simulation”, Lai and Roychowdhury, 2006
“General envelope-transient formulation of PLLs using three time scales”,
Sancho et al., 2004
“Adaptive multi-rate wavelet method for circuit simulation”, Bittner and
Brachtendorf, 2014
“Phase noise in oscillators: a unifying theory and numerical methods for
characterization”, Demir et al., 2000
“Steady-state analysis of voltage and current controlled oscillators”, Mehrotra
et al., 2005
“Rigorous RF and microwave oscillator phase noise calculation by envelope
transient technique”, Ngoya et al., 2000
“A unified approach of PM noise calculation in large RF multitone
autonomous circuits”, Bolcato et al., 2000
“Eldo User Manual”, Mentor Graphics Corp., 2015
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Experiment: Integer-N PLL
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